Isotropic TFT Characteristics in the {100}-Oriented Grain-Boundary-Free Laser-Crystallized Si Thin Films

Abstract

Isotropic TFT characteristics are realized in the {100}-oriented grain-boundary-free 60 nm thick Si film obtained by the continuous-wave laser lateral crystallization, where the grain- and sub-boundaries are defined as the crystallographic boundaries having misfit angles of θ > 15° and θ < 15°, respectively. Sub-boundaries are observed in the film parallel to the scan directions; the misfit angles were 5–10° and the sub-boundary density was 0.02956 μm⁻¹. Sub-grains, joined by the sub-boundaries, have widths of 8 ~ 69 μm. The cumulative distributions of mobility, threshold voltage, and subthreshold swing agree well between the parallel and perpendicular TFTs in the film, where parallel or perpendicular means the source-to-drain directions to the laser scan direction. The maximum mobilities of the parallel and perpendicular TFTs are 695 and 663 cm²/Vs, respectively. The trap-state density N_T in the sub-boundaries estimated from the product of the bond efficiency η and the dangling bond density decreases by two decades from those of the grain boundaries. A new carrier transport model of the current flow across the sub-boundary is proposed instead of the thermionic emission model for the grain boundaries.

1. Introduction

As is well known, various semiconductor materials for thin-film-transistors (TFTs) have been studied, such as amorphous-Si, organic semiconductors, oxide semiconductors, laser-crystallized Si, etc., in order to realize flat panel displays (FPDs) [1], smart sensors [2] and wearable devices [3,4] on glass or flexible substrates. The mobility of the laser-crystallized TFTs is >200 cm²/Vs, and those of other TFTs are <60 cm²/Vs [4,5]. The laser-crystallized Si TFTs have another advantage in making CMOS circuits, enabling low standby power consumption. Pulse excimer laser annealing (ELA) was developed to crystallize amorphous-Si films on SiO₂-coated glass for application in flat panel displays (FPDs) [6,7]. Continuous-wave laser lateral crystallization (CLC) has also been developed for SiO₂-coated glass [8,9,10,11]. ELA has been the sole commercialized technology of laser crystallization thus far. CLC has been a candidate for high-end applications, such as monolithic three-dimensional integrations, high-speed smart sensors, and systems on FPDs because thin-film-transistors (TFTs) on CLC films show a potential to realize high mobilities comparable to those of bulk field-effect transistors (FETs), even with the crystallization on insulating substrates at room temperature. However, the film obtained by the conventional CLC with the elliptic line-beam comprised grain boundaries (GBs) of a misfit angle θ > 15°, where randomly oriented narrow grains were observed longitudinally extending along the scan having surface orientations of both {100} and {110} in the crystallized film [9]. It is required to obtain GB-free CLC films to realize isotropic-high mobility in TFTs comparable to those of bulk FETs.

The maximum parallel TFT mobility of 925 cm²/Vs but the low perpendicular TFT mobility of 480 cm²/Vs were observed for the film crystallized with the six-times overlapped CLC [12], where parallel or perpendicular means the source-to-drain directions of TFTs to the laser scan direction. The title of the paper claimed that the TFTs were fabricated on the film comprising low-angle GBs, but the EBSD picture in the paper clearly shows that this film contained GBs with 15° < θ < 180° as well [12]. The reported small ratio of the perpendicular to parallel mobilities of 0.52 [12] suggests the existence of large-angle GBs in their film.

The remaining GBs in the conventional CLC elongated parallel to the scan direction results in anisotropy in the electrical characteristics of TFTs. The mobilities of the perpendicular TFTs were 60–70% of those of the parallel TFTs in the conventional CLC films, with GBs of θ > 15° [9]. It is required to remove the GBs from the active region of the TFT in order to realize the isotropic electrical characteristics of the TFTs and to increase mobility further.

The CLC crystallization, using a micro-chevron-laser-beam [13], made narrow stripes of 5–10 μm width and a few mm in length. The surface orientation of the stripe tended to rotate continuously with the scan travel, although GBs (5° < θ < 65°) were not detected; however, twin boundaries of Σ3 with a θ of 60.0 or 70.5° across the stripes were frequently observed as the scan travel at a period of 50 μm [13,14]. The mobility of the parallel TFT was 548 cm²/Vs, but the perpendicular TFT was not reported in this narrow stripe. We use the terminologies GBs and sub-boundaries (sub-Bs) [15] and define GBs as the boundaries having θ > 15° and sub-Bs having θ < 15°, according to the generally accepted criterion of θ = 15° [16].

Recently a GB-free stripe of 80–200 μm width having 99.8% {100} surface orientation within 10° has been obtained by a single scan of CLC at room temperature substrates of quartz [11,17,18,19,20,21,22] and glass [23] in air. A highly uniform line beam was scanned at an optimized laser power around the threshold of lateral growth. These films have the {100} orientations in the scan and transverse directions, as well as surface normal. These wide {100}-oriented GB-free stripes extend stably to more than 3 mm [21] or 10 mm [22] in length, so long as the scan continues. The {100} surface texture was obtained by CLC on polyimide substrates as well [24]. Selective CLC crystallization of the TFT-active area is effective in reducing energy consumption and improving the throughput of crystallization [8,18] because the TFT-active area occupies a tiny portion in the whole LSI or FPD substrate, and the remaining Si film in the whole substrate is etched off for the wiring and light-emitting cell areas.

We have observed the isotropic mobility of TFTs fabricated in GB-free films for the first time [25]. In the present paper, we describe that the effect of the remaining sub-Bs on the TFT characteristics is negligible. We characterize sub-Bs in the GB-free films and demonstrate isotropic characteristics of TFTs, including the threshold voltage and subthreshold swing of TFTs, as well as mobility. Suppressed leakage currents are also described. The trap-state density at the sub-Bs is estimated by multiplying a dangling bond efficiency by the calculated dangling bond density, which is smaller than those of GBs by two orders of magnitude. We propose a new current model across the sub-Bs, which is different from the conventional thermionic emission model.

2. Experimental

An undoped 60 nm thick a-Si film was deposited on fused quartz by using inductively-coupled plasma chemical vapor deposition (ICP-CVD) with SiH₄ at 250 °C and 6.8 Pa. Then, a 123 nm thick SiO₂ cap was deposited by ICP-CVD with tetraethoxysilane at 300 °C and 80 Pa. After the dehydrogenation annealing at 550 °C for 1 h in N₂, the a-Si was crystallized by an unseeded single-scanned CLC with a frequency-doubled diode-pumped solid-state Nd:YVO₄ laser at a wavelength of 532 nm, keeping the substrate at room temperature in air. A highly uniform line beam was used [17,18,19,20,21,22,23,24]. The spot size was 492 μm (long axis) × 8 μm (short axis) with a top-flat beam shape for the long axis and Gaussian for the short axis, which was generated by utilizing a diffractive optical element (DOE). The scans were performed perpendicular to the long axis at a 12 mm/s velocity. The laser power was 4.2 W for the GB-free CLC growth and 4.0 W for the grained CLC growth. After the cap removal, the crystal quality was characterized by electron backscatter diffraction (EBSD). The EBSD was taken at 15 kV and a tilt angle of 70° using the Hitachi SU6600 scanning electron microscope (SEM) equipped with an EBSD module from EDAX.

Top-gate TFTs were fabricated, as shown in Figure 1. The channel region was undoped. The laser-crystallized Si islands were patterned by plasma etching. A 120 nm thick gate SiO₂ was deposited by ICP-CVD with tetraethoxysilane at 300 °C and 80 Pa. The gate electrodes were formed by 230 nm thick Mo sputtering and photolithography. Phosphorus ions were implanted at 90 keV to a dose of 4 × 10¹⁵ cm⁻² at the source and drain regions. Activation annealing was performed at 550 °C for 1 h in N₂. Contact holes were opened, and the source and drain electrodes were formed by 230 nm thick Mo sputtering and lift-off. Finally, the N₂-H₂ annealing was performed at 450 °C for 1 h. The channel length, L, of the TFTs was 10 μm, and the width, W, was 5 μm. The TFT characteristics were measured with a Precision 4156C semiconductor parameter analyzer. The effective field-effect mobilities μ were derived from the following equation of the linear region assuming a uniform carrier distribution in the channel even with the sub-boundaries at a sufficiently small drain voltage, V_D, of 0.1 V.

I_D = μ C_ox (W/L)·(V_G − V_T) V_D

(1)

where I_D is the drain current, C_ox is the gate capacitance per unit area, V_G is the gate voltage, V_T is the threshold voltage, and V_D is the drain voltage.

3. Results

3.1. The Sub-Grains (Sub-G) and Sub-Boundaries (Sub-B) in the GB-Free Area

Figure 2 shows the misfit boundaries along the laser scan of the {100}-oriented GB-free film. Figure 2a shows the GBs with a misfit angle of θ > 15°. A 203 μm wide GB-free stripe was obtained along the laser scan. Figure 3 shows the GB-Free region is oriented to {100} in all the three directions of surface normal, scan, and transverse directions simultaneously. The twin boundaries were occluded in these GB-free regions.

Figure 2b shows all the boundaries with θ > 2°, including both the sub-Bs and GBs. Figure 2b shows five straight sub-Bs with a θ of 5 ~ 10° in the GB-free region running parallel to each other and the scan direction. The density of these sub-Bs is 0.02956 lines μm⁻¹. Sub-grains (sub-Gs) joined by the sub-Bs have widths of 8 ~ 69 μm. A few tiny lineages with limited length and θ = 2 ~ 5° are observed.

In the outside edges of the 203 μm wide {100}-oriented GB-free region, two grained CLC stripes of 118 or 149 μm in width were observed. The EBSD Inverse Pole Figure (IPF) analysis showed that these side regions also have a {100} orientation in the surface normal direction but comprised many grains with different in-plane orientations of {100}, {310}, {210}, {320}, and {110} in the scan or transverse direction, as shown in Figure 3.

The sub-Bs detected in Figure 2b are tilt boundaries [15] because the surface orientation is kept uniformly at {100}, as shown in Figure 3. The {100} orientation in the surface normal is realized by the minimum interfacial energy between Si {100} and SiO₂, and the {100} in the scan direction is by the fastest growth direction of <100> in Si [11]. The {100} in the transverse direction is fixed uniquely after the orientation determination of the surface normal and scan directions. The misfit angle θ profiles along the path, indicated by an arrow in Figure 2b, are shown in Figure 4. The point-to-point curve shows almost the same absolute misfit angle θ in each sub-B, and it is obvious that the neighboring sub-Gs tilt alternately in opposite directions from the point-to-origin curve.

For the sub-B, the crystallographic structure is described by a dislocation array [15,16] because of the small misfit angle of θ < 15°. We have found that there are two types of sub-Bs in the GB-free films. Figure 5 shows schematic views of the tilt boundaries described by the edge dislocation arrays. Figure 5a shows the dislocation arrays in the GB-free film. Neighboring sub-Bs are formed by dislocations with opposite polarities to each other with the same (100) surface normal axis, resulting in almost the same in-plane orientations throughout the film, as shown in Figure 3b,c. If all the sub-Bs comprise dislocations with the same polarities, the orientation in the scan direction of the film bends to one direction by the dislocation arrays, as shown in Figure 5b.

3.2. TFT Alignment in the Laser Scanned Stripe and Contact Resistance

Figure 6 shows the TFTs’ alignment to the laser scan: (a) just after the island patterning and (b) after the gate patterning. The parallel and perpendicular TFTs were fabricated alternately in the same laser scan with a period of 412 μm. The channel regions were placed in the GB-free stripe having a 203 μm width. The channel length and width were 10 μm and 5 μm, respectively, for both the parallel and perpendicular TFTs. The n⁺ wiring and contact regions were placed inside the grained or GB-free CLC stripes with a total 470 μm width. Good contact characteristics were obtained if the contacts were formed inside the grained CLC region. The phosphorus activation was carried out by the solid-phase epitaxial growth from the bottom crystalline Si layer by the 550 °C furnace annealing; the amorphous layer is solely induced by ion implantation near the front surface of the 60 nm Si film.

3.3. TFT Characteristics in the GB-Free CLC Region

The measured distributions of the electrical characteristics of TFTs show no difference between the parallel and perpendicular TFTs. The cumulative distributions of the obtained effective field-effect mobility, threshold voltage, and subthreshold swing agree well between the parallel and perpendicular TFTs in the GB-free films, as shown in Figure 7a–c, respectively. The remaining sub-boundaries in the {100}-oriented GB-free region did not affect the electrical characteristics of the TFTs. If the sub-boundaries did affect the electrical characteristics, the obtained cumulative TFT mobilities would differ between the parallel and perpendicular TFTs. A small SS value of 60 mV/dec around the theoretical limit at room temperature was obtained. Figure 7a gives

μ _‖ = μ _┴

(2)

where μ _‖ and μ _┴ are the effective field-effect mobilities of the parallel and perpendicular TFTs, respectively.

Figure 8 shows the electrical characteristics of the parallel and perpendicular TFTs with the maximum effective mobilities. The maximum mobilities are almost the same between the parallel and perpendicular TFTs; 695 cm²/Vs was obtained for the parallel TFT, and 663 cm²/Vs was obtained for the perpendicular TFT. The steep peak observed in the μ–V_G curve is similar to the conventional MOSFETs [26,27,28]. The I_D–V_G curve becomes steeper when the low substrate impurity concentration becomes low following the universal curve [26,27] and when the trap-state density in the boundary becomes low [28].

Figure 9 shows the variations in the drain current I_D versus gate voltage V_G characteristics and the mobility μ versus V_G characteristics in the GB-free TFTs. The characteristics between the perpendicular and parallel TFTs show the same tendency, including variations in these characteristics. The observed TFT variations are independent of the current direction of the scan. The leakage currents of most TFTs are well suppressed below 1 fA, but some devices accidentally show a larger leakage current of 0.1 pA. The increase in the leakage current observed at a high negative gate voltage from −20 V to −15 V is due to the conventional band-to-band tunneling.

Figure 10 shows the drain leakage current dependence on the drain voltage. The drain leakage current increases with the increasing drain voltage V_D. This increase shows the usual leakage current characteristics due to the band-to-band tunneling current at the drain. This tendency also confirms that the small leakage current observed at the V_D from −15 V to −5 V is not due to the current inversion. Figure 11 shows the drain current I_D versus drain voltage V_D characteristics. No anomaly is observed in these characteristics.

3.4. TFT Characteristic in the Grained CLC Region

Distributions of the electrical characteristics were also studied for the grained CLC film, in comparison, which was crystallized at a lower power by 0.2 W than the optimized power for GB-free crystallization. A preferential {100} surface orientation was obtained, as shown in Figure 12a. Many small grains existed, having different orientations of {100}, {310}, {210}, {320}, and {110} in the scan directions, as shown in Figure 12b. The corresponding GBs (15° < θ) are shown in Figure 12c, and the sub-Bs (2° < θ < 15°) overlapped to GBs are shown in Figure 12d. The cumulative distributions of the electrical characteristics in the grained TFTs differed between the parallel and perpendicular TFTs, as shown in Figure 13.

3.5. Comparison of Mobility Ratio Fabricated in the Present GB-Free CLC Film with Those in Other CLC Films

Figure 14 shows the ratio of the maximum effective mobilities of the perpendicular TFTs to that of the parallel TFTs. This ratio is a figure of merit for mobility isotropy. The TFTs obtained in the present GB-free films show the greatest ratio of 0.95 and a relatively large parallel mobility value of 695 cm²/Vs, even with the thin 60 nm thick Si film. The highest parallel mobility was obtained by the six-times overlapped CLC on a 150 nm thick Si film [12]; however, the ratio of the TFTs was as low as 0.5 [12] due to the inferior mobility value of the perpendicular TFTs resulting from the existence of the grain boundaries and twin boundaries having a θ > 15°. All the conventional CLCs with a 50 nm Si thickness show a ratio of less than 0.5 [9]. The ratio and mobility in the conventional CLC generally increase with the increasing Si film thickness due to the increase in grain size, as shown in Figure 14.

4. Theoretical Considerations and Its Comparison with Experimental Results

4.1. Trap-State Density at the Sub-Boundaries

The tilt sub-B is described by an edge dislocation array aligned in the sub-B. The distance D between the dislocations is given by

D = b/(2 sin (θ/2))

(3)

~ b/θ

(4)

where b is the magnitude of the Burgers vector and θ is the misfit angle of the sub-B in the radian unit [15]. The dislocation distance D in the present sub-B is 2 ~ 4 nm for θ = 5 ~ 10°, as shown in Figure 15. If we define the length s as a projected length of a unit cell along the dislocation line to the surface normal axis of the film, the dangling bond density per unit length is given by 2/s, where s is equal to the lattice constant of 0.543 nm. The dangling bond density in the sub-B is calculated from D and s as

Dangling bond density = 2/(D · s)

(5)

           = 2θ/(b · s).

(6)

If we assume one trap is generated by one dangling bond, trap-state density N_T is given by the dangling bond density; however, this simple calculation overestimates the state density because of the bond reconstruction from the perfect dislocations and passivation of dangling bonds by hydrogen. The trap-state density N_T is given by the product of efficiency η of the dangling bond and the calculated dangling bond density as

N_T = η × (dangling bond density).

(7)

We estimate η as 1 × 10⁻⁴, similar to the ratio of the experimentally measured state density to the calculated dangling bond density at the Si–SiO₂ interface of the bulk MOSFETs. The interface state density Q_ss was measured as 6 × 10¹⁰ cm⁻² for the (100) surface [29], and the number of the calculated dangling bonds is 6.8 × 10¹⁴ cm⁻² for the (100) surface [30]. The N_T obtained from Equations (6) and (7) is proportional to θ, as shown in Figure 16. The effect of sub-B on the TFT characteristics decreases with the decreasing θ.

4.2. Space Charge Model at the Sub-Boundaries in the Non-Doped Substrate

In the sub-G region without sub-Bs, the channel is formed by the gate-induced carriers in the undoped n-channel TFT. We assume that the free carrier is induced with the concentration n₀ of 1 × 10¹⁶ cm⁻³ in the inverted channel far from the sub-B, which is compatible with the generally used definition for the inversion layer. As the undoped Si substrate is floating, the electrostatic potential and the carrier concentration are uniform from the front to the back interface. From the symmetry, we treat the effect of the sub-Bs in one dimension with a vertical axis to the sub-B plane. Our model neglects the dislocation core of 0.154 nm thickness because it is very small [31]. The infinitely thin sub-B plane is assumed to have a deep trap with a density of N_T. The monoenergetic acceptor-like level is assumed and is ionized when the n-type inversion layer is formed. Due to the charged traps, two depleted regions of Δ are formed at both sides of the sub-B, resulting in a potential barrier of a height qV_B, as shown in Figure 17 [32,33,34,35,36,37], where q is the magnitude of electronic charge.

The depleted region Δ is roughly estimated by the charge neutrality condition as

2Δ· n₀ = N_T,

(8)

and

Δ = N_T / (2 n₀).

(9)

The calculation gives Δ = 4 ~ 8 nm from (9) and the estimated N_T of 0.8 ~ 1.6 × 10¹⁰ cm⁻² for the sub-Bs misfit angle θ of 5 ~ 10°.

Previous studies [28,33,34,35,36,37,38,39,40] of GBs in the poly-Si film assumed that the current flows over the potential barrier qV_B by the thermionic emission model. The N_T of the GBs in the previous study and the estimated N_T of the present sub-B are summarized in

Table 1. Comparison of trap-state density N_T and grain size between the GBs in the previous studies and the sub-Bs in the present work.

Data Source From	NT (cm−2)	Grain Size (nm)
Seto, 1975 [33]	3.41 × 1012	23
Baccarani et al., 1978 [34]	3.80 × 1012	30
Lu et al., 1981 [35]	2.10 × 1012	122
Martinez et al., 1981 [38]	1.2 × 1013	1 × 105
Levinson et al., 1982 [36]	3.9 × 1011	40
Fossum et al., 1983 [37]	1.00 × 1012	1 × 103
Proano et al., 1989 [39]	1.1 ~ 2.0 × 1012	100
Yang et al.,1999 [28]	2.5 × 1012	200
Walker et al.,2004 [40]	1.0 × 1013	-------
This Work	0.8 ~ 1.6 × 1010 (Sub-B)	2.03 × 105 (Perpendicular Grain Width ) 3.38 × 104 (Perpendicular Sub-G Width )

. The N_T of the sub-Bs with θ = 5 ~ 10° drops more than two decades from that of GBs. The Δ of sub-B decreases by the same orders of magnitude from that of GBs. The depletion width of the GBs in the previous studies is very large, Δ ~ 1 μm from Equation (9) if we take N_T = 2.1 × 10¹² cm⁻² typically.

4.3. Carrier Conduction in the Parallel TFTs

In the parallel TFTs containing one sub-B in the channel, the source-to-drain current flows mainly in the intra-sub-G region. Some winding current flows in the vicinity of the sub-B depleted regions, but the current at a distance from the depleted region Δ of sub-B will flow directly from the source to drain, as shown in Figure 18, in the same way as the free carriers in the inversion layer. The sub-B in the parallel TFTs reduces the effective channel width by an amount of 2Δ. Then the effective mobility of the parallel TFT with one sub-B in the active region is estimated as

μ_‖ = μ₀ · {1 − (2Δ)/W }

(10)

where μ₀ is the intra-sub-G mobility. Then, μ_‖ becomes

μ_‖ ~ μ₀

(11)

because 2Δ << W; the total sub-boundary depleted width is 2Δ = 8 ~ 16 nm and the channel width is W = 5 μm.

4.4. Carrier Conduction in the Perpendicular TFTs

When a TFT active region contains one sub-B, the effective resistance R_┴ of the perpendicular TFTs between the source and drain is given by the series resistance of the channel resistance with a length of (L − 2Δ ) and the sub-B resistance R_B

R_┴ = R₀ · (1 − 2Δ/L) + R_B

(12)

in the same way as the previous work [27,28,29], and the intra sub-G resistance R₀ is given by

R₀ = L / (W·n₀·μ₀·d)

(13)

where d is the Si film thickness, and R_B is the sub-B resistance with a length of 2Δ. On the other hand, the effective resistance R_‖ of the parallel TFT is given by

R_‖ = R₀ / (1 − 2Δ/W).

(14)

From the experimentally obtained isotropic effective mobility given by Equation (2),

R_┴ = R_‖.

(15)

Then, as Δ << L, (12) and (14) become

R_┴ = R₀ + R_B

(16)

and

R_‖ = R₀.

(17)

By combining Equations (15)–(17)

R_B = 0.

(18)

The previous works analyzed the current across the GBs with the thermionic emission model of electrons over the barrier qV_G produced by the charged traps [28,33,34,35,36,37,38,39,40]. However, the thermionic emission model cannot explain Equation (18) because the resistance of sub-B does not vanish, even for the barrier height qV_B = 0. The model is invalid for the small barrier height qV_B corresponding to the small N_T of the sub-B because the model was originally derived under the assumption that

qV_B > kT

(19)

where kT is 2.6 × 10⁻² eV at room temperature [37]. The barrier height qV_B is given by

qV_B = (q²·N_T²)/(8·ε_s·n₀)

(20)

for the GBs [37], where ε_s is the permittivity of Si. The barrier height calculated from (20) and the N_T value of the sub-Bs in the present study (shown in Table 1) is a very small value of qV_B = 1.28 ~ 5.2 × 10⁻⁴ eV.

In the measured 13 perpendicular TFTs, a single sub-B comprises at least one TFT. The probability is very high: P = 0.9895, which is calculated from the 10 μm channel length and the density of sub-Bs per unit length of 0.02956 μm⁻¹ obtained from Figure 2b.

4.5. A New Model of the Perpendicular Carrier Conduction at the Sub-B

The sub-B is no more treated as a potential barrier, such as a wall, but is treated as a column of space charge cylinders allowing the current to flow between the dislocation space charge cylinders, as shown in Figure 19. The space charge cylinders are partly overlapped. The radius r of the space charge cylinder of a single dislocation is roughly estimated by the charge neutrality condition as follows:

2 η · d/s = π r²·d· n₀.

(21)

The estimated r is 3.36 nm. This is comparable to the distance D of the dislocations in sub-B; D = 2 ~ 4 nm for θ = 5 ~ 10°, as shown in Figure 15. The carriers can go through the sub-B between the cylinders without the necessity of a high carrier energy surmounting a potential barrier. The dislocation space charge cylinders affect the negligible effect on the current, as concluded in (18), due to only one row of space charge cylinders existing vertically to the current from the source to the drain.

4.6. Origin of the Variations in Electrical Characteristics

The variations in electrical characteristics shown in Figure 9 are caused by some mechanisms independent of the sub-boundary direction because the distributions of parallel and perpendicular TFTs agree well. Figure 20 shows the correlation between the effective mobility and threshold voltage V_th. The measured points in Figure 20 gather around two clusters: in each cluster, there is no relation between parallel (red circle) and perpendicular (blue square) TFTs. In one cluster, the mobility decreases with the negative shift of V_th. This cluster suggests the mobility reduction due to the scattering by the charged Si–SiO₂ interface states at the front or back interface since the negative shift in V_th means an increase in the interface states density Q_ss. The other cluster shows that the mobility is fixed at a low value, independent of V_th. This suggests that the mobility in this cluster is affected by the neutral scattering centers [41], such as surface roughness, and the effect of the neutral scattering center shields the effect of the Q_ss fluctuations. The fluctuation of Q_ss will be suppressed by the optimization of the gate insulator fabrication process at the low temperature of 300 °C. The surface roughness will be suppressed by optimizing the cap structure during the crystallization.

5. Conclusions

Isotropic TFT characteristics have been realized in the {100}-oriented grain-boundary (GB)-free Si thin films crystallized by continuous-wave laser lateral crystallization (CLC). The GB-free films comprise sub-boundaries (sub-Bs) with a misfit angle θ of 5 ~ 10°. The sub-Bs in the GB-free film extend parallel to the scan direction. The neighboring sub-grains (sub-Gs) joined by the sub-Bs tilt alternately to opposite directions, resulting in the uniform {100) in-plane orientation in the scan and transverse directions of the GB-free film. The density of the sub-Bs is 0.022956 μm⁻¹. The width of the sub-grains is 8 ~ 69 μm. The estimated trap-state density N_T of the sub-B is 0.8 ~ 1.6 × 10¹⁰ cm⁻², which drops more than two decades from that of GB. The remaining sub-B does not change the electrical characteristics of either the parallel or perpendicular TFTs. The cumulative distributions of the mobility, Vth, and SS are overlapped precisely between the parallel and perpendicular TFTs. A new current model across the sub-Bs has been proposed instead of the thermionic emission model of the GBs to explain the negligible impedance across the sub-B.