Analysis and Improved Behavior of a Single-Phase Transformerless PV Inverter

Abstract

Transformerless inverters have an important role in the electrical energy market. The high-efficiency and reliable inverter concept is one of the most widely used inverters in single-phase photovoltaic systems because of its high efficiency, low cost, and reduced leakage ground current. However, the leakage ground current behavior depends on the power and weather conditions, which can increase the parasitic capacitance value, thus producing an increase in the leakage ground current magnitude. In this paper, it is proposed to add a passive inductive–capacitive output filter to the inverter structure in order to reduce the dependency of the leakage ground current on the system power and weather conditions. The inductive–capacitive output filter is designed in such a way that it can provide a low impedance path for the leakage ground current, different from the ground path. The proposed system was evaluated both through simulations and experimentally in a 1 kW laboratory prototype.

1. Introduction

Transformerless inverters are widely implemented in photovoltaic (PV) generation systems due to their high efficiency and low cost. However, the common mode behavior problem arises when there is no galvanic isolation in the coupling between the inverter and the electrical grid [1]. Then, leakage ground currents (LGCs) circulate through the system due to the fast dynamic variations of the voltage across the equivalent parasitic capacitance formed at the PV panel. The LGC behavior depends on several factors, for instance, moisture, system size, dust, and the PV panel structure, among others. These conditions and parameters establish the magnitude of the parasitic capacitance which has been studied, determining values from 60 nF/kW to 160 nF/kW according to references [2,3]. On the other hand, the LGC represents a safety and operation risk since it could be responsible for tripping protections or injuring users in contact with the PV system. Thus, there are several international norms that impose limits to the LGC, for instance, 300 mA${}_{RMS}$, according to the German Standard DIN VDE 0126-1-1 [4].

The literature reports a wide range of solutions dealing with the LGC which, in general, can be classified as follows:

• Redesign of the topology [5,6].
• Design of a specific pulse width modulation (PWM) sequence [7].
• Methods based on the design of the output filter [8].
• Virtual grounding techniques [9].
• Control techniques [10].

For transformerless single-phase PV power converters, a popular solution, based on modifying the inverter topology, is presented in [11], where an H-bridge is used with an additional switch on the DC side. The fifth switch is used to perform a decoupling action during the freewheeling periods of the load current, thus achieving a constant common mode voltage (CMV) and consequently reducing the magnitude of the LGC. A solution, based on the implementation of a bidirectional switch on the AC side, is presented in [12], where the topology is called the Highly Efficient and Reliable Inverter Concept (HERIC). The main idea is the same as that presented in [11], but in this case, the freewheeling period is enabled by the bidirectional switch, allowing constant common mode voltage and the reduction in the LGC. The HERIC inverter has been the object of study in several contributions reported in the literature, for instance, an improvement based on the design of the PWM strategy for the HERIC inverter is presented in [13]. Here, the authors proposed a hybrid unipolar PWM strategy to simultaneously achieve high efficiency, low harmonic distortion and reactive power management. During the positive half-cycle, the converter operates with the conventional unipolar PWM; however, during the negative half-cycle, a PWM using only the freewheeling switches is proposed. Moreover, the output voltage and the zero-crossing points of the inverter are improved by modifying the dead times of the PWM strategy. In [14], an improvement behavior regarding LGC for the HERIC inverter is proposed. The improvement is based on the modification of the topology, where an additional switch is implemented to connect the bidirectional switch to the midpoint of the input capacitor. Then, better common mode voltage and LGC performance is achieved; however, an additional cost is introduced to the inverter. Moreover, in [15], an improvement to the HERIC-based topology presented in [14] is proposed. Here, a PWM strategy is designed to provide flexible power compensation and also to compensate for the effects of the dead time and the distortions produced by the minimum pulse width of the PWM signals. Furthermore, in [16], a zero-voltage-transition (ZVT) HERIC inverter is proposed, where resonant tanks are implemented around the high-frequency switch. Resonant tanks mainly contribute to improve efficiency; however, additional resonant active–passive cells must be added to the inverter structure, making it costly. On the other hand, in [17], the leakage current reduction for a single-phase grid-interfaced inverter is proposed. The full-bridge inverter is modified by introducing an AC passive filter capable of operating bidirectionally and reducing the leakage current at the DC side while improving the EMI (Electromagnetic Interference) noise. However, six inductances plus three capacitances are used, and the robustness of the inverter against changes in the parasitic capacitance is not validated. In [8], the cascade multilevel inverter is analyzed to propose two passive filter-based solutions to mitigate the leakage ground current. The first solution introduces common mode chokes in both the AC-side and the DC-side, reducing the LGC magnitude at the two common mode loops formed in the structure of the cascade multilevel inverter. The second solution keeps the common mode chokes introduced in the first solution but adds two capacitors connected to the output of the inverter in parallel with the grid, whose middle point is connected to the middle point of the capacitor at the DC-side. Both methods effectively reduce the LGC; however, multiple passive components are used in the system. Reference [18] presents a solution for a three-phase system with the neutral point connected to the middle point of the DC link for modular multilevel converters, where this connection induces a zero-sequence circulating current resonance issue. The proposed solution for the LGC issue is a bypass capacitor applied to the parallel inverters with common AC and DC bus, ensuring the reduction in the LGC magnitude. In this paper, a new structure for the HERIC inverter based on the common mode model is proposed. The HERIC inverter is modified by providing a low impedance path through two capacitors, thus achieving a noticeable reduction in the leakage ground current magnitude. Therefore, no additional active or passive circuits are added, considering that a passive LCL filter is conventionally included in the inverter system, keeping the proven high efficiency and improving the leakage ground current performance. The main contributions of this paper are the following:

• An improved LC output filter is included in order to improve the LGC mitigation capability of the HERIC converter.
• It is demonstrated through the mathematical models of common mode and differential mode that the modified LC filter improves the LGC mitigation capability.
• The improvement of the LGC behavior by eliminating the dependency on power, size and weather conditions without the use of additional power semiconductors, special control design or specific modulation strategies.

2. Inverter Description and PWM Strategy

The topology under study, which is composed of a full bridge inverter with a bidirectional switch on the AC side, is shown in Figure 1 [12]. The main function of the bidirectional switch is to provide an output current path during the freewheeling states of the inverter. The list of all possible operation states is shown in

Table 1. Summary of the operation states of the HB-HERIC inverter.

State	${\mathit{S}}_1$	${\mathit{S}}_2$	${\mathit{S}}_3$	${\mathit{S}}_4$	${\mathit{S}}_5$	${\mathit{S}}_6$	${\mathit{V}}_{\mathit{Az}}$	${\mathit{V}}_{\mathit{Bz}}$	${\mathit{V}}_{\mathit{AB}}$	${\mathit{V}}_{\mathit{cm}}$
$\mathbf{1}$	1	0	0	1	1	0	$V_{pv}$	0	$V_{pv}$	$V_{pv}/2$
$\mathbf{2}$	1	0	1	0	1	0	$V_{pv}$	$V_{pv}$	0	$V_{pv}$
$\mathbf{3}$	0	0	0	0	1	0	-	-	0	0
$\mathbf{4}$	0	0	0	0	0	1	-	-	0	0
$\mathbf{5}$	0	1	0	1	0	1	0	0	0	0
$\mathbf{6}$	0	1	1	0	0	1	0	$V_{pv}$	$-V_{pv}$	$-V_{pv}/2$

.

The freewheeling state is enabled by disconnecting the four switches, $S_1$ to $S_4$, and connecting either $S_5$ or $S_6$ of the AC bidirectional switch, depending on the current direction. Conventionally, the states $\mathbf{1}$, $\mathbf{2}$, $\mathbf{5}$ and $\mathbf{6}$ are used to synthesize a three-level output voltage delivered by the inverter to the AC side. The signals to modulate the inverter are typically generated by a conventional PWM strategy that adds a simple digital circuit to generate the signals for switches $S_1$ to $S_6$ according to Figure 1. The proposed PWM control signals for the HERIC converter based on the states described in Table 1 are depicted in Figure 2. As it can be noted, during half a period of the grid, the switches $S_5$ and $S_6$ do not perform any switching, and as a consequence, during the positive half period, only switches $S_1$ and $S_4$ are operating. A similar situation can be observed for the negative half period.

3. Proposed Passive Method

The proposal is aimed at reducing the LGC by taking advantage of the properties that output filter passive elements present at different frequencies. Capacitors decrease their reactance as the frequency increases; if their capacitance value is high, the reactance reduction is greater. On the other hand, LGC in photovoltaic circuits occurs at frequencies higher than the switching frequency, which is typically on the order of kHz. Hence, it is proposed to place a new capacitive path for the flow of the LGC. Thus, the possibility of providing the LGC with a capacitive path arises, and in this way, enabling to return it without injecting it into the electrical grid.

The connection of the new trajectory can be seen in Figure 3, where the LGC flows from the photovoltaic panels to the grid and returns through the ground connection. The proposed route joins each output of the photovoltaic inverter with the positive and negative bus of the photovoltaic array using a capacitor. Hence, the capacitor is acting with a low impedance for these high-frequency currents, allowing their circulation and blocking all low-frequency current components, and is also preventing the flow of direct current due to the connection of the DC bus.

3.1. Common and Differential Mode Models

To analyze the behavior of the proposed passive trajectory and its influence on the LGC compensation, a mathematical modeling of the system is performed. The modeling technique is based on the well-known Kirchhoff’s currents and voltages analysis, and yields

$$\begin{array}{c}\hfill L_1{\dot{\widehat{i}}}_{L1}=v_{Az}-v_{Cf1}-\frac{v_{pv}}{2},\end{array}$$

(1)

$$\begin{array}{c}\hfill L_2{\dot{\widehat{i}}}_{L2}=v_{Bz}-v_{Cf2}+\frac{v_{pv}}{2},\end{array}$$

(2)

$$\begin{array}{c}\hfill C_{f1}{\dot{v}}_{Cf1}=i_{L1}-i_{out1},\end{array}$$

(3)

$$\begin{array}{c}\hfill C_{f2}{\dot{v}}_{Cf2}=i_{L2}-i_{out2},\end{array}$$

(4)

$$\begin{array}{c}\hfill i_{LGC}=c_{p1}{\dot{v}}_{cp1}+c_{p2}{\dot{v}}_{cp2},\end{array}$$

(5)

$$\begin{array}{c}\hfill v_{pv}-v_s=v_{Cf2}-v_{Cf1},\end{array}$$

(6)

where the following restrictions for the capacitor voltages are considered:

$$\begin{array}{c}\hfill v_{Cf1}=v_s-v_{cp2}-v_{Rg},\end{array}$$

(7)

$$\begin{array}{c}\hfill v_{Cf2}=-v_{cp1}-v_{Rg}.\end{array}$$

(8)

As is common practice in this kind of systems analysis, the values of the capacitors are assumed to be equal $C_{f1}=C_{f2}=C_{fT}$, and the values of the inductors are also assumed to be equal $L_1=L_2=L$. Also, the parasitic capacitances are considered of the same value, $c_{p1}=c_{p2}=c_{pT}$. Notice also that the DC input voltage of the converter is considered constant or with slow dynamic and is denoted by $v_{pv}$.

The output filter is designed by means of the common mode and differential mode variables and considering the following definitions:

$$\begin{array}{c}\hfill v_{cpT}\triangleq \frac{v_{cp1}+v_{cp2}}{2},\end{array}$$

(9)

$$\begin{array}{c}\hfill v_{CfT}\triangleq \frac{v_{Cf1}+v_{Cf2}}{2},\end{array}$$

(10)

$$\begin{array}{c}\hfill v_{cm}\triangleq \frac{v_{Az}+v_{Bz}}{2},\end{array}$$

(11)

$$\begin{array}{c}\hfill v_{dm}\triangleq v_{Az}-v_{Bz},\end{array}$$

(12)

$$\begin{array}{c}\hfill i_{cm}\triangleq i_{L1}+i_{L2},\end{array}$$

(13)

$$\begin{array}{c}\hfill i_{LGC}\triangleq i_{out1}+i_{out2},\end{array}$$

(14)

$$\begin{array}{c}\hfill i_{idm}\triangleq \frac{i_{L1}+i_{L2}}{2},\end{array}$$

(15)

$$\begin{array}{c}\hfill i_{rdm}\triangleq \frac{i_{out1}+i_{out2}}{2},\end{array}$$

(16)

where $v_{cpT}$ is the total common mode voltage of the parasitic capacitance, $v_{CfT}$ denotes the total common mode voltage of the filter capacitors, $v_{cm}$ is the common mode voltage of the inverter, $v_{dm}$ is the output differential voltage, $i_{icm}$ denotes the common mode current at the inverter side, $i_{LGC}$ is the leakage ground current at the ground path, $i_{idm}$ is the differential current at the inverter side, and $i_{rdm}$ is the differential current at the grid side.

According to the previous analysis related to the electrical variables and considering the definitions (9)–(16), a change of variables can be used to obtain the common mode and differential mode models for the output filter. As a result, the differential mode model can be defined by Equation (17) as follows:

$$\begin{array}{c}\hfill 2L{\dot{\widehat{i}}}_{idm}=v_{dm}-v_s.\end{array}$$

(17)

The equations that describe the common mode model are as follows:

$$\begin{array}{c}\hfill \frac{L}{2}{\dot{\widehat{i}}}_{cm}=v_{cm}-v_{CfT},\end{array}$$

(18)

$$\begin{array}{c}\hfill 2C_{fT}{\dot{v}}_{CfT}=i_{cm}-i_{LGC},\end{array}$$

(19)

$$\begin{array}{c}\hfill 2c_{pT}{\dot{v}}_{cpT}=i_{LGC},\end{array}$$

(20)

$$\begin{array}{c}\hfill v_{CfT}=-v_{cpT}-v_{Rg}+\frac{v_s}{2}.\end{array}$$

(21)

Taking into account the restrictions related to the capacitors of the output filter, it is possible to simplify the common mode model equations to obtain a new set of two equations, which are (22) and (23), defined as follows:

$$\begin{array}{c}\hfill \frac{L}{2}{\dot{\widehat{i}}}_{cm}=v_{cm}+v_{cpT}+v_{Rg}-\frac{v_s}{2},\end{array}$$

(22)

$$\begin{array}{c}\hfill 2C_{fT}{\dot{v}}_{cfT}=i_{cm}-2c_{pT}{\dot{v}}_{CpT}.\end{array}$$

(23)

From Equation (17), it is possible to derive an equivalent differential mode circuit, which is shown in Figure 4a, and from Equations (22) and (23), the common mode circuit depicted in Figure 4b can be also defined.

In the case of the differential mode model from Figure 4a, it is observed that the capacitors proposed for the output filter do not appear, so it can be expected that the addition of these capacitors to the inverter topology does not influence the differential output voltage.

On the other hand, considering the common mode model from Figure 4b, it can be noted that there is a low impedance path provided by the output filter capacitor, which conducts the LGC. This new trajectory avoids the circulation of the LGC throughout the ground path connected between the neutral point of the electrical grid and the terminals of the parasitic capacitors.

3.2. LC Filter Analysis

The structure proposed for the connection of the output filter capacitors allows to take advantage of the frequency dependence behavior of these capacitors, which presents low impedance for LGC frequencies and high impedance to the grid frequency. On the other hand, the frequency behavior of the output inductive filter is also used since the inductor presents low impedance for the grid current and high impedance for the LGC frequency components. The design of this filter is described below.

From Equations (18) and (19), the model based on the state space presented in Equations (24) and (25) can be derived, which represents the behavior of the common mode current and the voltage through the output filter capacitors:

$$\begin{array}{c}\hfill {\dot{\widehat{i}}}_{cm}=-\frac{2v_{CfT}}{L}+\frac{2v_{cm}}{L},\end{array}$$

(24)

$$\begin{array}{c}\hfill {\dot{v}}_{CfT}=\frac{i_{cm}-i_{LGC}}{2C_{fT}},\end{array}$$

(25)

The transfer function for the relation $I_{cm}\left(s\right)/V_{cm}\left(s\right)$ can be defined as:

$$\begin{array}{c}\hfill G_{cm}\left(s\right)=\frac{2s{C}_{fT}}{L{C}_{fT}{s}^2+1},\end{array}$$

(26)

from which the characteristic polynomial is:

$$\begin{array}{c}\hfill {\Delta }_{G_{cm}\left(s\right)}=s^2+\frac{1}{L{C}_{fT}}.\end{array}$$

(27)

Moreover, the cutoff frequency (${\omega }_c$) is:

$$\begin{array}{c}\hfill {\omega }_c=\sqrt{\frac{1}{L{C}_{fT}}}.\end{array}$$

(28)

From Equation (28), the value of the output filter capacitor $C_{fT}$ can be obtained as a function of the cutoff frequency and the inductor value as follows:

$$\begin{array}{c}\hfill C_{fT}=\frac{1}{{\omega }_c^{2}L}.\end{array}$$

(29)

On the other hand, the inductance value can be chosen as a function of the desired current ripple amplitude at the inverter side. The method is described in [19,20,21,22], where the analysis is based on the charge and discharge of the inductor. The required inductance value can be determined by means of Equation (30) as follows:

$$\begin{array}{c}\hfill L_1=\frac{v_{pv}}{8\Delta i_{L_{max}}{f}_c},\end{array}$$

(30)

where $\Delta i_{L_{max}}$ is the maximum ripple output current peak-to-peak value.

A ripple magnitude of 20% of the nominal current can be considered acceptable, as it guarantees a proper inductor size according to [21,23]. Additional design parameters for LCL filters can be determined from the values reported in [21,24]. From experimental tests, it is considered that the value of $L=L_1+L_2$ must be lower than 10% than the base impedance defined as $L_b=v_{rms}^2/2\pi f_{m}S$, where $L_b$ is the base inductance, $v_{rms}$ is the RSM value of the grid voltage, $f_m$ is the grid frequency, and S is the output apparent power.

Considering the above concepts and with 5 kHz as the cutoff frequency for the passive filter, the following values for the passive filter were calculated:

$$\begin{array}{c}\hfill L_1=L_2=1.45\mathrm{mH},\end{array}$$

(31)

$$\begin{array}{c}\hfill C_{fT}=13.7\mathrm{uF}.\end{array}$$

(32)

In Figure 5, the Bode plot from (26) is presented, where this transfer function and the filter design are validated. As it can be observed, the cutoff frequency is around 5 kHz as established through the design. This means that only high-frequency components are allowed, while low-frequency components, such as the grid frequency, are attenuated.

4. Simulation Results

The numerical simulations were performed using PSIM software. The parameters used for both simulations and experimental test are defined in

Table 2. Converter parameters.

Parameters	Variable	Value
DC input voltage	$v_{pv}$	220 V
Rated power	S	1 kW
Modulation frequency	$f_m$	60 Hz
Modulation index	$m_a$	0.9
Switching frequency	$f_c$	12 kHz
Dead-time	$t_d$	4 $\mathsf{\mu }$s
Active power	P	1 kW
Input capacitor value	$C_{pv}$	660 $\mathsf{\mu }$F
Filter capacitor value	$C_{f1,2}$	5 $\mathsf{\mu }$F
Filter inductor value	$L_{1,2}$	2 mH
Ground parasitic resistance value	$R_g$	10 $\Omega$
Parasitic capacitance value	$c_{p1,2}$	20–840 nF

. Note that the values of L and C were adjusted according to the values available in the laboratory to have a fair comparison between the simulations and experiments.

In Figure 6a, the output voltage and current behaviors of the inverter without the passive filter are shown. Note that these results were obtained in an open loop with an RL load. Moreover, Figure 6b shows the same variables as in Figure 6a, but now the passive filter is connected. As it can be observed, the proposed output filter is acting as a conventional output filter on the output parameters. Hence, both figures present similar output current and voltage waveforms.

Table 3. THD${}_i$ values obtained with the numerical simulations with and without the output LC filter.

THD${}_{\mathit{i}}$	Value
Without the output filter	2.91%
With the output filter	3.04%

shows the THD measured for the load current waveform, where a small difference appears (0.13%) in the THD magnitude, which corresponds to an increase in the current ripple due to the leakage current trajectory provided by the implemented passive filter.

Figure 7 and Figure 8 show the FFT (Fast Fourier Transform) of the output current $i_{out1}$. The harmonics appearing in these plots correspond to the switching frequency $f_c$ and its multiples. The results in Figure 7 correspond to the system without the passive filter. The harmonic components related to the switching frequency have lower magnitudes than the switching harmonic components of Figure 8 with the system, including the proposed passive filter. This effect is due to the circulating LGC through the power inverter.

Figure 9 shows the common mode voltage and leakage current behaviors without the connection of the passive filter in the HERIC topology. As it can be observed, there are excursions of the CMV along the grid period, which contribute to produce the LGC shown in the red plot below. The LGC magnitude in this case presents an $RMS$ value around 31.24 mA. On the other hand, Figure 10 shows the same electrical variables but with the passive filter connected to the HERIC topology. As it can be noted, the CMV variations are reduced, and as a consequence, the magnitude of the LGC is now around 11 mA${}_{RMS}$. These results demonstrate that, even when the topology is designed to deal with the LGC, it is possible to improve its behavior using a complementary technique without additional cost.

Figure 11 and Figure 12 show the dynamic test considering transitions for the output power and parasitic capacitance values, respectively. In Figure 11, from top to bottom, the $C_{p1}$ voltage, $C_{p2}$ voltage, output current and LGC are presented. Note that a power step from 347 W to 1014 W is applied at around 1.05 seconds without any influence on the LGC behavior. Moreover, Figure 12 shows, from top to bottom, the $C_{p1}$ voltage, $C_{p2}$ voltage and LGC under a step change in the parasitic capacitance from 20 nF to 840 nF that occurs at around 1.05 s without any disturbance on both parasitic capacitance voltages. However, the LGC increases from 1.04 mA${}_{RMS}$ to 35.41 mA${}_{RMS}$ as it is shown in

Table 4. Leakage current magnitude for different values of the parasitic capacitance.

$\mathbf{Parasitic}\mathbf{Capacitance}\mathbf{Values}$	${\mathbf{i}}_{\mathbf{LGC}}$ Value
20 nF capacitance	1.04 mA${}_{RMS}$
840 nF capacitance	35.41 mA${}_{RMS}$

, and notwithstanding the hard increment on the parasitic capacitance value, the magnitude of the LGC is still under the limit imposed by the international standard. This means that the proposed system is robust against changes in the rated power and increments of the parasitic capacitance value. It is worth noticing that there is a current spike when the parasitic capacitance value is increased, which corresponds with the general definition of the capacitor current; however, in a real implementation, the capacitor value will typically increase smoothly so that the current spike will not appear.

Regarding the behavior of the LGC when the switching frequency varies, it can be considered that the typical switching frequency interval in this kind of system for powers less than 10 kW in single-phase inverters is commonly defined in the interval of 5 kHz and 25 kHz due to the characteristics of the power semiconductors and the behavior of their power losses. Considering this interval, the impact on the behavior of the leakage ground current is as in Figure 13, where it can be observed that the magnitude of the LGC decreases as the switching frequency increases. On the other hand, the switching frequency of these systems is considered constant, so the analysis of the LGC current is commonly performed under this condition.

5. Laboratory Implementation and Comparative Analysis

A laboratory prototype is designed and implemented to validate the proposed solution. The experimental parameters are fixed equal to those defined for the simulation results in Table 2. For the HERIC inverter design, the power semiconductors listed in

Table 5. List of components used in the experimental prototype.

Part Number	Description	Characteristics	Amount
G4PC40FD	IGBT (with ultra fast soft recovery diode)	600 V, 27 A.	6
IDH16S60C	SiC Schottky Diode	600 V, 16 A.	2
HFBR-2531	Fiber optic opto receiver	7 V, 25 mA.	6
HCPL-3120	Opto-coupler for IGBT gate drive	5 V, 16 mA, 1200 V.	6

are used. The DSP TMS320F28335 from Texas Instruments is used as the platform to program the modulation sequence to control the HERIC inverter. The experimental setup is shown in Figure 14. As in the simulation results, the experimental test was performed in open loop; therefore, in the experimental setup, the grid voltage is implemented using a resistive load. In addition, the input DC voltage is considered constant and implemented using a constant DC source. Finally, in order to emulate the ground path resistance, $R_G$ is connected between the grid neutral connection and the parasitic capacitances according to [25,26,27].

The digital signals obtained using a SPWM technique are shown in Figure 15, where two grid cycles are considered. The six signals correspond to those obtained in the simulation results section.

Figure 16 and Figure 17 show the experimental plots for the differential output voltage $v_{dm}$ and the load current $i_{out}$ without and with the proposed LC output filter, respectively. The $RMS$ values are around 158 V and 7.65 A for both cases, which correspond also with the simulation results. A small difference can be observed regarding the output current ripple, which is slightly higher when the output filter is considered. This is due to the addition of the trajectory for the CMC.

The above affirmation can be demonstrated by comparing the frequency spectrum for the output current. Figure 18 and Figure 19 show the Fourier Fast Transform (FFT) of the output current with and without the output filter. As it can be noted, the magnitude of all harmonics is greater in the case of the connected filter than in the case when the filter is not connected. This will result in an increment of the THD as demonstrated in the simulation results section.

The CMV and the CMC were also obtained from the prototype, which are depicted in Figure 20 and Figure 21, with and without the passive filter, respectively. Note that the CMV behavior is different, with larger excursions for the first case. In consequence, the magnitude of the CMC is lower when the output filter is connected. This means that even when the HERIC topology is designed to deal with the CMC, a complementary method can be implemented to improve its performance.

Changes in the rated power were also performed. Figure 22 and Figure 23 show the results obtained with and without the implemented filter. The power step was defined from 347 W to 1000 W. As it can be noted, the step of the output power when the filter is not connected produces a reduction in the CMC; however, when the filter is connected, there are no changes in the magnitude of the CMC.

Table 6. Leakage ground current magnitude under an output power step.

Power	${\mathbf{i}}_{\mathbf{LGC}}$ without Filter	${\mathbf{i}}_{\mathbf{LGC}}$ with Filter
	Peak Value–RMS Value	Peak Value–RMS Value
347 W	910 mA–127 mA	150 mA–20 mA
1000 W	710 mA–72.1 mA	130 mA–20.8 mA

summarizes the peak and $RMS$ values. According to the results, the increment in the power does not imply an increment of the CMC in the proposed case.

Moreover, an important plot is that related to the changes in the parasitic capacitance. In Figure 24 and Figure 25, the results obtained without and with the filter for a step in the capacitance value from 20 nF to 840 nF are shown respectively. As can be noted, in the case where the filter is not implemented, the LGC increases until the $RMS$ value is around 105 mA. On the other hand, when the filter is connected, the LGC also increases, but in this case, the increment is marginal, being 36.7 mA. This demonstrates that the dependency regarding capacitance value is well reduced by the proposed passive filter.

Table 7. Leakage ground current magnitude under parasitic capacitance steps.

${\mathit{C}}_{\mathit{p}\mathbf{T}}$	${\mathbf{i}}_{\mathbf{LGC}}$ without Filter	${\mathbf{i}}_{\mathbf{LGC}}$ with Filter
	Peak Value–RMS Value	Peak Value–RMS Value
20 nf	850 mA–30.3 mA	230 mA–16 mA
840 nf	1.01 A–105 mA	170 mA–36.7 mA

summarizes the peak and $RMS$ values for capacitance steps. In addition, in order to show that the implemented filter guarantees an additional path for the leakage ground current, Figure 26 is considered. It must be noted that, effectively, the leakage current flows through the low impedance provided by the capacitors implemented in the output filter.

6. Conclusions

In this paper, a redundant solution to deal with the common mode problem in the HERIC transformerless photovoltaic inverter is proposed. The HERIC topology by itself has common mode currents, whose magnitude depends on the power and the magnitude of the parasitic capacitances. The proposed solution deals with the magnitude of the LGC when there is an increase in the rated power or magnitude of the parasitic capacitances. The LGC magnitude keeps the same value when the power increases. When the parasitic capacitance changes from 20 nF to 840 nF, the LGC increases 75 mA without the proposed filter. However, considering the solution proposed, the increase is marginal, and its value is around 20 mA. The proposed solution adds the passive filter components; however, a conventional PV inverter requires an output filter, which is generally third order. Therefore, the implementation does not imply an additional cost. It can be concluded that the redundant method presented in this paper effectively reduces the dependence of the leakage currents of the HERIC inverter with respect to the power and the magnitude of the parasitic capacitance.