Improved Current-Sharing Imbalance Control Model Based on Magnetic Ferrite Inductance and a Gate Drive Circuit

Abstract

The dynamic and static imbalance of parallel current sharing has held the concern of researchers in view of the variation in multiple parasitic parameters on high-frequency parallel switching mode power supply (SMPS). The joint simulations and suppression experiments on the parallel current-sharing imbalance of various parasitic parameters are investigated on the improved dual-pulse detection circuit platform to determine the method of detecting the parallel current-sharing imbalance ratio using the sum of the differential magnetic flux. An improved model of current-sharing imbalance control is presented consisting of magnetic ferrite inductance and a gate drive circuit. The main concerns are the suppression performance of drain, gate, and source parasitic inductance, gate–source capacitance, driving time and voltage, gate resistance, and delayed forward/reverse driving signals on the ratio of parallel current-sharing imbalance, respectively. The improved model effectively reduces the parallel current-sharing imbalance ratio by more than 5% and 2–4.2%, compared with using a gate drive circuit alone and using magnetic ferrite inductance solely.

1. Introduction

High-frequency switching mode power supply (SMPS) controls the time ratio of turn on and turn off and maintains a stable output voltage, which is generally composed of IC and MOSFET and controlled by pulse width modulation (PWM). The parallel current-sharing imbalance is suppressed [1,2,3] based on Ohm’s law and Thevenin’s voltage theorem [4,5,6] when the voltages and impedance of the parallel branches in SMPS are the same. However, the imbalance of parallel current sharing [7,8,9] will occur due to the variation in multiple parasitic parameters on high-frequency SMPS. The current-sharing imbalance of the SiC modules can be divided under the dynamic and static conditions [10,11,12]: (1) dynamic current-sharing imbalance of i_d during switching and (2) static current-sharing imbalance during turn on. The above dynamic and static parallel current-sharing imbalances both reduce the working efficiency and affect the stable operation of parallel SiC modules [13,14].

Earlier, most researchers and institutions focused on the theoretical analysis of parallel current sharing based on the double-pulse test. The switching performance of parallel-connected junction field-effect transistors (JFETs) was investigated using single- and double-gate drivers in a double-pulse test circuit, while the switched current sharing was reproduced in simulation by introducing the parasitic parameters [15]. The theoretical results of the current-sharing imbalance characteristics and switching energy of parallel SiC devices for some parasitic inductance differences were analyzed, where the parallel SiC transistor double-pulse circuit model was built by Pspice simulation software to verify the theoretical analysis [16].

Research on suppressing parallel current-sharing imbalance owing to multiple parasitic parameters has gradually attracted more interest using single- and double-gate drivers and magnetic ferrite inductance. The dispersion of SiC device parameters of the same model and its influence on parallel current-sharing imbalance were explored, while the relationship between static current-sharing imbalance and the on-resistance of SiC modules was analyzed [17,18,19]. The current-sharing feature of SiC modules and the switching loss of each device were analyzed under the condition of the threshold voltage difference [20]. The research results show that for devices with a small threshold voltage, the switching loss was greater than that of devices with a large threshold voltage both under turn-on and turn-off conditions of parallel devices. The influence of common drain and source parasitic inductance differences on the dynamic current-sharing imbalance of parallel SiC modules was studied through simulations and experiments [21,22]. It was pointed out that the drain parasitic inductance difference affects the turn-off voltage peak of parallel devices and parallel current sharing in the conduction process. The influence of the difference between third-generation 10 kV SiC device parameters and circuit parameters on parallel current sharing was analyzed, and the method of reducing the current imbalance by Kelvin connection was proposed [23]. A double-transistor parallel SiC module double-pulse simulation circuit was established considering the total parasitic inductance, which shows that the current-sharing imbalance caused by different threshold voltages can be effectively reduced by synchronously increasing the common source parasitic inductance, while the switching loss can be increased [24,25,26]. So far, research on suppressing parallel current-sharing imbalances based on various parallel double-pulse circuit models is still in urgent need of improvement owing to the multiple parasitic parameters [27,28], as shown in Table S1.

As the recent concern of research in high-frequency SMPS, various parasitic parameters (drain, gate, and source parasitic inductance, L_d, L_g, and L_s, gate–source capacitance, C_gs, driving time and voltage, t_d and V_on, gate resistance, R_g, and delayed forward/reverse driving signals, ΔT_m) that act on the parallel current-sharing imbalance of branches are investigated in this paper. The suppression of parasitic parameters on the ratio of parallel current-sharing imbalance, r_Δi, is revealed by single- and joint-simulation analysis and multiple parasitic parameter expression experiments. This paper sheds light on understanding the influence of multiple parasitic parameters on the dynamic and static parallel current-sharing imbalance and proposes an improved parallel current-sharing control model to suppress the current-sharing imbalance using magnetic ferrite inductance and a gate drive circuit.

2. Theoretical Basis and Experiments

2.1. Design of the Improved Current-Sharing Imbalance Control Model

The improved current-sharing imbalance control model considering multiple parasitic parameters is designed, where the design of a parallel single-channel circuit is shown in Figure 1. According to the standard setting of multiple parasitic parameters of the double-pulse test circuit [20,21,22], the multiple parasitic parameters (C_iss, C_oss, C_rss, L_d, L_g, L_s, C_gs, C_gd, C_ds, R_dson) are selected, respectively, as shown in

Table 1. Multiple parasitic parameters on the single-loop test circuit of the high-frequency SiC module (including test conditions).

Physical Symbol	Physical Meaning	Typical Values	Test Conditions	Unit
Rdson	On resistance	80	Vds = 20 V id = 20 A	mΩ
Rg	Gate-drive resistance	4.6		Ω
gm	Transconductance	9.8		S
Ciss	Input capacitance	950	Vgs = 0 V Vds = 1000 Vf = 100 kHz Vac = 25 mV	pF
Coss	Output capacitance	80		pF
Crss	Reverse transfer capacitance	6.5		pF
Lg	Gate parasitic inductance	15		nH
Ld	Drain parasitic inductance	6		nH
Ls	Source parasitic inductance	9		nH
Qgs	Gate–source charge	10.8	Vds = 800 V Vgs = 200 V id =20 A	nC
Qgd	Gate–drain charge	18		nC
Qds	Drain–source charge	49.2		nC
Cgs	Gate–source capacitance	54		pF
Cgd	Gate–drain capacitance	30		pF
Cds	Drain–source capacitance	61.5		pF

. C_bus and U_dd represent bus capacitance and DC load voltage, respectively, to maintain a constant output load voltage, where g_m dynamically adjusts according to the variation in C_bus and U_dd.

The test circuit for multiple parasitic parameters of high-frequency SiC modules considers input capacitance, output capacitance, and reverse transmission capacitance and is respectively designed to collect the input, output, and reverse transmission capacitance (C_oss, C_iss, and C_rss) [25,26,27], as shown in Figure 2a–c.

2.2. Principle of the Improved Current-Sharing imbalance Control Model

The principal design of parallel current sharing based on the single-channel magnetic ferrite inductance-combined gate drive circuit is obtained, as shown in Figure 3. The sum of the differential magnetic fluxes generated by electromagnetic induction is not zero in each branch on the parallel double-pulse test module, whilst the drain current i_d being unbalanced provides a certain inhibitory effect on r_Δi [29,30]. The principal design of parallel current sharing based on the single-channel magnetic ferrite inductance-combined gate drive circuit is designed, as shown in Figure 3.

The optimized layout of PCB in the vertical multi-loop layout for DUT1–DUT10, the parallel power circuit layout, and the single-channel driving circuit layout is designed, as shown in Figure 4a–c. Parallel conductance modules with opposite currents are inserted between DUT1–DUT10 under the same current conditions to make the differential magnetic flux more obvious. The parameter settings of the optimized layout of PCB in the vertical multi-loop layout are shown in Table S2.

The greater current-sharing imbalance is attributed to the larger dispersion between parallel conductance modules, with more magnetic ferrite inductance modules used in parallel. The schematic diagram of the multi-channel parallel inductance model is shown in Figure 5. DUT1, DUT2⋯⋯DUT10 are, respectively, 1–10 parallel channels, and H1, H2⋯⋯H10 are the magnetic field intensities for DUT1–DUT10. The size and type of the magnetic ferrite inductance model are shown in Figure S2. As the magnetic ferrite inductance modules increase to n, the schematic diagram of the multi-channel parallel inductance model is obtained, as shown in Figure S3.

In parallel branches, the current in each 1-10 branch is i_d1, i_d2, i_d3, ⋯⋯ i_d10. The difference in parallel current sharing is Δi_ab (1 ≤ b < a ≤ 10), as shown in Equation (1):

$$\Delta i_{ab}=i_{da}-i_{ab}\left(1\le a\le b\le 10\right)$$

(1)

The magnetic field intensity excited by i_d1, i_d2, i_d3, ⋯⋯ i_d10 for each 1–10 branch is H₁, H₂······H₁₀. The difference in parallel current sharing |Δi_ab| is, respectively:

$$\left|\begin{array}{c}\Delta i_{12}\\ \Delta i_{23}\\ ⋮\\ \Delta i_{8,9}\\ \Delta i_{9,10}\\ 0\end{array}\right|=\frac{1}{10}\left|\begin{array}{cccccccc}{l}_1+2l_2& -l_1& 0& \cdots & 0& 0& 0& 0\\ 2l_2& l_1+2l_2& -l_1& \cdots & 0& 0& 0& 0\\ ⋮& ⋮& ⋮& \cdots & ⋮& ⋮& ⋮& ⋮\\ 2l_2& 2l_2& 2l_2& \cdots & 2l_2& l_1+2l_2& -l_1& 0\\ 2l_2& 2l_2& 2l_2& \cdots & 2l_2& 2l_2& l_1+2l_2& -l_1\\ 1& 1& 1& \cdots & 1& 1& 1& 1\end{array}\right|\left|\begin{array}{c}{H}_1\\ H_2\\ ⋮\\ H_8\\ H_9\\ H_{10}\end{array}\right|$$

(2)

Derived from Faraday’s law of electromagnetic induction, the induced voltages in the DUT1, DUT2 ⋯⋯ DUT10 parallel channels are represented by U_f1, U_f2, ⋯⋯ U_f10:

$$U_{f\mathrm{n}}=n\frac{d{\varphi }_n}{dt}\left(1\le n\le 10\right)$$

(3)

In matrix form:

$$\left|\begin{array}{c}{U}_{f1}\\ U_{f2}\\ ⋮\\ U_{f8}\\ U_{f9}\\ U_{f10}\end{array}\right|=S{\mu }_0{\mu }_r{10}^2\left|\begin{array}{cccccccc}{l}_1+2l_2& -l_1& 0& \cdots & 0& 0& 0& 0\\ 2l_2& l_1+2l_2& -l_1& \cdots & 0& 0& 0& 0\\ ⋮& ⋮& ⋮& ⋮& ⋮& ⋮& ⋮& ⋮\\ 2l_2& 2l_2& 2l_2& \cdots & 2l_2& l_1+2l_2& -l_1& 0\\ 2l_2& 2l_2& 2l_2& \cdots & 2l_2& 2l_2& l_1+2l_2& -l_1\\ 1& 1& 1& \cdots & 1& 1& 1& 1\end{array}\right|\left|\begin{array}{c}\frac{d\Delta i_{12}}{dt}\\ \frac{d\Delta i_{23}}{dt}\\ ⋮\\ \frac{d\Delta i_{8,9}}{dt}\\ \frac{d\Delta i_{9,10}}{dt}\\ 0\end{array}\right|$$

(4)

According to (1)–(4), the relative permeability of the magnetic ferrite inductance, μ_r, the area of the magnetic core, S, and the leakage inductance of magnetic ferrite inductance and winding, L_σ, act on i_d to suppress r_Δi. In addition, the magnetic saturation and hysteresis of core inductance also induce the suppression of r_Δi.

2.3. Improved Double-Pulse Detection Circuit Platform

The improved dual-pulse platform is built to study multiple parasitic parameters on the parallel current-sharing imbalance using the half-bridge module, as shown in Figure 6. The high (low)-level pulse, respectively, drives the turn-on (off) parallel branch circuit from pulse width modulation (PWM). Based on high (low)-level pulse signals, the driving gate driver outputs a dual-pulse waveform from the drive push–pull circuit and relies on the compensation capacitor to suppress the oscillation using the suppression circuit. The parallel bridge circuit maintains the electrical isolation during the turn-on (off) parallel state, and the output control circuit is connected to the C2M008120D SiC module for testing.

3. Results and Discussion

3.1. i_d/t Simulation on Different L_g

During the first set of parallel simulations, the standard value and other parameters of L_g1 on the first branch are set according to Table 1, and L_g2 in branch I is simulated with the maximum value, minimum value, and average value of the measurement results. The simulation curves of i_d and the maximum value, standard value, average value, and minimum value of L_g are obtained, as shown in Figure 7. At this time, the i_d on branch I and branch II are i_d1 and i_d2, respectively. i_d1 and i_d2 are expressed by:

$$i_d=g_f\left(U_g-L_g\frac{d{i}_g}{dt}-V_{th}\right)$$

(5)

where g_f is the transconductance of the test module, and ig is the gate drive current.

The r_Δi is:

$$r_{\Delta i}=\frac{i_{d1}}{i_{d2}}=\frac{U_g-L_{g1}\frac{d{i}_g}{dt}-V_{th}}{U_g-L_{g2}\frac{d{i}_g}{dt}-V_{th}}$$

(6)

A comparison of the simulation results shows that the branch with a small L_g has a faster V_on and less i_d than the other branch. The maximum value, standard value, average value, and minimum value of L_g are set, respectively. The maximum values of i_d, 11.2 A, 11.2 A, 11.2 A, and 11.1 A, are obtained when L_g is at T = 5.5 μs, T = 5.0 μs, T = 3.7 μs, and T = 3.6 μs. According to Equation (6) for r_Δi, it can be seen that Δi_d in the process of parallel switching is affected only when ΔL_g is enormous, while Δi_d has no significant effect on ΔL_g under static conditions.

3.2. i_d/t Simulation on Different L_d

During the second set of parallel simulations, L_d affects the change rate of i_d. L_d and parasitic diode C_j form an oscillation circuit when turned on, and a spike in i_d appears. It forms a loop with C_ds and charges simultaneously under turn-off conditions. An oscillation loop is formed while reducing the turn-off speed. Branch I is set as the standard value, while branch II is set as the maximum, minimum, and average values three times. The others are set according to Table 1 and remain constant. The simulation curves of i_d and the maximum value, standard value, average value, and minimum value of L_d are shown in Figure 8. The simulation curves of i_d with L_d1 and L_d2 (L_d on branch I and branch II) are shown in Figure 9 where L_d1 and L_d2 affect r_Δi under dynamic and static conditions.

Equation (7) is obtained during turn on:

$$L_{d1}\frac{d{i}_{d1}}{dt}+R_{dson1}{i}_{d1}=L_{d2}\frac{d{i}_{d2}}{dt}+R_{dson2}{i}_{d2}=U_{dd}-L\frac{d{i}_L}{dt}$$

(7)

di/dt is the change rate of the drain current, and R_dson is the resistance after the test module is turned on.

When the total current is equal to the sum of i_d1/i_d2, Δi_d is derived:

$$\Delta i_d=i_{d1}-i_{d2}=\frac{L_{d1}-L_{d2}}{2R_{dson}}\frac{U_{dd}}{L}$$

(8)

L_d1, L_d2 directly determines Δi_d at static state. A resonant circuit composed of L_d and the parasitic body diode generates current oscillation during the switching process.

The oscillation frequency, f_zd, is expressed as:

$$f_{zd}=\frac{1}{2\pi \sqrt{L_d{C}_{gd}}}$$

(9)

Oscillation circuits I and II are obtained, composed of L_d (L_d1 and L_d2 on branch I and branch II in Figure 1) and C_gd (C_gd1 and C_gd2 on branch I and branch II in Figure 1), respectively.

A resonant circuit composed of L_d and C_ds (C_ds1 and C_ds2 on branch I and branch II in Figure 1) is obtained during switching. L_d charges C_ds at the resonant frequency of f_xz. f_xz is expressed as:

$$f_{zd}=\frac{1}{2\pi \sqrt{L_d{C}_{ds}}}$$

(10)

L_d affects r_Δi after i_d rises (falls) during the switching process. The oscillation frequency and damping coefficient are reduced on the branch with a larger L_d.

3.3. i_d/t Simulation on Different L_s

During the third set of parallel simulations, L_s on branch I is set as the standard value, and the values on branch II are set as the maximum, minimum, and average values of the measurement outcomes three times, respectively. The simulation curves of i_d and the maximum value, standard value, average value, and minimum value of L_s are obtained, as shown in Figure 10.

There is a nonlinear negative correlation between L_s and U_gs, and the change rate of i_d after conduction infinitely tends to zero, so the influence on r_Δi under static conditions is reduced to zero. U_gs is expressed by:

$$U_{gs}=U_g-i_g{R}_g-L_s\frac{d{i}_d}{dt}$$

(11)

At this time, r_Δi is:

$$r_{\Delta i}=\frac{i_{d1}}{i_{d2}}=\frac{U_g-i_g{R}_g-L\frac{d{i}_{d1}}{dt}}{U_g-i_g{R}_g-L\frac{d{i}_{d2}}{dt}}$$

(12)

According to Equations (11) and (12), during the switching process of the branch with a larger L_s, the switching time is longer, i_d is smaller, and the current overshoot is also tiny.

3.4. i_d/t Simulation on Different C_gs

During the fourth set of parallel simulations, branch I and branch II are set to the standard values and the maximum, minimum, and average values, respectively. The simulation curves of i_d and the maximum value, standard value, average value, and minimum value of C_gs are shown in Figure 11.

i_d is very sensitive to C_gs during the switching process. On the branch with a smaller C_gs, the turn-on time is short, the fluctuation range of i_d is small, and the current overshoot is slight. After being turned on, C_gs has little effect on r_Δi under static conditions. During the turn off of the SiC module, the branch with a smaller C_gs has a faster opening speed and a smaller i_d. The earlier the branch with a smaller C_gs is opened, the V_g first reaches the V_th. Since C_gs affects the change rate of V_g, V_g can reach V_th earlier on the branch with a smaller C_gs. The RC buffer circuit formed by C_gs and R_dson suppresses the occurrence of oscillation on i_d to reduce the charge/discharge and switching speed. On the branch with a larger C_gs, the charge/discharge and switching speed both decrease. The decrease in the switching speed increases the switching frequency of the test module. The occurrence of r_Δi is increased by C_gs, affecting the change rate of V_g. The turn-on speed of the branch is slower when C_gs is larger.

3.5. i_d/t Simulation on Different t_d

During the fifth set of parallel simulations, t_d is set to 0 on branch I, and t_d is set to 5 ns, 10 ns, and 15 ns, respectively, on branch II. The simulation curves of i_d and the 0 ns, 5 ns, 10 ns, and 15 ns values of t_d are acquired, as shown in Figure 12. i_d reaches the maximum values of about 14.1 A, 14.0 A, 14.2 A, and 14.2 A at 5 μs, 5.1 μs, 5.2 μs, and 5.3 μs, respectively, when t_d is 0 ns, 5 ns, 10 ns, and 15 ns, respectively. The r_Δi increases as t_d increases. The turn-on speed of the double-pulse parallel test module is faster, and r_Δi is smaller during the turn-on process of the branch with a smaller t_d. t_d shall be minimized to ensure parallel current-sharing imbalance control during double-pulse driving independently in parallel.

3.6. i_d/t Simulation on Different V_on

V_on is set to 18–20 V, which can effectively ensure the effective switching process of the double-pulse parallel test module. The branch with a larger V_on has a faster switching speed and bears a greater i_d. g_f is the ratio between i_d and V_g, being the slope of its curve. The larger g_f means that V_g has stronger control over i_d. V_g is larger, leading to a stronger control ability and a faster switching speed. V_on can effectively adjust i_d in the static state by R_dson. The branch that bears the whole i_d will damage the double-pulse parallel test module as the V_on signals differ greatly.

In the turn-on state, i_d is:

$$i_d=g_f\left(U_{gs}-V_{th}\right)$$

(13)

At this point, r_Δi is:

$$r_{\Delta i}=\frac{i_{d1}}{i_{d2}}=\frac{g_f\left(U_g-L_{g1}{i}_g-V_{th}\right)}{g_f\left(U_g-L_{g2}{i}_g-V_{th}\right)}$$

(14)

3.7. i_d/t Simulation on Different R_g

During the sixth set of parallel simulations, R_g is set to 10 Ω on branch I, and R_g is set to 5 Ω, 15 Ω, and 20 Ω, respectively, on branch II. The others are set according to Table 1. The simulation results are shown in Figure 13.

3.8. i_d/t Simulation on Different ΔT_m

R_dson and ΔT_m are larger, while i_d is smaller when the others are the same on the branch with a higher T_m. V_th of the test module shows a downward trend as T_m increases. V_th decreases and i_on increases on the branch with a higher T_m. Setting T_m1 > T_m2 > T_m3 > T_m4, the relationship between i_d and T_m is shown in Figure 14. When T_m1, T_m2, T_m3, and T_m4 are set as 5.8 μs, 5.3 μs, 5.1 μs, and 5.2 μs, respectively, the maximum values of i_d are 10.4 A, 10.4 A, 10.3 A, and 10.1 A.

4. Joint Simulation of Multiple Parasitic Parameters in the Double-Pulse Test Circuit

The simulation object is the extreme value of the multiple parasitic parameters on r_Δi during the joint simulation process. The joint simulation circuit of multiple parasitic parameters is designed, as shown in Figure 15.

The active control system of the gate drive circuit is connected to the drain first during the joint-simulation process. It takes a specific reaction time from detecting the parallel current-sharing imbalance to the beginning of suppression. The reaction time is about 0 due to the magnetic ferrite inductance connected to the wound coil of the drain. The r_Δi of the magnetic ferrite inductance is relatively weak, and r_Δi is not affected by hysteresis and other factors normally. The gate circuit actively regulates r_Δi and acts on the gate drive circuit to reduce r_Δi. The simulation results show that the parallel current-sharing control model based on magnetic ferrite inductance and the parallel current-sharing control model based on a gate drive circuit both can effectively reduce r_Δi. The r_Δi is reduced by 2–4.2%, as shown in Figure 16a–f. The combination of the two models can alleviate the hysteresis caused by a high switching frequency and reduce the requirements for the computing power of FPGA.

The parasitic parameters of the test channels numbered DUT1 and DUT10 are consistent, so DUT1 and DUT10 are selected for this experiment and verification. The measurement results are compared with the data manually, and the values of the parasitic parameters in the form of the external parasitic inductance and the connecting capacitance are changed to make the parameters involved in the test fluctuate within 10% of the range specified in the data manually, which is used to verify the simulation results, as shown in Figure 17 and Figure 18. During the experiment, the branch with more extensive parasitic parameters is labeled as 1, and the branch with smaller parasitic parameters is labeled as 2.

Using the consistency of the other parameters, except for the reference factors in the single- and joint-simulation experiments, each branch of the parallel double-pulse test module is driven solely to ensure that the driving signal can be regulated in two experiments, respectively. The optimal test channels in DUT1–DUT10 are selected for parasitic parameters (L_d, L_g, L_s, C_gs, t_d, V_on, R_on, and ΔT_m), as DUT9 and DUT10 are used as standard channels. Under the single- and joint-simulation experiments, the larger test data are marked as 1, while the smaller test data are marked as 2 to obtain the suppression effect on r_Δi.

The maximum L_g is on DUT5, and the minimum L_g is on DUT7. The maximum L_d is on DUT3, and the minimum L_g is on DUT5. The maximum L_s is on DUT4, and the minimum L_s is on DUT3. The maximum C_gs is on DUT1, and the minimum L_g is on DUT8. The parasitic parameters (L_d, L_g, L_s, C_gs, t_d, V_on, R_on, and ΔT_m) are tested independently on the DUT1–DUT10 channels by the parallel double-pulse test modules, respectively. The single- and joint-simulation suppression experiments of single magnetic ferrite inductance and the single- and joint-simulation suppression experiments of magnetic ferrite inductance combined with a gate drive circuit are carried out, as shown in Figure 19 and Figure 20.

The standard values of parasitic parameters are set according to Table 1. L_s, L_d, L_g, C_gs, T_dely, R_on, V_on, and T_m are respectively set as 10 nH, 6 nH, 15 nH, 25 pF, 10 ns, 10 Ω, 18 V, and 35 °C to realize that the standard value of the parallel current is maintained at 10 A. The r_Δi on multiple parasitic parameters is shown in Table S3. It is obvious that L_s, L_d, and L_g optimize the parallel current-sharing imbalance; the r_Δi is generally between 5% and 10%. L_g has a minimal influence on r_Δi; the r_Δi is about 6%, while L_d has a maximal influence on the parallel current-sharing imbalance; the r_Δi is about 9%. C_gs is the most sensitive to the parallel current-sharing imbalance. The r_Δi is about 11% by increasing C_gs every 5 pF, as shown in Table S4. The parallel current-sharing imbalance is reversed by changing the delay direction of the driving signals on branch I and branch II. The r_Δi is 0 as the delay of the driving signal is 0. R_on and V_on regulate r_Δi through the gate drive circuit; the r_Δi is about 5% and 6%, respectively. T_m optimizes the parallel current-sharing imbalance through the changes in device performance; the r_Δi is about 7%.

As shown in Figure 21, the r_Δi of L_d, L_g, and L_s on the parallel current-sharing imbalance is nonlinear. The initial r_Δi of L_s, L_d, and L_g is 1.7%, 2.0%, and 2.8%, respectively. L_d, L_g, and L_s are independently set to 5 nH, 10 nH, and 15 nH; the r_Δi reaches the maximum value, which is 8%, 9%, and 6% respectively.

The delay of the forward/reverse driving signal impacts r_Δi symmetrically, as shown in Figure 22. The interference of other irrelevant signals leading to the existence of fluctuation deviation is shown in the red box of Figure 22. The r_Δi reaches the maximum/minimum values of 5% and −5.3% when the forward and reverse driving signals are delayed by 10 ns. The average values of r_Δi on the forward and reverse driving signals are approximately 3.0% and −3.2% because of the existence of irrelevant signal interference. The average value of r_Δi is approximately equal to the average value of r_Δi on the reverse driving signal on the forward driving signal, assuming that the interference of irrelevant signals is excluded. The forward/reverse driving signals affect the parallel current-sharing imbalance similarly, while the direction is opposite.

5. Conclusions

The parallel current-sharing imbalance affected by multiple parasitic parameters (L_d, L_g, L_s, C_gs, t_d, V_on, R_on, and ΔT_m) wa investigated by single and joint simulations and suppression experiments. It was found that the r_Δi of L_d, L_g, and L_s is between 5% and 10%. When L_d, L_g, and L_s were independently set to 5 nH, 10 nH, and 15 nH, r_Δi reached the maximum value, which is 8%, 9%, and 6% respectively. The effect of the parasitic inductance of the parallel double-pulse test module on r_Δi was L_g > L_s > L_d. The r_Δi of the C_gs was approximately 9% to 11%. The r_Δi reached a maximum of about ±5% as the forward/reverse driving signals were delayed by 10 ns. The r_Δi is smaller with a larger V_on, smaller R_on, and larger ΔT_m. This work complements the investigation of current-sharing imbalance with multiple parasitic parameters using the sum of the differential magnetic flux. An improved parallel current-sharing imbalance control model consisting of ferrite inductance and a gate drive circuit was proposed, which respectively reduced r_Δi by more than 5% and 2–4.2%, compared with using a gate drive circuit alone and using magnetic ferrite inductance solely. The model is expected to be used to suppress the occurrence of high-frequency parallel current-sharing imbalances, especially.