FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits
Abstract
:1. Introduction
2. Materials and Methods
2.1. The Chua Circuit
2.2. Existence and Uniqueness of the Chua Circuit State Equations
- : the function is continuous and differentiable, with typically being a piecewise linear function. This ensures Lipschitz continuity.
- : This is a linear function and is Lipschitz-continuous.
- : This is also a linear function and is Lipschitz-continuous.
2.3. Synchronization of Chua Circuits
2.4. Numerical Procedures for Solving ODEs
2.5. Software-Based Numerical Simulation
2.6. Hardware-Based Numerical Simulation
3. Results
4. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
Appendix A
//‘timescale <time_units> / <precision> | ||
module chua (clk,x, y, z); | ||
parameter integerBits= 6; | ||
parameter fractionBits=25 ; | ||
parameter dtBits=16 ; | ||
parameter dtShift=30 ; | ||
parameter iteratorBits=16 ; | ||
parameter signed [integerBits + fractionBits : 0 ] dt=0.005 *(2.0 ** (fractionBits)); | ||
parameter [iteratorBits - 1 : 0 ] skip=1024 ; | ||
parameter signed [integerBits + fractionBits : 0 ] sigma=15.0 * 1 *(2.0 **(fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0 ] rho=1.0 * 1 *(2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0 ] beta =28.0 * 1 *(2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0 ] m1=-0.714 * 1 *(2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0 ] m0mm1x05=-0.2145 *1 * (2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0 ] startX=0.7 * 1 *(2.0 ** fractionBits); | ||
parameter signed [integerBits + fractionBits : 0 ] startY=0.0 * 1 *(4.0 ** fractionBits); | ||
parameter signed [integerBits + fractionBits : 0 ] startZ=0.0 * 1 *(2.0 ** fractionBits); | ||
localparam totalBits = 1 + integerBits + fractionBits; | ||
input wire clk; | ||
output reg signed [totalBits-1 :0 ] x = startX; | ||
output reg signed [totalBits-1 :0 ] y = startY; | ||
output reg signed [totalBits-1 :0 ] z = startZ; | ||
reg [iteratorBits-1 :0 ] iterator = 0 ; | ||
reg signed [totalBits-1 :0 ] a = startX; | ||
reg signed [totalBits-1 : 0 ] b = startY; | ||
reg signed [totalBits -1 :0 ] c = startZ; | ||
reg signed [totalBits*2 -1 :0 ] h = 0 ; | ||
reg signed [totalBits-1 :0 ] abs1 = 0 ; | ||
reg signed [totalBits-1 :0 ] abs2 = 0 ; | ||
reg signed [totalBits*2 -1 :0 ] dxdt = 0 ; | ||
reg signed [totalBits*2 -1 :0 ] dydt = 0 ; | ||
reg signed [totalBits*2 -1 :0 ] dzdt = 0 ; | ||
reg signed [totalBits - 1 : 0 ] res = 0 ; | ||
always @(posedge clk) | ||
begin | ||
iterator <= iterator+1 ; | ||
if (!iterator) | ||
begin | ||
x = a; | ||
y = b; | ||
z = c; | ||
end | ||
else | ||
begin | ||
if (iterator == skip) | ||
Begin | ||
a = x; | ||
b = y; | ||
c = z; | ||
End | ||
abs1=x+32 ’h04000000 ; | ||
if (abs1<0 ) begin | ||
abs1=-abs1; | ||
end | ||
abs2=(x-32 ’h04000000 ); | ||
if (abs2<0 ) begin | ||
abs2=-abs2; | ||
end | ||
h=(m1*x+m0mm1x05*(abs1-abs2))>>>fractionBits; | ||
dxdt = (sigma * (y - x-h)) >>> fractionBits; | ||
dydt = x -y+z; | ||
dzdt = (-beta* y) >>> fractionBits; | ||
x = x + ((dxdt * dt) >>> fractionBits); | ||
y = y + ((dydt * dt) >>> fractionBits); | ||
z = z + ((dzdt * dt) >>> fractionBits); | ||
end | ||
end | ||
endmodule |
Appendix B
‘timescale 1ns / 1ps | ||
module chuaN(clk,x1,x2,x,y,z); | ||
parameter integerBits = 6; | ||
parameter fractionBits = 25; | ||
parameter dtBits = 16; | ||
parameter dtShift = 30; | ||
parameter iteratorBits = 16; | ||
parameter signed [integerBits + fractionBits : 0] dt=0.0005 *(2.0 ** (fractionBits)); | ||
parameter [iteratorBits - 1:0] skip = 1024; | ||
parameter signed [integerBits + fractionBits:0] sigma = 15.0 * 1*(2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0] rho = 1.0 * 1*(2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0] beta = 28.0 * 1*(2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0] m1 = -0.714 * 1*(2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0] m0mm1x05 = -0.2145 *1* (2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0] startX = 0.7 * 1*(2.0 ** fractionBits); | ||
parameter signed [integerBits + fractionBits : 0] startY = 0.0 * 1*(2.0 ** fractionBits); | ||
parameter signed [integerBits + fractionBits : 0] startZ = 0.0 * 1*(2.0 ** fractionBits); | ||
parameter signed [integerBits + fractionBits : 0] deltaX = 7 * (2.0 ** (fractionBits)); | ||
parameter signed [integerBits + fractionBits : 0] uno = 1 * (2.0 ** (fractionBits)); | ||
localparam totalBits = 1 + integerBits + fractionBits; | ||
input wire clk; | ||
input signed [totalBits – 1 : 0] x2; | ||
input signed [totalBits – 1 :0] x1; | ||
output reg signed [totalBits - 1 : 0] x = startX; | ||
output reg signed [totalBits - 1 : 0] y = startY; | ||
output reg signed [totalBits - 1 : 0] z = startZ; | ||
reg [iteratorBits - 1 : 0] iterator = 0; | ||
reg signed [totalBits - 1 : 0] a = startX; | ||
reg signed [totalBits - 1 : 0] b = startY; | ||
reg signed [totalBits - 1 : 0] c = startZ; | ||
reg signed [totalBits * 2 - 1 : 0] h = 0; | ||
reg signed [totalBits - 1 : 0] abs1 = 0; | ||
reg signed [totalBits - 1 : 0] abs2 = 0; | ||
reg signed [totalBits * 2 - 1 : 0] dxdt = 0; | ||
reg signed [totalBits * 2 - 1 : 0] dydt = 0; | ||
reg signed [totalBits * 2 - 1 : 0] dzdt = 0; | ||
reg signed [totalBits - 1 : 0] res = 0; | ||
always @(posedge clk) | ||
begin | ||
iterator <= iterator + 1; | ||
if (!iterator) | ||
begin | ||
x = a; | ||
y = b; | ||
z = c; | ||
end | ||
else | ||
begin | ||
if (iterator == skip) | ||
begin | ||
a = x; | ||
b = y; | ||
c = z; | ||
end | ||
abs1=x+uno; | ||
if(abs1<0) begin | ||
abs1=-abs1; | ||
end | ||
abs2=(x-uno); | ||
if(abs2<0) begin | ||
abs2=-abs2; | ||
end | ||
h=(m1*x+m0mm1x05*(abs1-abs2))>>>fractionBits; | ||
dxdt = (sigma * (y - x-h)-deltaX*(2*x-x1-x2)) >>> fractionBits; | ||
dydt = x -y+z; | ||
dzdt = (-beta* y) >>> fractionBits; | ||
x = x + ((dxdt * dt) >>> fractionBits); | ||
y = y + ((dydt * dt) >>> fractionBits); | ||
z = z + ((dzdt * dt) >>> fractionBits); | ||
end | ||
end | ||
endmodule |
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Number | Binary | Hexadecimal |
---|---|---|
1.0 | 0_000001.0000000000000000000000000 | 02000000 |
0.0025 | 0_000000.0000000101000111101011100 | 00028F5C |
Logic Utilization | Used | Utilization |
---|---|---|
Number of Slice Flip Flop | 29 | 1% |
Number of 4 input LUTs | 16 | 1% |
Number of occupied Slices | 25 | 1% |
Number of bonded IOBs | 3 | 1% |
Variable x | Variable y | r | Lineal Model y = mx + b | |
---|---|---|---|---|
b | m | |||
1.0 | −0.00001635 | 1.00000263 | ||
1.0 | −0.00001541 | 1.00000245 | ||
1.0 | −0.00001541 | 1.00000245 | ||
0.9999887 | 0.00001353 | 1.00001967 | ||
0.9999498 | 0.00002214 | 1.00002846 | ||
0.9999498 | 0.00002214 | 1.00002846 | ||
0.9999788 | 0.0001184 | 1.0000158 | ||
0.9999925 | 0.00005549 | 1.00001217 | ||
0.9999925 | 0.00005549 | 1.00001217 |
Tool | Number of Chua Circuits | Simulation Time |
---|---|---|
Octave (Intel(R) Core i7-9750H CPU 2.59 GHz computer) | 1 | 493 ms |
3 | 3.177 s | |
FPGA | 1 | 0.2 ms |
3 | 0.2 ms |
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Rentería, L.; Mayacela, M.; Torres, K.; Ramírez, W.; Donoso, R.; Acosta, R. FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits. Computation 2024, 12, 174. https://doi.org/10.3390/computation12090174
Rentería L, Mayacela M, Torres K, Ramírez W, Donoso R, Acosta R. FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits. Computation. 2024; 12(9):174. https://doi.org/10.3390/computation12090174
Chicago/Turabian StyleRentería, Leonardo, Margarita Mayacela, Klever Torres, Wladimir Ramírez, Rolando Donoso, and Rodrigo Acosta. 2024. "FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits" Computation 12, no. 9: 174. https://doi.org/10.3390/computation12090174