1. Introduction
In a solid-state device, charge carriers interact with the lattice vibrations (phonons) of a material under an externally applied electric field. As a result, some of the applied electrical energy is converted into thermal energy; a phenomenon called Joule heating [
1,
2]. The Joule heating in electronic devices is a significant hindrance to their safe functionality and efficient performance. It is vital for most of the electronic components, such as integrated circuits, microprocessors and control systems, to maintain the low operating temperatures (below ~85 °C) to ensure durability, stable operation and prevention of thermal hazards [
3,
4].
The Joule heating effect becomes more challenging in modern electronics due to the recent developments in micro- and nano-scale technologies. The miniaturization of solid-state electronic devices has progressed at an exponential scale in line with Moore’s law, with transistor density doubling roughly every two years [
5]. As a result, the 10 nm node has already been realized [
6]. Simultaneously, Dennard scaling, which postulates that the transistor power density remains constant as dimensions are reduced, broke down around 2006, meaning that the modern electronic components are unable to operate within the same power envelope [
7,
8]. Therefore, the static power losses increase rapidly as a proportion of the overall supplied power with decreasing device dimensions and applied voltages. In addition to this, the static power losses are also a function of the device temperature, and thus directly depend upon the total dissipated power [
9].
More importantly, the increased static power losses at smaller dimensions adversely affect the thermal conductivity of materials due to phonon confinement effects and the increased boundary scattering [
1,
10]. These enhanced scattering events increasingly randomize the momenta of phonons, raising the internal energy of the device, and consequently its operational temperature. These factors, along with enhanced chip density, have led to a drastic increase in the power density for high-performance processors. Furthermore, the increased thermal impedance in smaller devices leads to localized hotspot formation, which is a major concern for future circuit design. Therefore, reconsideration of cooling techniques and related favorable device structures with optimized design and performance parameters are necessary to prevent thermal runaway and breakdown.
For a conventional bulk electronic system, the classical Fourier’s law is employed to analyze the self-heating problems. For nanoscale electronics, wherein the physical size of the device is smaller than the phonon mean free path (200–300 nm for silicon at room temperature [
11]), Fourier’s law is no longer applicable. At length scales comparable to or shorter than the phonon wavelength (1–2 nm for silicon at room temperature [
12]), and/or at temperature values much lower than the Debye temperature, the quantum-mechanical behavior of phonons becomes important, which necessitates the use of atomistic approaches like the lattice dynamics equations or the ab initio method [
12,
13,
14,
15]. However, despite aggressive miniaturization, the dimensions (and temperatures) involved in modern electronic devices are not yet as small (low) to require quantum-mechanical modelling, and semi-classical methods such as the Boltzmann transport equation (BTE) suffice.
The BTE method incorporates the effects of external electric fields, electron–phonon interactions, phonon decay and various scattering mechanisms in its self-consistent formulation of phonon and electron transport [
13]. The direct solution of the BTE is a cumbersome process and analytical solutions only exist for simple heat conduction problems [
16]. Alternate approaches to quantify heat generation in nanoscale electronic devices include the drift-diffusion, hydrodynamic and Monte Carlo (MC) simulation methods, which are based on the numerical solution of the BTE. The drift-diffusion and hydrodynamic models are unable to identify the contribution of the individual phonon modes to heat generation [
17,
18,
19]. Therefore, the determination of the energy-dependent scattering rates in mesoscopic devices with the desired level of accuracy becomes challenging. In contrast, the MC method, despite being stochastic in nature, provides detailed information about phonon generation and the exchange of energy between the charge carriers and the lattice [
18]. This is of critical importance because different phonon modes with different group velocities exhibit varying contributions to heat generation and confinement in electronic devices.
MC simulations have been extensively used in literature to develop an understanding of how changes in device design, material and dimensions affect heat generation profiles. The ability to incorporate an accurate treatment of the various scattering mechanisms, and the lack of need to make assumptions regarding the carrier distribution in energy space [
20] make the MC method a comprehensive approach for simulating charge transport in semiconductors. Pop et al. [
21] developed an MC model that incorporated analytical descriptions for the electron band structure and the phonon dispersion relationship of silicon, while neglecting the impact ionization, thus reducing the computational time significantly, but making it suitable only for low-field applications. The same model was further extended to analyze the volumetric heat generation rate in ultra-short silicon devices and to draw comparisons with the drift-diffusion approach [
22].
Electron–electron interactions were first incorporated in the MC simulations of nitride devices by Ashok et al. [
23]. These interactions were found to cause the charge carriers to lose energy more rapidly near the drain contact of the device, compared to when they are not included in the scattering model. Harada et al. [
24] applied the semi-classical MC method to silicon and monolayer graphene devices, and compared the differences in electron transport properties that arise due to the linear band dispersion of graphene. Shomali et al. [
25] performed energy carrier transport simulations using the MC method to investigate the effects of boundary conditions on the temperature distribution profiles and localized hotspots in silicon nanodevices. Fang et al. [
26] demonstrated the contribution of both acoustic and optical phonon emission to the energy loss in silicon and germanium devices through full-band MC simulations. Nghiem et al. [
15] studied the temperature distribution and heat confinement resulting from ballistic transport in a nanoscale silicon sample heated through the top surface by a localized heat source.
Previous studies report that the electron–phonon mean free path lies between 5–10 nm for silicon under typical device operating conditions [
22]. With the industry now aiming for the 5 nm lithography node, it is imperative that the behavior of silicon-based nanoscale electronic devices is studied to develop a fundamental understanding of the impact of increasingly ballistic carrier transport on device performance. Despite extensive MC-based studies of the performance characteristics of sub-micrometer nanoscale devices, detailed investigations of the variation of ballistic-regime device performance with operating conditions are not reported in the literature. This paper, therefore, studies the effects of several potentially critical parameters of interest (applied voltage, channel length, electrode lengths, electrode doping and initial temperature) on the performance parameters (volumetric heat generation rate, electron energy and electron drift velocity) of 1D silicon n
+nn
+ devices in the ballistic transport regime. The applied voltage and device dimensions both are expected to have a significant role in the determination of carrier energies and velocities through their influence on the electric field distribution in the devices. The electrode doping influences the number of available charge carriers present in the devices, and in turn, the electrical resistance of these devices. The initial lattice temperature is also expected to have a significant impact on carrier mobility and the rate of Joule heating in these devices.
2. Materials and Methods
The basics of the ensemble Monte Carlo method as applied to charge transport in semiconductors have been described in detail by Jacoboni and Lugli [
27].
Figure 1 presents a flowchart of the basic steps of the MC model employed in the current study—the simulations have been performed through remote access of the supercomputer at the Research Center for Modelling and Simulation, National University of Sciences and Technology, Islamabad, Pakistan. Several thousand super-particles, each in turn representing billions of real electrons, are used in the transient MC simulations to represent the mobile charge inside the semiconductor. Information about the device geometry, applied electric field and mesh setup, as well as the initial conditions for carrier concentration and doping profiles, are obtained from the output of preliminary simulations performed on a commercial device simulator based on the drift-diffusion model (COMSOL Multiphysics [
28], COMSOL Inc., Stockholm, Sweden). This eliminates the potential convergence issues associated with randomly initialized distributions and thereby enables faster MC computations [
29].
The MC model and related program code ‘MONET’ developed by Pop et al. [
21,
30], which uses an analytical non-parabolic band approximation for electron energy has been employed for this investigation. This approximation, which significantly reduces the computational time in comparison to full-band methods, is justified for sub-bandgap applied voltages and low energy studies, since impact ionization is insignificant at these conditions. For the non-parabolic conduction band with ellipsoidal equi-energetic surfaces, the relationship between the electron energy,
, and the wavevectors,
, can be expressed using the many-valley model as [
27]:
where
is the component of the effective electron mass tensor along the
th direction and
is the reduced Planck’s constant. The temperature dependence of the non-parabolicity parameter
for silicon was incorporated as [
22]:
where
is the bandgap energy at room temperature, and
is the temperature-dependent bandgap, which, for silicon, can be expressed in terms of the absolute temperature
as [
31]:
Therefore, at room temperature,
eV
−1, while using
results in the original parabolic model of Canali et al. [
32].
In the MC simulation, the super-particles are initialized with randomly oriented momenta in numbers proportionate to the mobile charge carrier distribution imported from COMSOL. The charge carriers are then subjected to free flight under the influence of an external electrical field for a certain time interval determined stochastically based on pre-defined scattering event probabilities. Upon undergoing scattering, a new electron state (
,
) is randomly chosen as the initial state for the next free flight interval, while accounting for energy and momentum conservation using a rejection algorithm [
21,
33]. The process then repeats iteratively until the desired precision is achieved. A fictitious self-scattering event is also introduced, which allows the charge carrier to continue its free-flight unimpeded by assigning it the same energy state after the event as before. In this way, the total scattering probability (through all mechanisms, including self-scattering) remains constant and independent of carrier energy. For the non-parabolic band model employed here, the electron velocity
associated with a particular state is determined as [
27]:
where
is the effective mass. Moreover, the total simulation time
is divided into multiple sub-histories over which intermediate ensemble averages are calculated. In
Figure 1,
is the number of time steps over which the intermediate ensemble averages are to be computed (a single sub-history), while
represents the number of time steps that have been simulated since the last ensemble averages were computed. An initial portion of the simulation is not included in the computation of final ensemble averages to exclude the transient effects of the initial condition selection.
Furthermore, the model treats all phonon scattering events inelastically to accurately capture the energy dissipation information for the heat generation calculations. The contribution of each phonon dispersion branch is separately accounted for, with the following analytical isotropic approximation applied:
where
is the phonon frequency,
is the phonon wave vector and the values of the parameters
,
and
, which have units of s
−1, cm s
−1, and cm
2 s
−1 respectively, are chosen separately as below for each of the four phonon modes to replicate the experimentally determined dispersion [
21,
30]:
Ionized impurity scattering, which significantly affects the carrier mobility at high doping concentrations, is incorporated using the model developed by Kosina [
34], also employed by Pop et al. [
22]. The MC model computes the volumetric heat generation rate at steady state as the sum of the energies
of all phonons emitted minus the energies of all phonons absorbed per unit volume over a certain simulation time
as follows:
The Poisson equation is also solved at regular intervals during free-flight to update the electric field self-consistently with the motion of the charge carriers. The super-particles are treated as individual charge carriers during free flight, but as clouds of charges for the Poisson equation solution. The updated charge distribution obtained through the solution of the equation is mapped to the mesh grid using the cloud-in-cell method, which performs a simple weighted linear interpolation of the charge of the cloud onto the adjacent grid nodes. This approach allows for realistic and more accurate simulations in comparison to models that maintain a fixed electric field regardless of charge carrier motion [
27,
29].
Figure 2 shows a schematic of the 1D n
+nn
+ silicon device investigated in the present work, which is a simplified model of the cross-section of a MOSFET channel. This model has an energy band diagram similar to that of a MOSFET channel, with an injection barrier and a highly peaked lateral electric field, and includes impurity scattering and velocity overshoot, but the multi-dimensional potential gradients and confinement effects encountered in full device simulations are not present. This realistic 1D representation has thus been frequently used in the literature [
20,
22,
23,
24] to study the transport phenomena in electronic devices in the primary direction of carrier transport—which fundamentally determine the device performance—in isolation from the complicating factors that arise in a full device simulation together with an increase in the computation time and cost. Moreover, while the MONET program employed in this study is able to simulate carrier transport in two-dimensional geometries, it does not incorporate a Poisson equation solver for the 2D mode. This means that the electric field distribution cannot be updated self-consistently with the motion of charge carriers, rendering the program unable to provide quantitative results and greatly reducing the advantage in accuracy offered by the MC method over the much faster drift-diffusion method for 2D simulations [
35].
The n-type channel of the 1D device shown in
Figure 2 has homogeneous mild doping of 1 × 10
16 cm
−3 (almost intrinsic doping), while the channel length, electrode lengths, electrode doping and applied potential difference are varied systematically for this study. The potential difference across the boundaries is kept constant according to the potential profile obtained from a preliminary drift-diffusion simulation. A periodic boundary condition is applied to the device contacts to ensure current continuity, such that particles escaping from one contact are reintroduced at the other contact with thermal energy and inwards momentum
, calculated as:
where
is the Boltzmann constant and
is a random number uniformly distributed between
and
. A uniform grid is used to simplify the charge assignment process. The effects of grid resolution and the time step size were assessed in a preliminary study and the values of these parameters were carefully chosen to be
nm and
fs from the preliminary study to ascertain the accuracy of the simulations. Furthermore, after analyzing the convergence of the numerical results of this preliminary study, a total simulation time
ps was chosen, with the number of time steps constituting a single sub-history taken to be
. The start of the channel is taken as the reference point of the
-coordinate, unless stated otherwise.
4. Conclusions
In this study, the effects of changing the applied electric field, channel length, electrode lengths, electrode doping and initial lattice temperature on the heat generation, electron energy and electron velocity distributions in nanoscale 1D n+nn+ silicon devices have been investigated through an established ensemble Monte Carlo simulation model. Given the continued focus on device miniaturization, the results of this study are of particular significance to the development of modern electronic devices with a characteristic length scale lying in the ballistic transport regime.
The performance parameters are found to vary linearly with the applied voltage, whereas mutually offset maxima have been observed by varying the channel length due to transition into the ballistic regime. These maxima indicate a significant departure from the performance trends known for longer devices operating in the quasi-ballistic transport regime. Furthermore, results for the impact of the electrode lengths are found to be primarily dependent upon the variation of the potential difference across the three device regions with electrode length, and emphasize the necessity of careful drain and contact design in ultra-short devices, since most of the heat dissipation occurs in the drain region. Given the spatial constraints that are compounded by miniaturization, the incorporation of a heat sink in the vicinity of the drain should thus be of preferential importance.
Moreover, the results indicate that it is essential to consider the trade-off between a reduction in the maximum heat generation rate and a simultaneous reduction in the electrical and thermal conductivities—which leads to inefficient operation and may even cause thermal runaway—as device dimensions are scaled-down. An increase in initial lattice temperature does not have a significant effect on the heat generation rate due to the counteracting contributions of the effects on carrier energy and velocity. The heat generation rate is found, however, to increase with an increase in electrode doping.