Simulation of Figures of Merit for Barristor Based on Graphene/Insulator Junction
Abstract
:1. Introduction
2. Materials and Methods
3. Results
3.1. Tunneling Current Model in GIM Junction
3.2. Fowler–Nordheim Tunneling Model in GIM Junction
3.3. Direct Tunneling Model in GIM Junction
3.4. FNT Barrier Height
3.5. Simulation for Barrier Height Engineering to Improve Delay Time and Cut-Off Frequency
3.6. Simulation for Insulator Thickness Engineering to Improve Power-Delay Product
4. Conclusions
Supplementary Materials
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
Appendix A
References
- Yang, H.; Heo, J.; Park, S.; Song, H.J.; Seo, D.H.; Byun, K.; Kim, P.; Yoo, I.; Chung, H.; Kim, K. Graphene Barristor, a Triode. Science 2012, 336, 1140–1143. [Google Scholar] [CrossRef] [PubMed]
- Ojeda-Aristizabal, C.; Bao, W.; Fuhrer, M.S. Thin-Film Barristor: A Gate-Tunable Vertical Graphene-Pentacene Device. Phys. Rev. B 2013, 88, 035435. [Google Scholar] [CrossRef]
- Parui, S.; Pietrobon, L.; Ciudad, D.; Vélez, S.; Sun, X.; Casanova, F.; Stoliar, P.; Hueso, L.E. Gate-Controlled Energy Barrier at a Graphene/Molecular Semiconductor Junction. Adv. Funct. Mater. 2015, 25, 2972–2979. [Google Scholar] [CrossRef]
- Oh, G.; Kim, J.-S.; Jeon, J.H.; Won, E.; Son, J.W.; Lee, D.H.; Kim, C.K.; Jang, J.; Lee, T.; Park, B.H. Graphene/Pentacene Barristor with Ion-Gel Gate Dielectric: Flexible Ambipolar Transistor with High Mobility and on/off Ratio. ACS Nano 2015, 9, 7515–7522. [Google Scholar] [CrossRef] [PubMed]
- Moon, J.S.; Seo, H.-C.; Stratan, F.; Antcliffe, M.; Schmitz, A.; Ross, R.S.; Kiselev, A.A.; Wheeler, V.D.; Nyakiti, L.O.; Gaskill, D.K.; et al. Lateral Graphene Heterostructure Field-Effect Transistor. IEEE Electron. Device Lett. 2013, 34, 1190–1192. [Google Scholar] [CrossRef]
- Georgiou, T.; Jalil, R.; Belle, B.D.; Britnell, L.; Gorbachev, R.V.; Morozov, S.V.; Kim, Y.-J.; Gholinia, A.; Haigh, S.J.; Makarovsky, O.; et al. Vertical Field-Effect Transistor Based on Graphene—WS 2 Heterostructures for Flexible and Transparent Electronics. Nat. Nanotechnol. 2013, 8, 100–103. [Google Scholar] [CrossRef]
- Parui, S.; Ruiter, R.; Zomer, P.J.; Wojtaszek, M.; Van Wees, B.J.; Banerjee, T. Temperature Dependent Transport Characteristics of Graphene/n-Si Diodes. J. Appl. Phys. 2014, 116, 244505. [Google Scholar] [CrossRef]
- Tian, H.; Tan, Z.; Wu, C.; Wang, X.; Mohammad, M.A.; Xie, D.; Yang, Y.; Wang, J.; Li, L.-J.; Xu, J.; et al. Novel Field-Effect Schottky Barrier Transistors Based on Graphene-MoS 2 Heterojunctions. Sci. Rep. 2014, 4, 5951. [Google Scholar] [CrossRef]
- Jeong, S.-J.; Gu, Y.; Heo, J.; Yang, J.; Lee, C.-S.; Lee, M.-H.; Lee, Y.; Kim, H.; Park, S.; Hwang, S. Thickness Scaling of Atomic-Layer-Deposited HfO2 Films and Their Application to Wafer-Scale Graphene Tunnelling Transistors. Sci. Rep. 2016, 6, 20907. [Google Scholar] [CrossRef]
- Huh, W.; Jang, S.; Lee, J.Y.; Lee, D.; Lee, D.; Lee, J.M.; Park, H.G.; Kim, J.C.; Jeong, H.Y.; Wang, G.; et al. Synaptic Barristor Based on Phase-Engineered 2D Heterostructures. Adv. Mater. 2018, 30, e1801447. [Google Scholar] [CrossRef]
- Hwang, H.J.; Heo, S.; Yoo, W.B.; Lee, B.H. Graphene—ZnO:N Barristor on a Polyethylene Naphthalate Substrate. AIP Adv. 2018, 8, 15022. [Google Scholar] [CrossRef]
- Kim, S.Y.; Hwang, J.; Kim, Y.J.; Hwang, H.J.; Son, M.; Revannath, N.; Ham, M.H.; Cho, K.; Lee, B.H. Threshold Voltage Modulation of a Graphene–ZnO Barristor Using a Polymer Doping Process. Adv. Electron. Mater. 2019, 5, 1800805. [Google Scholar] [CrossRef]
- Shim, J.; Kim, H.S.; Shim, Y.S.; Kang, D.-H.; Park, H.-Y.; Lee, J.; Jeon, J.; Jung, S.J.; Song, Y.J.; Jung, W.S.; et al. Extremely Large Gate Modulation in Vertical Graphene/WSe2Heterojunction Barristor Based on a Novel Transport Mechanism. Adv. Mater. 2016, 28, 5293–5299. [Google Scholar] [CrossRef] [PubMed]
- Lee, J.-H.; Shin, D.H.; Yang, H.; Jeong, N.B.; Park, D.-H.; Watanabe, K.; Taniguchi, T.; Kim, E.; Lee, S.W.; Jhang, S.H.; et al. Semiconductor-Less Vertical Transistor with I ON/I OFF of 106. Nat. Commun. 2021, 12, 1000. [Google Scholar] [CrossRef]
- Tsu, R.; Esaki, L. Tunneling in a Finite Superlattice. Appl. Phys. Lett. 1973, 22, 562–564. [Google Scholar] [CrossRef]
- Gehring, A.; Selberherr, S. Modeling of Tunneling Current and Gate Dielectric Reliability for Nonvolatile Memory Devices. IEEE Trans. Device Mater. Reliab. 2004, 4, 306–319. [Google Scholar] [CrossRef]
- Novoselov, K.S.; Geim, A.K.; Morozov, S.V.; Jiang, D.; Katsnelson, M.I.; Grigorieva, I.V.; Dubonos, S.V.; Firsov, A.A. Two-Dimensional Gas of Massless Dirac Fermions in Graphene. Nature 2005, 438, 197–200. [Google Scholar] [CrossRef]
- Ishigami, M.; Chen, J.H.; Cullen, W.G.; Fuhrer, M.S.; Williams, E.D. Atomic Structure of Graphene on SiO 2. Nano Lett. 2007, 7, 1643–1648. [Google Scholar] [CrossRef]
- Fowler, R.H.; Nordheim, L. Electron Emission in Intense Electric Fields. Proc. R. Soc. Lond. Ser. A Contain. Pap. Math. Phys. Character 1928, 119, 173–181. [Google Scholar] [CrossRef]
- Simmons, J.G. Electric Tunnel Effect between Dissimilar Electrodes Separated by a Thin Insulating Film. J. Appl. Phys. 1963, 34, 2581–2590. [Google Scholar] [CrossRef]
- Britnell, L.; Gorbachev, R.V.; Jalil, R.; Belle, B.D.; Schedin, F.; Mishchenko, A.; Georgiou, T.; Katsnelson, M.I.; Eaves, L.; Morozov, S.V.; et al. Field-Effect Tunneling Transistor Based on Vertical Graphene Heterostructures. Science 2012, 335, 947–950. [Google Scholar] [CrossRef] [PubMed]
- Britnell, L.; Gorbachev, R.V.; Jalil, R.; Belle, B.D.; Schedin, F.; Katsnelson, M.I.; Eaves, L.; Morozov, S.V.; Mayorov, A.S.; Peres, N.M.R.; et al. Electron Tunneling through Ultrathin Boron Nitride Crystalline Barriers. Nano Lett. 2012, 12, 1707–1710. [Google Scholar] [CrossRef] [PubMed]
- Lee, G.-H.; Yu, Y.-J.; Lee, C.; Dean, C.; Shepard, K.L.; Kim, P.; Hone, J. Electron Tunneling through Atomically Flat and Ultrathin Hexagonal Boron Nitride. Appl. Phys. Lett. 2011, 99, 243114. [Google Scholar] [CrossRef]
- Persaud, A. Analysis of Slope-Intercept Plots for Arrays of Electron Field Emitters. J. Appl. Phys. 2013, 114, 154301. [Google Scholar] [CrossRef]
- Gotoh, Y.; Tsuji, H.; Ishikawa, J. Relationships among the Physical Parameters Required to Give a Linear Relation between Slope and Intercept of Fowler-Nordheim Plots. Ultramicroscopy 2001, 89, 63–67. [Google Scholar] [CrossRef]
- Logoteta, D.; Fiori, G.; Iannaccone, G. Graphene-Based Lateral Heterostructure Transistors Exhibit Better Intrinsic Performance than Graphene-Based Vertical Transistors as Post-CMOS Devices. Sci. Rep. 2014, 4, 6607. [Google Scholar] [CrossRef]
- Liang, S.J.; Hu, W.; Di Bartolomeo, A.; Adam, S.; Ang, L.K. A Modified Schottky Model for Graphene-Semiconductor (3D/2D) Contact: A Combined Theoretical and Experimental Study. In Proceedings of the 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3–7 December 2016; pp. 14.4.1–14.4.4. [Google Scholar] [CrossRef]
- Yu, Y.-J.; Zhao, Y.; Ryu, S.; Brus, L.E.; Kim, K.S.; Kim, P. Tuning the Graphene Work Function by Electric Field Effect. Nano Lett. 2009, 9, 3430–3434. [Google Scholar] [CrossRef]
- Schwierz, F. Graphene Transistors. Nat. Nanotechnol. 2010, 5, 487–496. [Google Scholar] [CrossRef]
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Lee, J.-H.; Choi, I.; Jeong, N.B.; Kim, M.; Yu, J.; Jhang, S.H.; Chung, H.-J. Simulation of Figures of Merit for Barristor Based on Graphene/Insulator Junction. Nanomaterials 2022, 12, 3029. https://doi.org/10.3390/nano12173029
Lee J-H, Choi I, Jeong NB, Kim M, Yu J, Jhang SH, Chung H-J. Simulation of Figures of Merit for Barristor Based on Graphene/Insulator Junction. Nanomaterials. 2022; 12(17):3029. https://doi.org/10.3390/nano12173029
Chicago/Turabian StyleLee, Jun-Ho, Inchul Choi, Nae Bong Jeong, Minjeong Kim, Jaeho Yu, Sung Ho Jhang, and Hyun-Jong Chung. 2022. "Simulation of Figures of Merit for Barristor Based on Graphene/Insulator Junction" Nanomaterials 12, no. 17: 3029. https://doi.org/10.3390/nano12173029