Highly Adaptive Reconfigurable Receiver Front-End for 5G and Satellite Applications
Abstract
:1. Introduction
2. Highly Adaptive Reconfigurable Receiver Front-End (HARRF) for 5G and Satellite Applications
2.1. Conceptual Design Objectives
- High Linearity: Ensuring minimal distortion under high-power signal conditions.
- Low Noise Figure (NF): Optimising the sensitivity of the receiver.
- Adequate Gain: Maintaining sufficient signal amplification while minimising losses.
- Efficient Switching Mechanism: Seamless transition between X-band and K/Ka-band with minimal insertion loss.
- Wideband Operation: Supporting mmWave 5G FR2 applications with bandwidth flexibility.
2.2. Design Parameter Definitions
- Noise Figure (NF):
- Gain ():
- Linearity and Third-Order Intercept Point (IP3):
2.3. Design Process Flow
3. Switchable Receiver Front-End Architecture: HARRF LNA and SPDT Integration
3.1. Mathematical Model of the Receiver Frontend
- -
- represents the noise figure of each stage,
- -
- denotes the gain of the preceding stages.
3.2. Transmission Line Integration
- -
- is the transmission line impedance,
- -
- is the propagation constant,
- -
- l is the transmission line length.
3.3. Impedance Matching Between the Switch and the LNA
3.4. Impact on Noise Figure and Gain
4. Active Device Technology S-Parameter Extraction
4.1. I-V Characteristics of pHEMT Devices
4.2. Transconductance Characteristics
4.3. Reflection Coefficient and Matching Conditions
5. HARRF LNA Design
5.1. X-Band LNA Design Procedure
5.1.1. Stage-by-Stage Design Considerations
- Stage one: The first stage consists of a transistor of size , using inductive source feedback for stabilisation. This feedback helps bring the optimum noise match close to the gain match, thereby reducing the overall noise figure. The input source impedance is 50 , and the input matching network was implemented using an LC combination (series inductor and capacitor).
- Stage two: The second stage also employs a transistor of size . An inter-stage matching network is used between stages one and two to transform the output impedance of stage one to the input impedance of stage two. The goal is to provide the maximum stable gain and linearity while maintaining stability.
- Stage three: The final stage uses a transistor of size . The output of stage two is matched to the input of stage three to maximise the overall gain. A parallel feedback network is introduced in this stage to achieve gain flatness and to boost output power handling.
- Capacitors C1 and C10 act as DC blocks, preventing DC voltage from flowing along the RF path.
- Capacitors C2, C4, C5, C7, C8, and C9 are bypass or decoupling capacitors connected to the bias lines to reduce the coupling of RF signals into the power supply.
- Resistors R1, R3, and R5 are high-value resistors used to isolate RF signals from the DC supply.
- The input matching network for the first stage is formed by C1 and L1, ensuring that the amplifier sees at the transistor’s gate when terminated in 50 .
- The output matching network is composed of L6 and C10, allowing for proper load matching.
5.1.2. Noise Figure Design Considerations
5.1.3. X-Band LNA S-Parameter Analysis
5.1.4. State-of-the-Art in X-Band LNA Design
5.2. K/Ka-Band LNA Design Procedure
5.2.1. Stage-by-Stage Design Considerations
- Stage one: The first stage uses a pHEMT with inductive source feedback to achieve the optimum noise match () for the target frequency. The inter-stage matching network transforms the 50 input source impedance to the required noise match impedance.
- Stage two: The second stage also uses a pHEMT. The inter-stage matching network ensures that the output impedance of stage one is properly matched to the input impedance of stage two to maintain maximum stable gain.
- Stage three: A pHEMT is employed in the final stage to provide higher output power. Parallel feedback is introduced to enhance gain flatness across the entire band of operation.
- C1 and C11 serve as DC blocking capacitors, preventing DC currents from flowing along the RF path.
- C2, C4, C5, C7, C8, and C10 are power supply decoupling capacitors to isolate RF signals from the bias lines.
- R1, R3, and R5 are large-valued resistors that help in reducing RF coupling into the DC supply.
- The third stage employs a series RC feedback network (C9 and R6) to achieve the desired gain flatness.
- M1, M2, and M3 denote the pHEMT devices in stages one, two, and three, respectively.
5.2.2. K/Ka-Band LNA S-Parameter Analysis
5.2.3. Comparison with State-of-the-art K/Ka-Band LNAs
6. HARRF SPDT Design
6.1. FET Device Biasing
- ON State: Gate voltage . The low gate-source voltage produces a low channel resistance () and enables the RF signal to pass from drain to source.
- OFF State: Gate voltage . The transistor channel is pinched off, creating a high channel resistance (), thereby blocking the RF signal path.
6.2. Scattering Parameters (S-Parameters)
- is the reflection coefficient at port 1.
- , are the transmission coefficients from port 1 to ports 2 and 3, respectively.
- , represent the transmission from ports 2 and 3 back to port 1, respectively.
- is the reflection coefficient at port 2.
- is the reflection coefficient at port 3.
- , indicate the transmission between ports 2 and 3.
6.2.1. Network Power Relations
6.2.2. Integral Measures over Frequency
6.3. Incident and Reflected Waves
Power Consistency Check
6.4. Key Performance Metrics
6.4.1. Insertion Loss
6.4.2. Isolation
6.4.3. Return Loss
- Two series FETs to improve power handling and ensure operation down to DC.
- Four shunt-stacked FET units to enhance isolation by absorbing the off-state capacitance into a low-pass filter section.
6.5. Series vs. Shunt FET Configuration
- Series FETs: Used primarily to handle higher power and to lower the ON resistance. By stacking multiple FETs in series, the drain-source voltage across each FET is reduced, mitigating breakdown issues at high power levels or high operating voltages.
- Shunt FETs: These help improve isolation by providing an alternate low-impedance path to ground when they are turned ON (pinched-off for the main path). In the distributed design, the parasitic off-state capacitance of the shunt FETs can be absorbed into the matching network, effectively extending the bandwidth of operation.
7. Result Analysis of Wideband SPDT Switch and Reconfigurable Front-End
7.1. Comparison with State-of-the-Art Designs
7.2. SPDT Integration with X-Band ON and K/Ka-Band OFF
7.2.1. Gain Performance
7.2.2. Noise Performance
7.2.3. Reflection Coefficients
7.2.4. Stability
7.3. SPDT Integration with X-Band OFF and K/Ka-Band ON
7.3.1. Gain Performance
7.3.2. Noise Performance
7.3.3. Reflection Coefficients
7.3.4. Stability
8. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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Ref. | Process | Application | Freq. (GHz) | Gain (dB) | Noise (dB) | Power (mW) |
---|---|---|---|---|---|---|
[19] | 0.7 GaAs mHEMT | SATCOM | 7–11 | 30 | 1 | 62.2 |
[20] | 0.65 CMOS | SATCOM | 9.35–10.65 | 27.8 | 1.8 | 4.68 |
[21] | 0.13 SiGe BiCMOS | SATCOM | 6–12 | 21 | 1.7 | 100 |
[22] | 0.65 CMOS | SATCOM | 8–12 | 15 | 8.4 | 110 |
[23] | 0.18 CMOS | SATCOM | 6.4–7.4 | 12.5 | 3 | 19 |
[24] | 0.1 GaAs mHEMT | SATCOM | 4–12 | 31.5 | 1.31 | 8 |
[25] | 0.1 InP HEMT | SATCOM | 0.3–14 | 40 | 2.73 | 12 |
[15] | 0.15 InGaAs pHEMT | SATCOM | 8–12 | 40 | 0.9 | 43 |
Ref. | Process | Application | Freq. (GHz) | Gain (dB) | Noise (dB) | Power (mW) |
---|---|---|---|---|---|---|
[13] | 0.4 CMOS SOI | SATCOM | 20–22 | 3-17 | 8 | 2.82 |
[26] | 0.25 SiGe | SATCOM | 19.7–21 | 0 | 5 | 0.24 |
[27] | 0.4 CMOS | 5G | 26.5–29.5 | 0 | 4.2 | 0.9 |
[28] | 0.28 CMOS | 5G | 25.8–28 | 30–69 | 6.7 | 0.4 |
[29] | 0.13 SiGe | 5G | 27.5–29 | 30 | 3.7 | 3.3 |
[30] | 0.65 CMOS | SATCOM | 17–21 | 16–34 | 5.4 | 0.93 |
[31] | 0.15 AlGaAs-InGaAs pHEMT | 5G | 26-33 | 22.8 | 1.6 | - |
[24] | 0.1 GaAs mHEMT | 5G | 25–34 | 24.2 | 3.04 | 2.8 |
[25] | 0.1 InP HEMT | SATCOM/5G | 16–28 | 32.3 | 4.11 | 3.5 |
[32] | GaAs pHEMT | SATCOM | 18–21.6 | 30.3 | 1 | 60 |
[33] | 0.1 GaAs pHEMT | SATCOM/5G | 18–43 | 21.6 | 1.8–2.7 | 140 |
[34] | 0.25 SiGe | 5G | 24–34 | 26.4 | 3.1–3.5 | 134 |
[35] | 0.4 CMOS | 5G | 26–33 | 27.1 | 3.3–4.3 | 31.4 |
[18] | 0.15 InGaAs pHEMT | 5G | 23–28 | 30.8 | 1.7 | 43 |
Band | SPDT On-State | SPDT Off-State | ||
---|---|---|---|---|
Left Arm | 0 V | 2 V | −1.5 V | 0 V |
Right Arm | 2 V | 0 V | 0 V | −1.5 V |
Design Parameter | Requirement | 10 GHz | 26 GHz | 38 GHz |
---|---|---|---|---|
(dB) | −16 | −21 | −17 | |
(dB) | −70 | −55 | −50 | |
(dB) | −3 | −3 | −4 | |
(dB) | −15 | −18 | −20 |
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Uko, M.; Ekpo, S.; Enahoro, S.; Elias, F.; Unnikrishnan, R.; Al-Yasir, Y. Highly Adaptive Reconfigurable Receiver Front-End for 5G and Satellite Applications. Technologies 2025, 13, 124. https://doi.org/10.3390/technologies13040124
Uko M, Ekpo S, Enahoro S, Elias F, Unnikrishnan R, Al-Yasir Y. Highly Adaptive Reconfigurable Receiver Front-End for 5G and Satellite Applications. Technologies. 2025; 13(4):124. https://doi.org/10.3390/technologies13040124
Chicago/Turabian StyleUko, Mfonobong, Sunday Ekpo, Sunday Enahoro, Fanuel Elias, Rahul Unnikrishnan, and Yasir Al-Yasir. 2025. "Highly Adaptive Reconfigurable Receiver Front-End for 5G and Satellite Applications" Technologies 13, no. 4: 124. https://doi.org/10.3390/technologies13040124
APA StyleUko, M., Ekpo, S., Enahoro, S., Elias, F., Unnikrishnan, R., & Al-Yasir, Y. (2025). Highly Adaptive Reconfigurable Receiver Front-End for 5G and Satellite Applications. Technologies, 13(4), 124. https://doi.org/10.3390/technologies13040124