Bisimulation for Secure Information Flow Analysis of Multi-Threaded Programs
Abstract
:1. Introduction
2. Preliminaries and Assumptions
2.1. Program Model
l:=0; l:=1 || if l=1 then l:=h (P1)
2.2. Attacker Model
2.3. Low-Bisimulation
- 1.
- .
- 2.
- If with , then there exists a finite path fragment with and , and .
- 3.
- If with , then there exists a finite path fragment with and , and .
3. Related Work
4. The Proposed Approach
4.1. Bisimulation-Based Observational Determinism
l:=0; h:=l+3; l:=l+1 (P2)
if l>0 then h:=h+1 else h:=0 (P3)
l:=0; while h>0 do {l++; h--} (P4)
l:=0; if h>0 then l:=1 else {sleep 100; l:=1} (P5)where sleep 100 means 100 consecutive skip commands. The Kripke structure of the program is depicted in Figure 4.
l:=0 l:=2 || (if h=1 then sleep 100); l:=1 (P6)
4.2. Verifying BOD
4.2.1. The Algorithm
Algorithm 1 Verification of BOD |
|
4.2.2. Correctness of the Algorithm
4.2.3. Complexity of the Algorithm
4.2.4. Implementation and Case Study
Thread α: while mask != 0 do while trigger0 = 0 do; /* busy waiting */ result := result | mask ; /* bitwise ‘or’ */ trigger0 := 0; maintrigger := maintrigger + 1; if maintrigger = 1 then trigger1 := 1 Thread β: while mask != 0 do while trigger1 = 0 do; /* busy waiting */ result := result & ~ mask ; /* bitwise ‘and’ with the complement of mask */ trigger1 := 0; maintrigger := maintrigger + 1; if maintrigger = 1 then trigger0 := 1 Thread γ: while mask != 0 do maintrigger := 0; if (PIN & mask ) = 0 then trigger0 := 1 else trigger1 := 1; while maintrigger != 2 do; /* busy waiting */ mask := mask / 2; trigger0 := 1; trigger1 := 1
5. Conclusions and Future Work
Author Contributions
Funding
Conflicts of Interest
Appendix A
dtmc const int n = 3; // num of bits of the pin variable global result : [0.. pow (2, n) -1]; global mask : [0.. pow (2, n) -1]; global pin : [0.. pow (2, n) -1]; global trigger0 : [0..1]; global trigger1 : [0..1]; global maintrigger : [0..2]; global turn : [1..3]; module Alpha c1 : [0..5]; [] turn =1 & c1 =0 & mask !=0 -> (c1 ’=1); [] turn =1 & c1 =1 & trigger0 =0 & trigger1 =1 -> (turn ’=2); [] turn =1 & c1 =1 & trigger0 =0 & trigger1 !=1 -> (turn ’=3); [] turn =1 & c1 =1 & trigger0 !=0 -> (c1 ’=2); [] turn =1 & c1 =2 & mod( floor ( result / mask ) ,2)=0 & result +mask <= pow (2,n)-1 -> ( result ’= result + mask ) & (c1 ’=3); [] turn =1 & c1 =2 & mod( floor ( result / mask ) ,2)=1 -> (c1 ’=3); [] turn =1 & c1 =3 -> ( trigger0 ’=0) & (c1 ’=4); [] turn =1 & c1 =4 & maintrigger <2 -> ( maintrigger ’= maintrigger +1) & (c1 ’=5); [] turn =1 & c1 =5 & maintrigger =1 -> ( trigger1 ’=1) & (c1 ’=0); [] turn =1 & c1 =5 & maintrigger !=1 -> (c1 ’=0); endmodule module Beta c2 : [0..5]; [] turn =2 & c2 =0 & mask !=0 -> (c2 ’=1); [] turn =2 & c2 =1 & trigger1 =0 & trigger0 =1 -> (turn ’=1); [] turn =2 & c2 =1 & trigger1 =0 & trigger0 !=1 -> (turn ’=3); [] turn =2 & c2 =1 & trigger1 !=0 -> (c2 ’=2); [] turn =2 & c2 =2 & mod( floor ( result / mask ) ,2)=1 -> (result ’= result - mask ) & (c2 ’=3); [] turn =2 & c2 =2 & mod( floor ( result / mask ) ,2)=0 -> (c2 ’=3); [] turn =2 & c2 =3 -> ( trigger1 ’=0) & (c2 ’=4); [] turn =2 & c2 =4 & maintrigger <2 -> ( maintrigger ’= maintrigger +1) & (c2 ’=5); [] turn =2 & c2 =5 & maintrigger =1 -> ( trigger0 ’=1) & (c2 ’=0); [] turn =2 & c2 =5 & maintrigger !=1 -> (c2 ’=0); endmodule module Gamma c3 : [0..6]; [] turn =3 & mask !=0 & c3 =0 -> (c3 ’=1); [] turn =3 & mask =0 & c3 =0 -> (c3 ’=5); [] turn =3 & c3 =1 -> ( maintrigger ’=0) & (c3 ’=2); [] turn =3 & c3 =2 & mod( floor ( pin / mask ) ,2)=0 -> ( trigger0 ’=1) & (c3 ’=3); [] turn =3 & c3 =2 & mod( floor ( pin / mask ) ,2)=1 -> ( trigger1 ’=1) & (c3 ’=3); [] turn =3 & c3 =3 & maintrigger =2 -> (c3 ’=4); [] turn =3 & c3 =3 & maintrigger !=2 -> 0.5:( turn ’=1) + 0.5:( turn ’=2); [] turn =3 & c3 =4 -> (mask ’= floor ( mask /2)) & (c3 ’=0); [] turn =3 & c3 =5 -> ( trigger0 ’=1) & (c3 ’=6); [] turn =3 & c3 =6 -> ( trigger1 ’=1) ; endmodule init mask =2 & result =0 & maintrigger =0 & trigger0 =0 & trigger1 =0 & c1 =0 & c2 =0 & c3 =0 & turn =3 endinit
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Noroozi, A.A.; Karimpour, J.; Isazadeh, A. Bisimulation for Secure Information Flow Analysis of Multi-Threaded Programs. Math. Comput. Appl. 2019, 24, 64. https://doi.org/10.3390/mca24020064
Noroozi AA, Karimpour J, Isazadeh A. Bisimulation for Secure Information Flow Analysis of Multi-Threaded Programs. Mathematical and Computational Applications. 2019; 24(2):64. https://doi.org/10.3390/mca24020064
Chicago/Turabian StyleNoroozi, Ali A., Jaber Karimpour, and Ayaz Isazadeh. 2019. "Bisimulation for Secure Information Flow Analysis of Multi-Threaded Programs" Mathematical and Computational Applications 24, no. 2: 64. https://doi.org/10.3390/mca24020064
APA StyleNoroozi, A. A., Karimpour, J., & Isazadeh, A. (2019). Bisimulation for Secure Information Flow Analysis of Multi-Threaded Programs. Mathematical and Computational Applications, 24(2), 64. https://doi.org/10.3390/mca24020064