Fault Tree Analysis for Robust Design
Abstract
:1. Introduction
1.1. Design Optimization Background
1.2. Fault Tree Analysis (FTA) Background
1.3. Purpose and Outline
2. Materials and Methods
2.1. Parallel Circuit Configuration: A Demonstrative Example
2.2. A Bolted Plate Design Problem and Deterministic Design Optimization
2.3. Robust Design and Reliability Index-Based Design Optimization
2.4. Robust Design with System Failures Built by FTA
2.4.1. Case 1: System Reliability with “and” Gate
2.4.2. Case 2: System Reliability with “or” Gate
2.4.3. Case 3: System Reliability with “Inhibit” Gate
2.5. Post-Optimality Design Sensitivity Analysis
3. Numerical Results
3.1. Robust Design Optimization
- Deterministic Design Optimization: Equations (2)–(4).
- Robust Design with Reliability-Indices: Equations (11)–(13).
- Robust Design with “and” Gate: Equations (15)–(17).
- Robust Design with “or” Gate: Equations (22)–(24).
- Robust Design with “Inhibit” Gate: Equations (28)–(30).
3.2. Post-Optimality Sensitivity Analysis
3.3. Design Evolution by Increasing System Reliability
4. Discussion
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
Appendix A
References
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Symbol | Name | Equation |
---|---|---|
AND | ||
OR | ||
INHIBIT |
Method | |||||
---|---|---|---|---|---|
RD | MC | ||||
Deterministic | 64.8332 | 319.6463 | - | - | - |
Robust Design | 66.0437 | 332.5874 | (13.7859, 0.1298) | 0.9505 | 0.9483 |
“and” Gate | 66.0437 | 332.5874 | (13.7859, 0.1298) | 0.9505 | 0.9483 |
“or” Gate | 65.3925 | 331.285 | (13.8994, 0.1317) | 0.7776 | 0.7760 |
“Inhibit” Gate | 66.2687 | 333.0374 | (13.7470, 0.1291) | 0.9505 | 0.9468 |
Methods | Lagrange Multiplier | Post Optimality SA, | |||
---|---|---|---|---|---|
95.053% to 95.994% | , 14 to 13.9 | 95.053% to 95.994% | , 14 to 13.9 | ||
Deterministic | 11.2439 | - | 1.1244 | - | 1.1316 |
Robust Design | 1.4593 | 0.1459 | 1.1245 | 0.1458 | 1.2018 |
“and” Gate | 14.2637 | 0.1343 | 1.1251 | 0.1458 | 1.1313 |
“or” Gate | 11.1726 | 0.1050 | 1.1244 | 0.114 | 1.1317 |
“Inhibit” Gate | 12.7206 | 0.1197 | 1.1246 | 0.1303 | 1.1317 |
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DeGroff, J.; Hou, G.J.-W. Fault Tree Analysis for Robust Design. Designs 2025, 9, 19. https://doi.org/10.3390/designs9010019
DeGroff J, Hou GJ-W. Fault Tree Analysis for Robust Design. Designs. 2025; 9(1):19. https://doi.org/10.3390/designs9010019
Chicago/Turabian StyleDeGroff, Jonathan, and Gene Jean-Win Hou. 2025. "Fault Tree Analysis for Robust Design" Designs 9, no. 1: 19. https://doi.org/10.3390/designs9010019
APA StyleDeGroff, J., & Hou, G. J.-W. (2025). Fault Tree Analysis for Robust Design. Designs, 9(1), 19. https://doi.org/10.3390/designs9010019