Van der Waals Heterostructure Based Field Effect Transistor Application

Abstract

Van der Waals heterostructure is formed by two-dimensional materials, which applications have become hot topics and received intensive exploration for fabricating without lattice mismatch. With the sustained decrease in dimensions of field effect transistors, van der Waals heterostructure plays an important role in improving the performance of devices because of its prominent electronic and optoelectronic behavior. In this review, we discuss the process of assembling van der Waals heterostructures and thoroughly illustrate the applications based on van der Waals heterostructures. We also present recent innovation in field effect transistors and van der Waals stacks, and offer an outlook of the development in improving the performance of devices based on van der Waals heterostructures.

1. Introduction

In the past few decades, graphene, which exhibits extraordinary electronic and optoelectronic properties in exploring low-dimensional materials, has become the most advanced research in the field of two-dimensional layered material (2DLM) science, solid-state physics and engineering [1,2,3]. Because graphene originally has excellent parameters, such as mechanical stiffness, strength and elasticity, very high electrical and thermal conductivity, graphene-based transistor preforms better than conventional Si-based transistors [1] in fabricating high-frequency transistors with the possible cut-off frequency f_T = 1THz at a channel length of about 100 nm [4] and photodetectors with a wide spectral from ultraviolet to infrared [1]. Therefore, the discovery of graphene creates a new generation of electronic devices with atomically thin geometry and unprecedented combination of speed and flexibility. Except for the advantages and merits of graphene-based transistor mentioned above, there are some shortcomings, such as the unique zero bandgap, hindering the graphene’s application in electronic industry [3]. To overcome the defect brought by graphene device, this extensive library of 2DLMs, such as graphene, phosphorene, hexagonal boron nitride and transition metal dichalcogenide mentioned in this article with selected properties opens up the possibility of heterogeneous integration at the atomic scale, creating novel hybrid structures that display totally new physics and enable unique functionality [5]. Because 2DLMs have various bandgap, the different material shows different property. For example, black phosphorus shows the characteristic of conductor; molybdenum disulfide (MoS₂) and tungsten selenide (WSe₂) are semiconductors; and boron nitride (BN) performs as insulator. 2DLMs with various properties make it possible to form special combination of heterogeneous integration at atom scale, such as van der Waals heterostructures (vdWHs).

In general, heterostructures formed by 2DLM monolayers are assembled by covalent bond force within layers and stacked together by van der Waals force between layers. Thus, there is no free dangling bond between 2DLM layers. In contrast to typical nanostructures persecuted by dangling bond and trap state on the surfaces [6], monolayer are free of these disadvantages (Figure 1a,b) and exhibit extraordinary electronic and optoelectronic properties. Additionally, without free dangling bonds, the interface between neighbor 2DLM layers are assembled by van der Waals forces, which is much weaker than chemical bond force. Therefore, the van der Waals heterostructure can be easily isolated by exfoliation with the help of taps [7]. Although some highly disparate materials have a great lattice mismatch in creating heterostructure, those can be assembled together by van der Waals force. This allows diverse 2DLMs to construct various van der Waals heterostructures (vdWHs) with completely novel properties and functions.

The early study in vdWHs focus on the combination of 2DLMs with 0D (for example, plasmonic nanoparticles and quantum dots) and 1D (for example, nanowires and nanoribbons) nanostructures [9,10,11,12]. These novel 0D–2D (Figure 1f) and 1D–2D (Figure 1g) vdWHs structures have fabricated many highly performed devices, such as photodetectors with highly optical response [10] and transistors with high speed and flexibility [12]. In recent years, most efforts have been taken to form 2D–2D integration vdWHs by vertically stacking various 2DLMs; for example, Dean fabricated a graphene–BN heterostructure transistor which Hall mobility reached ~25,000 cm²·V⁻¹·s⁻¹ at high density [13], and Withers stacked metallic graphene, insulating hexagonal boron nitride and various semiconducting monolayers into complex but carefully designed sequences, which exhibited an extrinsic quantum efficiency of nearly 10% and the emission can be tuned over a wide range of frequencies by appropriately choosing and combining 2D semiconductors [14]. 2D–2D vdWHs with diverse 2DLMs make it possible to accurately control and modulate the transport of charge carriers, excitons and photons within the atomic surface, and greatly promote the new generation of unique devices. Apart from 2D–2D vdWHs, 2DLMs can also be integrated with 3D bulk materials to form 2D–3D structures [8,15] (Figure 1f–h), which attract some interest. Hot electron transistors based on 2D–3D heterojunctions have been reported [16]. Gate tunable p-n junctions based on 2D–3D heterojunctions have been reported [17,18]. Heterojunction formed with MoS₂ and p type Ge can fabricate high performance tunneling field transistor [18].

Recently, most vdWHs are formed by mechanically stacking different monolayers together. Although this method allows great flexibility, it is slow and inconvenient. Thus, some simple and high-quality techniques are being developed, for example, large-area 2DLMs grown by chemical vapor deposition (CVD) and direct growth of heterostructure by CVD or physical epitaxy, which improves the growth quality of monolayers and the properties of heterostructure exhibited [19,20,21].

In this review, we mainly concentrate on the integration, properties, application and technology of vdWHs. First, we give a brief introduction of typical materials, which got highly unprecedented attention in the field of materials science and solid-state physics in the past few years, and discuss the electronical properties about them. Then, we focus on the applications of field effect transistors based on vdWHs, including elevating mobility, decreasing the contract resistance and conventional transistors like tunneling field effect transistor. Except for traditional FETs, we investigated some late-model structure, namely the vertical thin film transistor. Finally, we analyze the process of mechanically and chemically stacking van der Waals heterostructures. Meanwhile, we discuss the process of fabricating the field effect transistors (FETs) by van der Waals stacking methods.

2. Two Dimensional Materials

Two-dimensional materials, which constitute van der Waals heterostructures (vdWHs), have been explored to exhibit entirely different characteristics (Figure 2a), including conductors, semimetals, semiconductors, and insulators. Large group of two-dimensional materials provide various band gap and different electronic and optical performance, which offers the theoretical possibility of different device application requirement. With different 2D materials to form heterostructure, not only novel properties can be observed but also highly reliable nano-device can be achieved as well.

2.1. Graphene

With a honeycomb lattice structure assembled by strong covalent bond force, crystal structure shown in Figure 1d, graphene only has a single atomic carbon layer, which can be manufactured via mechanically exfoliating from bulk graphite. Due to bulk graphite has weak interlayer connection formed by van der Waals force, the large-area monolayer graphene can be easily and successfully exfoliated from bulk material with the help of a scotch tape. Owing to the unique lattice structure and atom combination, graphene has zero band gap which means charge carriers move in a ultrahigh speed about 25,000 cm²·V⁻¹·s⁻¹ at room temperature [24]. In other words, with high conductivity in 2DLMs family, graphene behaves like metal, which is the significant component of forming vdWHs. Transistors with graphene electrodes will have a lower contact resistance compared to transistors without graphene electrodes [25]. In flash memory devices, graphene also acts as charge trap layers [26]. Due to the single-atom thickness and specific density of state (DOS), it exhibits partial optical and electrostatic transparency under tunable work function. For possessing this characteristic, graphene serves as contact material integrated with other two-dimensional semiconductors in vdHW transistors, which achieves an appropriate contact resistance and admirable electrical performance [27].

Bilayer graphene, which is constituted of two atomic carbon-layers stacked by van der Waals interaction under specific direction, does not exhibit the same properties as monolayer graphene. That is because the interaction between two neighboring layers provides extra van der Waals electric field, which inducts bilayer’s bandgap [28] and forms four pseudospin flavors [29]. Although bilayer graphene has a band gap up to 250 mV under gate controlling, it is still smaller than other 2DLM like transition metal dichalcogenide, and even bulk Si (the band gap is about 1.2 eV). Even though monolayer graphene has zero band gap, it can be used in other ways such as graphene electrode in transistor, charge trap layer in flash memory and metal–graphene interfaces which can provide photo-generated carriers in photodetectors [30,31]. Moreover, bilayer graphene transistors also have a degradation of the carrier mobility compared with monolayer graphene [2].

2.2. Transition Metal Dichalcogenide

Transition metal dichalcogenide (TMDC) is the group of two-dimensional materials with chemical form MX₂, where M stands for transition metal (molybdenum and tungsten) and X represents for the chalcogenide (sulfur, selenium or tellurium). The arrangement of atomic layered TMDC is X-M-X form. The crystal structure is shown in Figure 1f. Considering the same reason that adjacent layers of TMDC are weakly held together by van der Waals force, monolayers of TMDC can also be directly split from bulk crystals (regardless of artificiality or natural mineral) by scotch tape, called mechanical exfoliation, and it can also be fabricated by chemical vapor deposition (CVD) processes [32,33]. From bulk structure to two-dimensional layered structure, the most frequently studied TMDCs, such as MoS₂, MoSe₂, WS₂ and WSe₂, show various band gaps (Figure 2b) and tunable electronic properties with its volume changing from bulk material to monolayer [16]. At room temperature, as the thickness of TMDC decreases from bulk to monolayer, its band gap ranges from 1 eV to 2 eV and carrier mobility reaches over 100 cm²·V⁻¹·s⁻¹. Owing to the varied bandgap resulting in tunable electrical characteristics, there are some distinctive properties observed in TMDC, for example, valley Hall effect [34], valley polarization [35], superconductivity [36] and photoelectric characteristic [37,38]. TMDC’s lack of dangling bands is another reason that makes it attractive for use in FET channel material. This means the lattice mismatching is out of consideration during the formation of TMDC–TMDC van der Waals interconnection.

2.3. Phosphorene

Phosphorene is a monolayer material constituted of phosphorus, with a vertically interlaced hexagonal lattice that looks like armchairs. Phosphorene’s bandgap varies from 0.33 eV to 1.5 eV depending on the number of layers stacked [39]. Notably, an individual property is observed in few layers of phosphorene, i.e., anisotropic transportation in different phosphorene’s crystal orientations [40]. Specifically, transporting in the armchair direction (x direction) is much more efficient than in zigzag direction (Figure 1c). In addition, a p-type semiconductor characteristic emerges in phosphorene. When the hole mobility exceeds 1000 cm²·V⁻¹·s⁻¹ in certain direction [41], the phosphorene becomes the significant 2D material for electronic device. Later report shows that the drain current of FETs based on phosphorene can be modulated to 10⁵, which means the I_on/I_off ratio reaches 10⁵ [42]. The tunable bandgap of phosphorene make it possible to react with different spectral regime from visible to infrared, which can be applied in fabricating multispectral photodetector [43].

The main challenge for phosphorene’s extensive application is the environmental stability, which means it can be easily oxidized [44]. To prevent the surface oxidization which leads to the decrease of device performance, some solutions have been adopted, for example, using h-BN [45], atomic layer of Al₂O₃ [46,47] and hydrophobic fluoropolymer [48] as encapsulating materials during process of van der Waals stacking.

2.4. Hexagonal Boron Nitride

Hexagonal boron nitride (h-BN), also called white graphite, has the same lattice structure as graphite. (Figure 1e) For boron and nitrogen are combined together by the strong covalent sp² hybridized chemical bond, h-BN exists as insulator with a large bandgap of 6 eV [49]. Mechanical exfoliation can provide an atomically smooth surface without dangling bond and carrier traps, so a few layers of h-BN can be used as ultra-flat insulating substrates, the gate dielectrics [50] and ideal encapsulate material [24] in heterostructure transistors [13]. Besides, ultrathin h-BN can be served as great tunneling barrier material in tunneling devices [51,52].

2.5. Other Various 2D Materials for vdWHs

In the past few years, novel 2D TMDCs draw a lot of concentration on creating new types of devices; meanwhile, traditional 2D materials such as MoS₂ and WSe₂ have been considered once more. In virtue of doping technology, high-k amorphous titanium suboxide (ATO) is used as an n-type charge transfer dopant on the monolayer MoS₂, which decreases the contact resistance to 180 Ω·µm [53]. Utilizing AlO_x, another method of n-type doping in MoS₂ is demonstrated, which can also reduce the contact resistance to 480 Ω·µm [54]. After confirming operational parameters of chemical vapor deposition, ultrathin MoS_2(1−x)Se_2x alloy nano-flakes with atomic or few-layer thickness can be obtained and it have high activity and durability during the hydrogen evolution reaction [55]. These various 2D materials show variable bandgaps, tunable optical and electronic properties [56,57].

3. Techniques

Two-dimensional materials can be assembled or grown directly into heterostructures, where the monolayers are held together by van der Waals forces. Although variety of 2D materials have been found, the assembly techniques currently used allow only certain types to build up the heterojunction. At the same time, the alternative technique, called sequential growth of monolayers, potentially do well in large scale production. Actually, the growth method has some limitations, such as slow growth and hard to control, and is still in early stages. Nevertheless, a great number of experiments with van der Waals heterostructure indicate that 2D materials are versatile and practical for further applications [58].

3.1. Assembly

Direct mechanical assembly is the most commonly used techniques of assembling heterostructures at present. This techniques was been put forward in 2010 by Dean et al., who demonstrated a very high level of performance provided by graphene and h-BN [13].

In early works, the technique is only used in preparing a flake of 2D material on a sacrificial membrane, such as PDMS, aligning and placing it on the substrate, and then remove or dissolve the membrane (Figure 3A–G). Then, the progress is repeated to deposit the other 2D material on the top of the former layer. Because the materials have close contact with the sacrificial layer, which is dissolved finally, the interface between TMDC and sacrificial layer will be contaminated. However, annealing can remove this contamination and achieve high interface quality, so the mobility of graphene device can reach 10⁶ cm²·V⁻¹·s⁻¹¹ [13].

The other substantially cleaner method has the same principle that van der Waals interaction exist between layers. After sticking the first layer onto membrane, the second layer is directly stuck on the first layer, instead of dissolving the membrane (Figure 3G–O). Then, the process is repeated several times to get expected multilayer. This method leads to cleaner interface over large areas, and higher electron mobility.

3.2. Growth Methods

Although the assembly methods can stack the layers and achieve a clean interface, it still has some disadvantages, for example, the stacking position cannot be accurately controlled, which affects the device properties [22]. The direct growth of vertical layered heterostructures via chemical vapor deposition (CVD) is much more promising in terms of being controllable and scalable.

The direct growth of heterostructures can be divided into two parts: (1) sequential CVD growth of 2D materials layered; and (2) molecular beam epitaxy (MBE). The detailed information is presented in the following.

3.2.1. CVD

For the CVD system of MoS₂ growth, as depicted in Figure 4, two separated furnaces are used to precisely control temperature applied on both precursors and substrate. Sulfur powder and the substrate are in the same pipe while different furnaces, where the interaction temperature can be independently controlled. Twenty milligrams of MoO₃ powder, which temperature is dominated by furnace 2, is loaded between sulfur powder and the substrate and has an independent mini-pipe (diameter 1 cm). This is to prevent any cross-contamination and reaction between sulfur and MoO₃, resulting in the decrease amount of MoO₃ and unstable precursor supply in the vapor phase. Typical growth temperatures used for sulfur, MoO₃, and the substrate are ~180 °C, ~300 °C, and ~800 °C, respectively. To ensure the sufficient supply of sulfur vapor in the system, it is preheated before increasing the temperature of MoO₃.

This simple but scalable CVD growth approach can realize the direct fabrication of large-area MoS₂/h-BN heterostructures with cleaner interface and better contact, compared with mechanical transfer method or assembly methods [59].

3.2.2. MBE

As one of the most commonly used growth methods of heterostructures, CVD has successfully accomplished several two-dimensional layered materials [60]. Although it is almost theoretically perfect, the reaction condition of CVD is hard to control at present and the results reported publicly can only form a few well-defined islands over the entire wafer. Considering the defects, MBE is an alternative approach for CVD in some ways [61].

As the name suggests, MBE is a kind of physical deposition method that takes place in ultrahigh vacuum. Figure 5 shows a typical MBE system. The required components are heated into vapor and sprayed on the substrate through a small hole. At the same time, a controlling molecule beam is used to scan the substrate line by line, and the molecules or atoms are arranged layer by layer in lattice structure. The ultra-high vacuum(UHV) environment minimize the contamination of the interface between substrate and growing flake. Because there are few particles in UHV environment, the ionized atoms and molecules traveled in nearly collision-free path until hitting the substrate or the chilled oven walls, where atoms condense immediately, and thus are effectively cleaned up from the reacting system without extra contamination. Because the components are sprayed onto substrate through a small hole, it can be turned off almost instantly and changed into another reactant whenever necessary. Most importantly, MBE growth can be simplistically described as “spray painting” the substrate crystal with layers of atoms, changing the composition or impurity in each layer until a desired structure is obtained [62].

Compared with CVD, MBE can potentially grow products overspread the whole wafer, precisely control the rate of interaction by means of regulating the rate of spraying and easily change the reactant as requirement. In this sense, MBE is almost the ideal method of vdWHs fabrication since the composition can be precisely controlled layer by layer.

4. FETs Based on Heterostructures Applications

Various 2D materials provide diverse electronic properties from conductors to insulators which benefits new devices creation. Van der Waals heterostructures exhibit ultrathin thickness and special properties that give a chance to build transistors at nanoscale size compared to bulk materials. Thus, novel field effect transistors based on van der Waals heterostructures have developed.

4.1. Decrease the Contact Resistance

Two-dimensional semiconductors (2DSCs), especially TMDCs, have sparked immense interest in the electronic devices since the MoS₂-based transistor was first reported [64]. Source and drain are often made of Metal-TMD directly contact, which induce a high contact resistance Rc. Even the contact resistance is larger than Si based transistors. The excessive contact resistance Rc on the source and drain interface is a great challenge for 2DSCs devices.

The high contact resistance, induced by a high Schottky barrier [65], prevent the charge carriers moving through the metal-semiconductor contacts. While the typical 2DLMs contact resistance currently achieved is 100 times higher than Si-based electronics (<20 Ω·μm) [66], there is still much work to do to decrease the actual contact resistance (Figure 6a). Some strategies have been used to reduce the contact resistance with the help of graphene/metal heterostructures. Schematics are shown in Figure 6d–f.

In silicon-based transistor, doping is conventionally used in traditional process of decreasing contact resistance at the source and drain interface, which is not reliable in TMDC-based transistor. That is because a highly doped silicon-based transistor can provide more carriers to fill valence band [65]. However, injecting other elements into TMDC seriously damages the covalent bonds between the atoms and breaks TMDC’s unique lattice structure, thus a great deal of defects are generated into layers resulting in Fermi-level pinning, which causes undesired contact resistance [68,69]. Besides TMDC, graphene is another 2DLM drawing extensive concern. The greatest contribution of graphene is forming van der Waals stacks with metal and 2DLM, which commendably decreases the contact resistance due to its special band structure. Because graphene is single-element 2DLM, it can be doped similar to silicon. Compared with intrinsic graphene, the highly-doped graphene decreases the height of Schottky barrier formed by the connection of graphene and metal, which means the contact resistance is greatly reduced [70]. A typical TMDC-based transistor, which uses monolayer graphene as metal electrodes, 2DLMs such as tungsten diselenide (WSe₂) as semiconductor channel, and hexagonal boron nitride (h-BN) as gate dielectric, exhibits very high performance, such as high current on/off ratio, remarkable temperature stability, low contact resistance and low subthreshold slop [71]. Even though the Schottky barriers is still high (0.22 eV) at the graphene–WSe₂ contact, the on-state current is dominated by tunneling through the barriers which makes the barriers almost transparent to the charge carriers. After using 3 nm h-BN as gate dielectric and 1.5 nm WSe₂ flake as channel material, the tunneling distance is only 1.6 nm [72]. There are three types of interface of graphene–2DSCs contact: coplanar contacts (Figure 6d), staggered contacts (Figure 6e) and hybrid contacts (Figure 6f).

The coplanar structure is that the TMD channel materials and source/drain electrodes are on the same side of graphene. With the bottom graphene contact for 2DSCs transistors, nearly perfect work function matching lead to a barrier-free contact, which can significantly decrease Rc. MoS₂ and WSe₂ transistors using this strategy have been demonstrated [25,70,73,74]. Staggered contacts mean that TMD channel and source/drain electrodes are on different sides of graphene. With this strategy, transistors can be less susceptible to lithographic contamination, because the polymer residue did not touch TMD channel directly. Otherwise the residue will affect the charge transport at the interface. With this method, high performance MoS₂ transistors [75,76,77,78] and air stable black phosphorus transistors [45] have been reported. Metal–graphene hybrid structure as a unique contact to reach minimized Rc (300 Ω·μm) compared to metal–TMD structure. With graphene inserted as the interlayer buffer, the carrier injection was enhanced at metal–graphene–TMD channel interfaces. For example, nickel–etched–graphene electrodes have achieved a relatively low resistance [79]; Ti–graphene–MoS₂ stacks can ruduce Rc from 12.1 ± 1.2 Ω·mm to 3.7 ± 0.3 Ω·mm to some degree compared with stacking Ti onto MoS₂ directly [80].

When integrating two-dimensional transition metal dichalcogenides with metal, the valence band shows unusual Fermi level pinning. Compared with chemical doping, which will destroy the covalent bond of TMDs within layers, the stacking of graphene can create a undamaged van der Waals contact and a ultraclean interface, which prevents Fermi level pinning [25,75]. There are some other reports demonstrate a stacking structure formed by MoS₂ and graphene to reduce the connect resistance [73,77,81]. In this structure, graphene and metal are connected together to form electrodes and molybdenum disulfide (MoS₂) is used as channel. The tunability of doping graphene’s work function can significantly improve the ohmic contact to MoS₂ [77].

Besides graphene, other 2DLMs such as MoS₂ can also be doped with element to improve the mobility of charge carriers which leads to low contact resistance, for example, physisorbing chloride molecule into WS₂ or MoS₂ [82]. With the method of physisorbed molecules, contact resistance can be obviously decreased [83]. Other efforts of contacting electrode metal materials with TMDs create the low Schottky barrier. For example, the connection between molybdenum (Mo) and MoS₂ forms perfect interface, leading to ultralow Schottky barrier about 0.1 eV [84]. Other methods based on van der Waals heterostructure to decrease Rc have include phase-engineering. With the organolithium chemical method, MoS₂ changes from 1T phase to 2H phase. 2H phase MoS₂ behaves as electronic channel, as shown in Figure 6b. This 1T–2H–1T structure can receive relatively low Rc [67] (Figure 6c). To create stable homojunction contact of MoTe₂, some reports use laser to achieve two phase interconversion. Stacking semiconducting hexagonal (2H) and metallic monoclinic (1T) MoTe₂ together can fabricate an ohmic heterophase homojunction, which is necessary in lowing contact resistance [67]. Phase engineering, therefore, provide a way of creating lateral heterostructures with low resistance, but additional work is needed to achieve values comparable to state-of-art materials and close to the quantum limit.

4.2. Tunneling Field Effect Transistor and Barrister

The principle of tunneling field effect transistors (TFETs) is band-to-band tunneling [85]. The barriers induce by van der Waals gap narrow because the width of van der Waals gap is below 1 nm, which will lead to charge carriers tunneling [86]. For width of barriers narrowing at the contact interface, the tunneling current between source and drain increases rapidly in silicon-based transistor. However, vertical tunneling transistor based on vdWHs is different from conventional TEFTs. In vertical structure, two separate monolayers of graphene serve as electrodes, and ultrathin dielectric material are stuck between them. Based on gate-voltage tunability of the DOS in graphene, the height of Schottky barrier reduces and realizes the charge carriers’ transportation.

Transistors based on that principle use very thin BN (1.4 nm) and MoS₂ as vertical transport barrier, making devices have the switching ratio of ~10,000 at room temperature [87]. Further study of this type of heterostructure is the resonant tunneling and gate voltage-tunable negative differential conductance [88]. Other studies have put forward how to achieve the resonant tunneling with the help of crystallographic orientation alignment of the graphene-BN-graphene heterostructure [89,90].

In addition of graphene, two dimensional TMDs have sharp band edges and ultra-narrow channel length, which has been the suitable candidates for TFETs. By correctly choosing two 2D layers of semiconductors to make up a suitable heterojunction (one layer is n-type and the other layer is p-type), it can achieve both large tunneling current and low subthreshold swing (SS). Subthreshold swing (SS) shows the current transformation with the change of voltage, when the device works in subthreshold state. With the proper heterojunction band offsets between the two 2D semiconductor layers (Figure 7a,b), the tunneling current will be significantly increased because of the band alignments. TFETs with SnSe₂/WSe₂ van der Waals heterostructure (Figure 7c) have achieved the SS of 80 mV/dec at room temperature and I_ON/I_OFF ratio exceeding 10⁶ [91] (Figure 7d). In addition, dual-gated MoS₂/WSe₂ van der Waals heterostructures were demonstrated and carrier concentration of MoS₂ and WSe₂ can be independently controlled by up and down symmetric gates, which achieved a high efficiency of 80% due to the weak electrostatic barrier through atomic layers [92].

4.3. Van der Waals Heterostructure Based Vertical Transistors (VFETs)

With ultrathin structure and suitable band structure, 2DLMs can create totally new devices such as vertical transistors. Compared with conventional planar field effect transistors, which consist of a source and a drain plate electrode with a conducting channel located between them, vertical transistors often use graphene and metal as source and drain electrodes, respectively. In planar transistors (Figure 8a), the gate electrical field (E) controls the channel carriers to influx. Thus, the channel current density (J) is always perpendicular to the gate electrical field (E) (J⊥E). The channel length is decided by the area of 2DSCs. In other word, the lithographic accuracy which decides the distance of source and drain would influence the channel length. In particular, the tunable work function and partial electrostatic transparency make graphene become the appropriate candidate of interconnecting with semiconductor to fabricate vertical transistors, in which graphene acts as the active contact. In this fundamentally different geometry, as shown in Figure 8b, the channel carriers transport direction is parallel to the gate electrical field (J∥E). The channel length is decided by the thickness of 2DSCs which can be prominently shorter than the planar transistors. With effectively modulating the work function of graphene by introducing the gate voltage, the Schottky barrier between graphene and semiconductor changed and result in large current injection, which brings a large on/off ratio that cannot be achieved in planar transistors.

Different kinds of transistors based on vertical vdWHs have been reported according to its special device structure. N-channel vertical FET created by sandwiching multilayered MoS₂ between graphene and metal panel (Figure 8c), has the on/off ratio >10³ at room temperature [93]. Due to van der Waals interface between MoS₂ and graphene, the Schottky barrier restrains current injection. Introducing an external electric field can strongly modulate the height of Schottky barrier owing to the small density of states of graphene [94]. The band structure of graphene/MoS₂/metal heterostructure is shown in Figure 8d. The source/drain voltage (V_B) drives current follow vertically into multilayered MoS₂ channel. The carriers transport is dominated by thermionic-emission (TE). The application of V_B changes the Fermi level in graphene due to the capacitive coupling through MoS₂. With the increasing V_B, the Fermi level will reach the Dirac point at some point, as shown in the right panel of Figure 8d [95,96]. Other 2DLMs such as WS₂ possessing the same geometrical structure of MoS₂ VFETs have been reported, achieving extremely large on-state current [97].

As graphene has attracted increasing attention among researchers, other carbon-based materials such as fullerene also draw attention to be assembled with graphene or 2DLMs to create organic vertical field effect transistors (OVFETs). In other words, the work function of fullerene (C₆₀) is closed to graphene. Thus, the graphene/C₆₀/metal VFET with a measured current on/off ratio up to 10⁵ has been reported [98] and the logic inverter based on this structure also has been reported yet [99]. Some types of organic or molecular crystals can act as semiconductor. After stacking on graphene to form 2D–3D heterojunction, which is an excellent vertical channel for VFETs, new opportunities in developing novel OVFETs exist. At the same time, organic transistors such as 2D quasi-freestanding molecular based graphene transistors which had the mobility up to 10 cm²·V⁻¹·s⁻¹ have been achieved [100].

4.4. Photodetector and Diodes Based on van der Waals Heterostructure

Based on fine optical characteristic of two-dimensional TMDCs, photovoltaic applications about van der Waals heterostructure combined with such materials have been explored. The typical application is the photodetectors made of graphene act as channel material and MoS₂ act as light sensitive material [101]. Under the combination of two kinds of 2D materials which have different tunable work functions, photoexcited electrons and holes can be accumulated in conductor layers. Shown in Figure 9a, photoexcited pairs have been observed in the heterostructure of MoS₂/WSe₂ [102] and MoSe₂/WSe₂ [103]. Most photovoltaic devices can be created by combining few layers of TMDCs with graphene. Using graphene as electrodes and TMDCs sandwiched between two graphene electrodes, one can create efficient photoexcited carriers inject into graphene electrodes [104,105]. In other words, graphene can form a typical ohmic contacts which will significantly decrease the resistance and serve as a transparent electrode.

If p-type and n-type 2D semiconductors stack together with van der Waals force, then atomic layers of p-n junctions can be acquired. Gate tunable diode based on TMDCs have been abundantly created. Various combinations of 2D semiconductors were used to construct p-n junction for photodetectors (typical p-n structure and band structure shown in Figure 9b) to realize the excellent performance of responsivity and detectivity [106,107,108,109,110,111,112]. Heterostructures such as MoS₂/WSe₂ [107], black phosphorus/MoS₂ [109], and MoS₂/WS₂ [110] p-n junctions are widely used in photodetectors. GaTe/MoS₂ heterostructure received a high photovoltaic performance whose photoresponsivity can reach 21.83 AW⁻¹ [112].

4.5. Memory

There are many types of memory devices which include dynamic random access memory (DRAM), static random access memory (SRAM), resistive random access memory (RRAM) and flash memory. The memory cells of DRAM and SRAM are based on the one-transistor and one-capacitance (1T1C) structure and six transistors (6T), respectively. The 1T1C DRAM cell is shown in Figure 10a. The capacitance charging and discharging controlled by the transistor on-state and off-state. When the word line voltage reaches the transistor on-state voltage, the current will follow through transistor and charge the capacitance when the bit line voltage is at high potential. This operation is called the programming process. When the bit line voltage is at low potential, the charged capacitance will discharge and the current will follow through the transistor into bit line, which is called erasing process. When the word line voltage controls transistor at the off-state, the charge carriers will be held in capacitance. After setting bit line at half of the high potential, the voltage will rise if the capacitance is charged and will decline if the capacitance is discharged. This is called the reading operation of DRAM. However, DRAM is a typical volatile memory, which means that the storage performance will disappear under the power-down state.

A new concept of constructing memory is based on the domain wall motion which means that crystalline particles with the same polarization direction as the external electric or magnetic field inside the crystal become larger. This process is done by the movement of domain wall. Current driven domain wall motion and electrically controlling the magnetization switching by spin orbit torque have been proposed for information storage. Decreasing the current density to realize the domain wall motion plays an important role in practical applications [114]. Basically, the external magnetic field is necessary to control the current-induced magnetization switching direction by spin orbit torque [115,116]. Later research has reported that the electric field definitively control the current induced ferromagnet switching at room temperature with the polarized ferroelectric substrate [117]. Piezo voltage solely controlling the magnetization switching at room temperature without external magnetic field has been realized, which can largely decrease the energy consumption compared with the electric current switching magnetization [118]. This concept offers an idea to develop ferroelectric random access memory, magnetic random access memory and phase change random access memory.

Another block of memory is flash, a kind of non-volatile memory. Flash memory is based on 2D material stacks established on a semiconductor–insulator–metal (SIM) structure (Figure 10b). MoS₂/BN/Graphene heterostructure for use in flash memory has been widely explored [113,119]. Graphene and MoS₂ were utilized as charge trapping layers and channel layers and h-BN acted as a tunnel barrier, respectively. Under a considerable voltage positive bias, the tunneling current exponentially increases with the decreasing of BN thickness, which will lead to the increasing charge injection into the trap layer. Thus, the thickness of insulator becomes especially important in SIM structure. The critical thickness of tunneling barrier is 7 nm. Tunneling current cannot be formed in the thick layers (>10 nm), while leakage current will exist in the thinner layers (3.5 nm), which will cause charging process failure [113]. When gate voltage becomes negative in releasing process, charge carriers trapped in the graphene layer will be transferred into MoS₂. Thus, the charge retention and gate hysteresis that contains a memory window can be observed (Figure 10c). Retention time of trapping and releasing current shows the endurance of charge trapping flash device (Figure 10d). Detailed band is structure shown in Figure 11a with the charging and releasing process.

Nonvolatile floating gate flash memory based on black phosphorus/BN/MoS₂ stacks have been reported, where MoS₂ behaves as charge trapping layer and black phosphorus acts as channel [120]. Charge trap memory with high k dielectric materials can greatly improve the storage performance. Few-layer MoS₂ channel and three-dimensional Al₂O₃/HfO₂/Al₂O₃ stack together to form a charge trap flash memory device, exhibiting an unprecedented gate window of 20 V and a program/erase current ratio of 10⁴ [121]. Band diagram of program/erase state of device under different top gate bias (V_tg) is shown in Figure 11d. Positive V_tg carry out the programming process. Electrons tunneling from MoS₂ channel are accumulated in HfO₂ charge-trap layer. Negative V_tg carry out the erasing process. Holes tunnel from MoS₂ channel to HfO₂ charge-trap layer. The charge-trap layer holds different charges, causing the threshold shifting. Thus, memory window exists. Besides MoS₂ channel based charge-trap memory, Ambipolar WSe₂ channel based charge-trap memory devices have also been reported [122]. Subsequently, black phosphorus based charge-trap memory devices with a Al₂O₃/HfO₂/Al₂O₃ charge trap stack have been demonstrated, where the long data retention with only 30% charge loss after 10 years were obtained [123]. Beside floating gate memory, novel structure based on vertically stacked 2D materials (WSe₂/h-BN/graphene) has the gate metal stack directly on the graphene, thus we call it semi-floating gate (SFG) flash memory [124]. The structure is shown in Figure 11b,c. When a positive voltage is applied on Si, electrons are accumulated in the WSe₂. These electrons tunnel through BN and begin to be accumulated in graphene due to the different potential between WSe₂ and graphene which is considered as programing process. When the positive bias is removed, electrons are still trapped in graphene due to the potential barriers of h-BN. When applying a small negative voltage bias on Si, the electrons tunnel through BN and are injected into WSe₂ channel as an erasing process. Similar behaviors can be observed for holes when a negative voltage is applied on Si. When treated with plasmas, multilayer MoS₂ transistors can serve as nonvolatile, highly durable flash memory with multibit data storage capability. This novel multibit flash memory is desirable for improving data storage density in order to reach manufacturing process [125].

Memory have made significant progress due to the multiduty van der Waals heterostructures. New type of memory devices structure began to spring up. However, effort still needs to be made to improve the memory performance such as stability, reliability and time of memory operation. 2D van der Waals heterostructures offer a new route of building novel memory.

5. Perspective

The inherent absolute advantages of 2D materials—exhibiting free of dangling bond and gate tunable electronic properties—make them promising candidates for van der Waals stacks, which are widely used in novel device design. However, the burgeoning van der Waals heterostructures applied to electronic devices remain in their infancy. Technical improvement still needs to be explored in the following effort.

Conventional laboratory-stage process of assembling van der Waals stack is mechanical exfoliation and transfer methods. The shape of exfoliated 2D materials is irregular and the size can only reach micron order. It is hard to acquire monolayer materials and most are few layers. Large area 2D materials are still needed in some cases during transfer process. Although with the utilize of chemical vapor deposition, large-scale synthesizing 2D materials and van der Waals heterostructures is developed, it still cannot be applied in integrated technique and lacks controllability of the relative orientation, size, shape and interlayer spacing with increasing vdWH layers. Furthermore, the electrical performance of chemically synthesized 2DLMs is inferior to their exfoliated counterpart. Thus, there is still much room to improve the process of assembling van der Waals heterostructure.

FETs based on van der Waals heterostructures have largely focused on attaining high performance with certain parameter to measure. However, parameters such as low SS at extensive range of gate voltage biases, which will lead to large on/off ratios with low input voltage biases, have become important criteria for measuring the performance of the devices. Besides, contact resistance is still a big deal for limiting the improvement of devices. There is still plenty of room to lower the contact resistance, as it is still above theoretical minimum, even larger than Si based transistors. The contact resistance must be lower by at least an order of magnitude to <100 Ω·μm. In 2D TMDCs, based on phase engineering, changing semiconductor to metal phases is a promising route of creating an ohmic contact which can greatly lower the contact resistance. In addition, the majority of TMDCs are unipolar, n-type or p-type. Controllable and stable doping process is still a major challenge to overcome the achievement of bipolar—both n-type and p-type—semiconductors or van der Waals stack of homogenous material, which will enable the next generation of high speed and low power devices. Direct growth of homogenous 2D semiconductor with stable doping process to form different types of heterostructures and phase engineering to decrease contact resistance are topics for future research. Scalable fabrication of van der Waals stacks also need to be explored. Creating new structure of semiconductor devices based on van der Waals heterostructures still has a long way to go.