3.4. Investigating the Effects of Ferrite
Using the ferrite layer under the NFC conductor is another method to miniaturize the structure. Ferrites have high permeability and as a result, increase the inductance of the NFC loop. In order to investigate the effects of ferrite, a 1 µm thick ferrite layer between the NFC loop and the Si-Ni layer is inserted for a one-layer NFC loop that covers the whole area under the loop and extends to the silicon edges. The ferrite layer is chosen from the HFSS library with electromagnetic properties of (relative permeability) µr = 1000 and (conductivity) σ = 0.01S/m. As can be seen from
Figure 5, the magnetic fields are more concentrated towards the ferrite layer as a result of high magnetic permeability.
The input impedance of the NFC loop in presence of the ferrite layer shows the increase of the inductance although the resistance increases slightly due to ferrite conductivity.
Table 3 shows a comparison between cases with and without the ferrite layer. It is found that using this ferrite layer, the inductance has been increased by 1.54 times while the increase in resistance is marginal. Hence the NFC antenna in presence of the ferrite has been significantly miniaturized.
It must be mentioned that ferrite layers are very sensitive to the fabrication process and hence will show different electrical properties [
12,
13]. In order to investigate the effect of the ferrite conductivity, ferrites of different conductivities and its effects on losses are compared here. The loss mechanism in the current structure is a result of eddy currents induced in the silicon substrate, ferrite ohmic loss as well as the resistivity of the loop itself. It has been found, as shown in
Table 3, that the effect of ferrite loss seems trivial compared to other loss sources such as conductors’ resistance.
As expected, increasing the thickness of the ferrite will enhance the inductance further with a slight increase in resistivity.
3.6. Coupling of Antennas
A different viewpoint for performance assessment is the transferred power efficiency between the antennas in the study and a reader antenna. To assess the potential for coupling the chip antenna to a standard-sized reader antenna, several assumptions have been made. Firstly, since every smartphone is different in its geometry internally, there does not exist a standardized reader antenna. We therefore compared antennas from several smartphones and came up with a reader antenna geometry that resembles the actual antennas as closely as possible. We assumed the size to be about 4 × 4 cm
2, with 5 Planar turns and a ferrite sheet thickness of about 0.5 mm. This coil is then coupled to the various antennas under investigation. Solid metrics for power efficiency are the coupling factor, as well as the total quality factors, which are calculated from the Z-parameters that are related to the port S-parameters. The coupling factor as well as the quality factors are defined as [
14] respectively,
where port 1 is defined at the reader side and port 2 at the chip side and
Zij = Zji for
i ≠ j, as this is a passive, and therefore reciprocal device. It should be noted that
Re(Zii) includes all losses of the coil with port i, including the ohmic conductor losses and the eddy current losses inside the ferrite due to finite conductivity as well as dielectric losses, if applicable.
Im(Zii) on the other hand includes inductive and capacitive contributions of the respective geometry, all at 13.56 MHz.
The maximum achievable efficiency of the transmission, assuming perfect power matching, can then be calculated from these quantities as [
15]
where
The results for the coupling factors and maximum achievable power transmission efficiency are shown in
Table 5.
It shows that the large paper coil provides sufficiently high efficiency. The overall limit is the minimum threshold power of 4 mW that has to be transferred into the NFC chip to operate it, which can be achieved for large distances. However, this result is to be expected since reader and tag coil are of similar dimension. The two-layer chip coil on the other hand would need at least 614 mW of reader power to operate the tag chip. This, of course, infers the best possible power matching. Since the NFC chip also provides an on-chip matching capacitor, which is comparably small due to the chip size, the matching is far away from being perfect. The actual resonance is significantly above the 13.56 MHz. If no external additional matching capacitor can be used, then the fact that the self inductance of the tag chip coil is increased due to the inclusion of a second layer or a ferrite sheet helps the matching to perform better. Simulations with Keysight ADS using standard NFC matching circuitry, pictured in
Figure 8, and the S-parameters from the HFSS simulations, showed improvement in the overall efficiency, but the improvements are still not high enough to directly couple the chip coil with a reader without the need of a booster antenna [
3], and are of course below the optimal limit. As indicated above, the optimal efficiency limit at a coil distance of 5 mm is 0.65% for the dual-layer coil, that was almost reached for optimized matching elements (0.6%). If the on-chip 78 pF capacitor is used for this configuration, the efficiency drops to about 0.12% for the dual-layer chip coil, while the single-layer chip coil and the 1 µm ferrite chip coil will drop to 0.11% and 0.16%, respectively. These results are presented in
Table 6.
As can be seen, the inductance of the dual-layer coil is already high enough (2.86 µH) that the on-chip matching capacitor becomes larger than the optimum value (78 vs. 48 pF) and therefore detunes the resonance in a different direction. This leads to worse performance compared to the single-layer chip coil with 1 µm ferrite, where the on-chip capacitor value comes closest to the optimum value (78 vs. 99.8 pF).
In terms of raw electrical performance, the ferrite coil should therefore be preferred over the double-layer coil if only on-chip matching can be applied. If different matching possibilities are available, then the double-layer coil outperforms the single-layer coil with ferrite by a small margin. From a manufacturing point of view, sputtering ferrite on the chip is more feasible than the addition of a second layer. Therefore, the ferrite approach appears to be more cost effective and less prone to low yield, while being the best performer using on-chip matching, and should be preferred. The easiest and cheapest version is the single-layer coil, but with the lowest power efficiency. In general, Equation (6) can be expressed in terms of electrical circuit parameters and results in
where
ω is the angular frequency,
M is the mutual inductance (
Im(
Zij)/ω) between the reader and the tag coil and
R1 and
R2 are the respective ohmic losses of the coils. Since the maximum achievable power efficiency grows monotonously with
, an optimization of
automatically optimizes also the power efficiency.