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Article

Wrapping Amorphous Indium-Gallium-Zinc-Oxide Transistors with High Current Density

by
Jiaxin Liu
1,
Shan Huang
2,
Zhenyuan Xiao
3,
Ning Li
4,
Jaekyun Kim
3,*,
Jidong Jin
3,* and
Jiawei Zhang
1,*
1
Shandong Technology Center of Nanodevices and Integration, School of Integrated Circuit, Shandong University, Jinan 250100, China
2
Department of Electronic and Computer Engineering, The Hongkong University of Science and Technology, Hongkong, China
3
Department of Photonics and Nanoelectronics, Hanyang University, Ansan 15588, Republic of Korea
4
Department of Electrical and Electronic Engineering, Hanyang University, Ansan 15588, Republic of Korea
*
Authors to whom correspondence should be addressed.
Electron. Mater. 2025, 6(1), 2; https://doi.org/10.3390/electronicmat6010002
Submission received: 30 October 2024 / Revised: 6 January 2025 / Accepted: 21 January 2025 / Published: 23 January 2025
(This article belongs to the Special Issue Metal Oxide Semiconductors for Electronic Applications)
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Abstract

:
Amorphous oxide semiconductor transistors with a high current density output are highly desirable for large-area electronics. In this study, wrapping amorphous indium-gallium-zinc-oxide (a-IGZO) transistors are proposed to enhance the current density output relative to a-IGZO source-gated transistors (SGTs). Device performances are analyzed using technology computer-aided design (TCAD) simulations. The TCAD simulation results reveal that, with an optimized device structure, the current density of the wrapping a-IGZO transistor can reach 7.34 μA/μm, representing an approximate two-fold enhancement compared to that of the a-IGZO SGT. Furthermore, the optimized wrapping a-IGZO transistor exhibits clear flat saturation and pinch-off behavior. The proposed wrapping a-IGZO transistors show significant potential for applications in large-area electronics.

1. Introduction

Amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) have been extensively investigated in recent years due to their high mobility, excellent uniformity, high transparency, and low temperature processability [1,2,3,4,5]. Notably, amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs typically exhibit mobilities of around 10 cm2/Vs, surpassing those of amorphous hydrogenated silicon TFTs [4]. Consequently, the adoption of a-IGZO TFTs has facilitated advancements in large-area electronics [2,6]. The a-IGZO TFTs are particularly well suited for high-resolution, fast-frame-rate, large-area flat-panel displays [3,4,7]. Moreover, a-IGZO TFTs demonstrate immense potential for applications in memory devices, wearable sensors, integrated circuits, and high-speed electronics [8,9,10,11,12,13].
In addition to AOS TFTs, researchers have investigated transistors based on AOS with different device architectures [14,15,16,17]. A notable advancement in this field is the development of a-IGZO based source-gated transistors (SGTs) [17,18,19,20,21]. The concept of the SGT was first introduced by Shannon and Gerstner [22]. SGTs integrate a TFT with a Schottky diode, delivering several performance enhancements over conventional TFTs, such as higher output impedance, reduced saturation voltage, and improved operational stability [18,23,24,25]. As a result, SGTs are well suited for large-area, high-density integrated circuits, as well as pixel driving circuits in display applications [18,26,27,28]. Nevertheless, the limitation of SGTs is their typically lower transconductance compared to TFTs [16]. In SGTs, transconductance is modulated by the source-gate overlap region, whereas in TFTs, it is governed by the channel [27]. TFTs achieve higher transconductance because the gate voltage directly controls the channel current.
In large-area electronics, achieving high current densities is crucial, and large integrated device dimensions require efficient, high-performance components. This is particularly important in organic light-emitting diode (OLED) display pixel driving circuits, where a driving transistor with a higher current density output ensures brighter OLED emission [2]. However, delivering higher current density from SGTs at constant operating voltage without improvements to the properties of the semiconductor material remains a significant challenge. Therefore, it is imperative to develop new device architectures to improve the current density output.
In recent years, substantial advancements have been made in the design of vertical channel transistors, including vertical channel TFTs (V-TFTs) and vertical organic field-effect transistors (VOFETs) [29,30,31,32]. V-TFTs typically utilize inorganic channel materials such as silicon or IGZO [30], whereas VOFETs employ organic semiconductors as channel materials [32]. Both V-TFTs and VOFETs feature a semiconductor channel layer arranged in a vertical configuration, with the source and drain electrodes positioned on different planes [30,32]. This vertical arrangement enables V-TFTs and VOFETs to achieve reduced channel lengths compared to traditional planar TFTs [30,31,32]. The reduction in channel length results in a higher width-to-length ratio for the transistors, facilitating increased current flow and directly contributing to enhanced current density [30,32].
In this study, a novel device called the “wrapping a-IGZO transistor” is proposed, where the a-IGZO layer is wrapped within its structure. This wrapping a-IGZO transistor represents a unique type of V-TFT, with the a-IGZO channel arranged vertically and the source and drain electrodes on different planes. Notably, a significant portion of the a-IGZO channel is insulated by dielectric materials, distinguishing it from conventional V-TFT designs. We demonstrate a progressive approach to enhancing the current density output through straightforward structural modification of the wrapping a-IGZO transistors.

2. Methods

Three types of wrapping a-IGZO transistors are proposed to achieve a higher current density output compared to the reference devices: a-IGZO TFT and a-IGZO SGT. The a-IGZO TFT and a-IGZO SGT are shown in Figure 1a,b, respectively. The three types of IGZO wrapping transistors are shown in Figure 1c,d, where a significant portion of the a-IGZO channel is covered by dielectrics. SiO2 was selected as the dielectric material due to its very high band gap of 9 eV and low defect density, with well-demonstrated performance as an insulator with a high breakdown voltage [33,34].
In the type 1 wrapping a-IGZO transistor, both the source and drain contacts are ohmic in nature. In contrast, for type 2 and type 3 wrapping a-IGZO transistors, the drain contact is ohmic, with Schottky source contacts. The dielectric configurations for type 1 and type 2 wrapping a-IGZO transistors are identical. Notably, the narrow dielectric regions in the type 3 wrapping a-IGZO transistor are 7 nm longer in the vertical direction compared to the narrow dielectric regions in the type 1 and type 2 wrapping a-IGZO transistors. The length of the narrow section of the top dielectrics for all wrapping transistors is 0.5 μm. The channel lengths for both the a-IGZO TFT and the a-IGZO SGT are 3 μm, and the a-IGZO length between the top two dielectric layers in all wrapping transistors is also 3 μm. The channel width for all devices is 1 μm.
In this study, all devices were modeled using a technology computer-aided design (TCAD) Silvaco Atlas device simulator to evaluate device performance. The key physical parameters used in the TCAD simulations are summarized in Table 1. For the a-IGZO SGT, as well as for type 2 and type 3 wrapping transistors, the source barrier height can be significantly influenced by the oxygen content at the interface between Schottky source contact and a-IGZO [16,17]. Variations in interfacial oxygen levels can result in measured barrier heights that are often lower than their theoretical values [16]. Consequently, even when employing a high work function metal such as Pt as the source contact for a-IGZO, the resultant Schottky barrier height can vary considerably, ranging from 0.17 eV to 0.77 eV [16]. A higher Schottky barrier at the source enhances channel control, but can also limit the device’s current density output [17]. To balance these factors, we set the work function of the source to 4.41 eV, achieving a source barrier height of 0.25 eV while maintaining a high current density output. The threshold voltage (VTH) of the devices is determined from the transfer curves when ID is 10 nA. The current density is defined as the drain current per unit width.

3. Results and Discussion

Figure 2a shows the transfer characteristics of the a-IGZO TFT and a-IGZO SGT devices. The VTH for the a-IGZO TFT and a-IGZO SGT are estimated to be 0.43 V and 0.53 V, respectively. Figure 2b shows the output characteristics of the a-IGZO TFT and a-IGZO SGT. Figure 2c,d depicts TCAD simulation contour plots of the electron concentration in the channel region for the a-IGZO TFT and a-IGZO SGT at VG = 6 V and VD = 6 V. As shown in Figure 2a, when VG = 6 V and VD = 6 V, the current densities of the a-IGZO TFT and a-IGZO SGT are 9.19 and 3.72 μA/μm, respectively. Therefore, the current density of the a-IGZO SGT is approximately 40% of that of the a-IGZO TFT. However, the a-IGZO SGT demonstrates well-defined saturation and pinch-off behavior in its output characteristics compared to the a-IGZO TFT. This behavior is attributed to the formation of a potential barrier at the interface between the source contact and the channel layer [18]. As shown in Figure 2d, this potential barrier creates a depletion region that suppresses electron flow within the channel layer. In OLED applications, when the driving TFT in the OLED exhibits a large slope in the saturation region, the driving current decreases, which negatively impacts display brightness [35]. In contrast, the flat saturation characteristic of the SGT enables a stable output current across a wide range of VD, ensuring consistent performance [17].
Figure 3a shows the transfer characteristics of the three types of wrapping a-IGZO transistors. When VG = 6 V and VD = 6 V, the current densities of the type 1, type 2, and type 3 wrapping a-IGZO transistors are 146.63, 7.46 and 7.34 μA/μm, respectively. Figure 3b,c shows the output characteristics of these three types of wrapping a-IGZO transistors. Figure 3d-f shows the TCAD simulation contour plots of electron concentration in the channel region for these transistors at VG = 6 V and VD = 6 V. As shown in Figure 3d, the type 1 wrapping a-IGZO transistor demonstrates an extremely high electron concentration in the channel. A significant challenge with the type 1 wrapping a-IGZO transistor is its inability to pinch off, as shown in Figure 3b. Furthermore, it exhibits a large negative VTH of −2.20 V, which is attributed to the high electron concentration in the channel. While the type 1 wrapping a-IGZO transistor demonstrates the highest current density output, the very negative VTH is unfavorable for display applications.
To address this issue, we modified the design of the type 1 wrapping a-IGZO transistor by replacing two ohmic source contacts with Schottky source contacts, resulting in the type 2 wrapping a-IGZO transistor, as depicted in Figure 1d. Similarly to the SGTs, the Schottky source contacts in the type 2 configuration suppress electron concentration in the channel by creating potential barriers between the source contacts and channel, as illustrated in Figure 3e. This modification leads to clear flat saturation and pinch-off behavior, as shown in Figure 3c. This improvement is attributed to its wrapping architecture with dual Schottky source contacts, which more effectively suppress the electron concentration within the channel (see Figure 3d,e). Nonetheless, the type 2 wrapping a-IGZO transistor still exhibits a negative VTH of −0.61 V.
To further shift the VTH in the positive direction, the narrow dielectric regions in the type 2 wrapping a-IGZO transistor were extended by an additional 7 nm, resulting in the design of the type 3 wrapping a-IGZO transistor, as shown in Figure 1e. The vertical dielectric extension of 7 nm facilitated a shift in VTH from −0.61 V to −0.01 V, as shown in Figure 3a. Under a VG of −1 V, both the type 2 and type 3 wrapping a-IGZO transistors can be turned off. Figure 4a,b presents TCAD simulation contour plots of the electron concentration in the channel region for both the type 2 and type 3 wrapping a-IGZO transistors at VG = −1 V. Notably, the 7 nm vertical dielectric extension results in the type 3 wrapping a-IGZO transistor exhibiting a reduced electron concentration in the narrow channel region compared to the type 2 wrapping a-IGZO transistor. This reduction in electron concentration is a key factor contributing to the positive shift in VTH. Figure 3f shows that the 7 nm vertical dielectric extension also slightly suppresses the electron concentration in the narrow channel region when VG = 6 V and VD = 6 V. Consequently, the type 3 wrapping a-IGZO transistor exhibits nearly identical output characteristics to its type 2 counterpart, with clear flat saturation and pinch-off behavior. Furthermore, the current density of the type 3 wrapping a-IGZO transistor reaches 7.34 μA/μm, approximately twice that of the a-IGZO SGT.

4. Conclusions

In this study, we propose a novel wrapping a-IGZO transistor architecture that achieves an enhanced current density output. Through structural optimization, the current density of the type 3 wrapping a-IGZO transistor reached 7.34 μA/μm, representing an approximate two-fold improvement compared to the a-IGZO SGT. Additionally, the type 3 wrapping a-IGZO transistor demonstrates clear flat saturation and pinch-off behavior. These results highlight the significant potential of the proposed wrapping a-IGZO transistors for applications in large-area electronics, representing an important step toward future advancements in the field.

Author Contributions

Conceptualization, J.L., J.J. and J.Z.; methodology, J.L., S.H., Z.X. and N.L.; writing—original draft preparation, J.L. and J.J.; writing—review and editing, J.J. and J.Z.; supervision, J.K., J.J. and J.Z. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the National Key Research and Development Program of China, grant number 2022YFB3603900; the National Natural Science Foundation of China, grant number 62204143; the Natural Science Foundation of Shandong Province, grant number ZR2022ZD04; the Korea Basic Science Institute (National Research Facilities and Equipment Center) grant funded by the Ministry of Education, grant number 2021R1A6C101A405.

Data Availability Statement

The data presented in this study are available upon request from the corresponding authors.

Conflicts of Interest

The authors declare no conflicts of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; or in the decision to publish the results.

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Electronicmat 06 00002 g001
Figure 1. Schematic of (a) a-IGZO TFT, (b) a-IGZO SGT, (c) type 1 wrapping a-IGZO transistor, (d) type 2 wrapping a-IGZO transistor, and (e) type 3 wrapping a-IGZO transistor.
Figure 1. Schematic of (a) a-IGZO TFT, (b) a-IGZO SGT, (c) type 1 wrapping a-IGZO transistor, (d) type 2 wrapping a-IGZO transistor, and (e) type 3 wrapping a-IGZO transistor.
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Figure 2. (a) Transfer characteristics of a-IGZO TFT and a-IGZO SGT. (b) Output characteristics of a-IGZO TFT and a-IGZO SGT. Electron concentration plots of (c) a-IGZO TFT and (d) a-IGZO SGT when VG = 6 V and VD = 6 V.
Figure 2. (a) Transfer characteristics of a-IGZO TFT and a-IGZO SGT. (b) Output characteristics of a-IGZO TFT and a-IGZO SGT. Electron concentration plots of (c) a-IGZO TFT and (d) a-IGZO SGT when VG = 6 V and VD = 6 V.
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Figure 3. (a) Transfer characteristics of wrapping IGZO transistors. (b) Output characteristics of type 1 wrapping a-IGZO transistor. (c) Output characteristics of type 2 and type 3 wrapping a-IGZO transistor. Electron concentration plots of (d) type 1, (e) type 2, and (f) type 3 wrapping a-IGZO transistors when VG = 6 V and VD = 6 V.
Figure 3. (a) Transfer characteristics of wrapping IGZO transistors. (b) Output characteristics of type 1 wrapping a-IGZO transistor. (c) Output characteristics of type 2 and type 3 wrapping a-IGZO transistor. Electron concentration plots of (d) type 1, (e) type 2, and (f) type 3 wrapping a-IGZO transistors when VG = 6 V and VD = 6 V.
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Figure 4. Electron concentration plots of (a) type 2 and (b) type 3 wrapping a-IGZO transistors when VG = −1 V.
Figure 4. Electron concentration plots of (a) type 2 and (b) type 3 wrapping a-IGZO transistors when VG = −1 V.
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Table 1. Key physical parameters for simulation.
Table 1. Key physical parameters for simulation.
ParametersIGZO
Carrier concentration1 × 1016 cm−3
Mobility10 cm2/Vs
Electron affinity4.16 eV
Band gap3.05 eV
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MDPI and ACS Style

Liu, J.; Huang, S.; Xiao, Z.; Li, N.; Kim, J.; Jin, J.; Zhang, J. Wrapping Amorphous Indium-Gallium-Zinc-Oxide Transistors with High Current Density. Electron. Mater. 2025, 6, 2. https://doi.org/10.3390/electronicmat6010002

AMA Style

Liu J, Huang S, Xiao Z, Li N, Kim J, Jin J, Zhang J. Wrapping Amorphous Indium-Gallium-Zinc-Oxide Transistors with High Current Density. Electronic Materials. 2025; 6(1):2. https://doi.org/10.3390/electronicmat6010002

Chicago/Turabian Style

Liu, Jiaxin, Shan Huang, Zhenyuan Xiao, Ning Li, Jaekyun Kim, Jidong Jin, and Jiawei Zhang. 2025. "Wrapping Amorphous Indium-Gallium-Zinc-Oxide Transistors with High Current Density" Electronic Materials 6, no. 1: 2. https://doi.org/10.3390/electronicmat6010002

APA Style

Liu, J., Huang, S., Xiao, Z., Li, N., Kim, J., Jin, J., & Zhang, J. (2025). Wrapping Amorphous Indium-Gallium-Zinc-Oxide Transistors with High Current Density. Electronic Materials, 6(1), 2. https://doi.org/10.3390/electronicmat6010002

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