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Keywords = LDO regulator network with ESD protection circuit

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21 pages, 11854 KB  
Article
Design of High-Reliability Low-Dropout Regulator Combined with Silicon Controlled Rectifier-Based Electrostatic Discharge Protection Circuit Using Dynamic Dual Buffer
by U-Yeol Seo, Sang-Wook Kwon, Dong-Hyeon Kim, Jae-Yoon Oh, Min-Seo Kim and Yong-Seo Koo
Electronics 2024, 13(15), 3016; https://doi.org/10.3390/electronics13153016 - 31 Jul 2024
Cited by 1 | Viewed by 1918
Abstract
Overshoot and undershoot caused by the current load impact the accuracy of the required output voltage and circuit performance. The transient response issue in existing low-dropout (LDO) regulators is a dynamic specification that must be addressed at the design stage. This transient response [...] Read more.
Overshoot and undershoot caused by the current load impact the accuracy of the required output voltage and circuit performance. The transient response issue in existing low-dropout (LDO) regulators is a dynamic specification that must be addressed at the design stage. This transient response is influenced by system parameters such as stability and gain. The LDO regulator suggested in this study is designed to minimize the change in output voltage by considerably enhancing the gain using a dynamic dual buffer structure. A dynamic dual buffer is utilized to effectively control undershoot and overshoot. Under the conditions that the input voltage range is from 3.3 to 4.5 V, the maximum load current is 300 mA, the output voltage is 3 V, and the output of the proposed LDO regulator with the dynamic dual buffer structure has undershoot and overshoot voltages of 41 mV and 31 mV, respectively. That is, the output voltage of the proposed LDO regulator effectively provided and discharged an additional current suited for the undershoot/overshoot conditions to enhance the transient response characteristics. Furthermore, the electrostatic discharge (ESD) robustness characteristics of the proposed LDO regulator improved because of the silicon-controlled rectifier underlying the ESD protection device embedded in the output node and power line. Full article
(This article belongs to the Special Issue Feature Papers in Circuit and Signal Processing)
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