Search Results (3)

Environmental electromagnetic interference (EMI) has always been a major interference source for multiple-channel neural recording systems, and little theoretical work has been attempted to address it. In this paper, equivalent circuit models are proposed to model both electromagnetic interference sources and neural signals in such systems, and analysis has been performed to generate the design guidelines for neural probes and the subsequent recording circuit towards higher common-mode interference (CMI) rejection performance while maintaining the recorded neural action potential (AP) signal quality. In vivo animal experiments with a configurable 32-channel neural recording system are carried out to validate the proposed models and design guidelines. The results show the power spectral density (PSD) of environmental 50 Hz EMI interference is reduced by three orders from 4.43 × 10⁻³ V²/Hz to 4.04 × 10⁻⁶ V²/Hz without affecting the recorded AP signal quality in an unshielded experiment environment. Full article

In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50 $\mathsf{\mu }$m × 65 $\mathsf{\mu }$m compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04 $\mathsf{\mu }{V}_{rms}$. Power consumption is also tested, with a measured value of 3.77 $\mathsf{\mu }$W per channel, corresponding to an overall consumption of about 60 $\mathsf{\mu }$W. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results. Full article

A low-noise and -power readout integrated circuit (IC) for two-electrode electrocardiogram (ECG) recording is developed in this study using a common-mode charge pump (CMCP) for a robust 20-V_PP common-mode interference (CMI). Two-electrode ECG recording offers more comfort than three-electrode ECG recording. Contrasting to the three-electrode ECG recording, the two-electrode ECG recording is affected by CMI during measurements; the intervention of a large CMI will distort the ECG signal measurement. To achieve robustness for the CMI, the proposed ECG readout IC adopts CMCP—it uses switched capacitors that store and subtract CMI by control logic. In this paper, a window comparator structure is applied to CMCP to obtain a signal with less distortion. The window voltage ranges were set between the input common-mode ranges in which IA can operate. Therefore, a signal with less distortion was obtained by stopping the operation of CMCP between the window voltage ranges. It also reduced additional current consumption. To achieve this, the proposed circuit is implemented using a chopper stabilization technique. The chopper implemented in the amplifier can reduce low-frequency noise components, such as 1/f noise, and it comprises a CMCP, current feedback instrumentation amplifier, QRS peak detector, relaxation oscillator, voltage reference, timing generator, and serial peripheral interface on a single chip. The proposed circuit was designed using a standard 0.18 μm CMOS process with an active area of 0.54 mm². The proposed CMCP achieves a CMI robustness of 20 V_PP at 60 Hz. The measured input-referred noise level was 119 nV/√Hz at 1 Hz, and the power consumption was 23.83 μW with a 1.8 V power supply. Full article