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Search Results (1,325)

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Keywords = digital circuits

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11 pages, 2922 KB  
Article
Efficient Implementation of a Balanced Dynamic TDMA Arbitration Scheme for System-on-Chip Buses
by Ronny García-Ramírez, Iran Medina-Aguilar, Alfonso Chacón-Rodríguez and Renato Rimolo-Donadio
Electronics 2025, 14(17), 3531; https://doi.org/10.3390/electronics14173531 - 4 Sep 2025
Abstract
This paper proposes a balanced dynamic Time Division Multiple Access bus architecture with a novel selectable–sequence–counter arbitration circuit. Most existing dTDMA-related studies focus on wireless communications, which involve significantly different architectural assumptions, design constraints, and implementation platforms compared to digital bus systems. Our [...] Read more.
This paper proposes a balanced dynamic Time Division Multiple Access bus architecture with a novel selectable–sequence–counter arbitration circuit. Most existing dTDMA-related studies focus on wireless communications, which involve significantly different architectural assumptions, design constraints, and implementation platforms compared to digital bus systems. Our comparative analysis was carried out against the only available implementation in the literature, aligning to the target domain of digital buses. The proposed SSC-based arbiter, evaluated on a 65 nm CMOS process, demonstrates superior performance, achieving substantial reductions in area and power consumption with an approximated linear resource scaling as the number of connected devices to the bus increases, unlike the quadratic growth in the conventional architecture. Thus, this work offers a practical and yet efficient novel dTDMA architecture solution for on-chip communication. Full article
(This article belongs to the Section Microelectronics)
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16 pages, 3598 KB  
Article
BTI Aging Influence Analysis and Mitigation in Flash ADCs
by Konstantina Mylona, Helen-Maria Dounavi and Yiorgos Tsiatouhas
Chips 2025, 4(3), 36; https://doi.org/10.3390/chips4030036 - 3 Sep 2025
Viewed by 84
Abstract
Bias Temperature Instability (BTI)-induced aging of transistors is a serious concern in modern electronic circuits, yet its effects on the operation of mixed-signal circuits have not been extensively studied. In this work, initially we analyze how BTI-induced aging degradation influences the analog front [...] Read more.
Bias Temperature Instability (BTI)-induced aging of transistors is a serious concern in modern electronic circuits, yet its effects on the operation of mixed-signal circuits have not been extensively studied. In this work, initially we analyze how BTI-induced aging degradation influences the analog front end of Flash analog-to-digital converters (ADCs). BTI-induced aging leads to substantial increments in the offset voltage of the ADC comparators, which in turn affect their trip point voltage, leading to the alteration of the ADC’s performance characteristics, such as gain, full-scale error and integral nonlinearity. Thus, erroneous responses are generated. Next, we propose a low-cost BTI-induced aging mitigation technique based on a circuit reconfiguration method which periodically alters the average voltage stress on the ADC comparators’ transistors. The proposed method limits the comparators’ offset voltage development, restricting the shift in their trip point voltage. Consequently, the impact of aging on the performance characteristics of the ADC is drastically reduced, and its reliability is improved. According to our simulations, after two years of operation, the gain error is reduced by 95.43%, the full-scale error is reduced by 63.31% and the integral nonlinearity is reduced by 63.00%, with respect to operation without applying the proposed aging mitigation technique. Full article
(This article belongs to the Special Issue New Research in Microelectronics and Electronics)
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20 pages, 7286 KB  
Article
Fault Identification Method for Flexible Traction Power Supply System by Empirical Wavelet Transform and 1-Sequence Faulty Energy
by Jiang Lu, Shuai Wang, Shengchun Yan, Nan Chen, Daozheng Tan and Zhongrui Sun
World Electr. Veh. J. 2025, 16(9), 495; https://doi.org/10.3390/wevj16090495 - 1 Sep 2025
Viewed by 125
Abstract
The 2 × 25 kV flexible traction power supply system (FTPSS), using a three-phase-single-phase converter as its power source, effectively addresses the challenges of neutral section transitions and power quality issues inherent in traditional power supply systems (TPSSs). However, the bidirectional fault current [...] Read more.
The 2 × 25 kV flexible traction power supply system (FTPSS), using a three-phase-single-phase converter as its power source, effectively addresses the challenges of neutral section transitions and power quality issues inherent in traditional power supply systems (TPSSs). However, the bidirectional fault current and low short-circuit current characteristics degrade the effectiveness of traditional TPSS protection schemes. This paper analyzes the fault characteristics of FTPSS and proposes a fault identification method based on empirical wavelet transform (EWT) and 1-sequence faulty energy. First, a composite sequence network model is developed to reveal the characteristics of three typical fault types, including ground faults and inter-line short circuits. The 1-sequence differential faulty energy is then calculated. Since the 1-sequence component is unaffected by the leakage impedance of autotransformers (ATs), the proposed method uses this feature to distinguish the TPSS faults from disturbances caused by electric multiple units (EMUs). Second, EWT is used to decompose the 1-sequence faulty energy, and relevant components are selected by permutation entropy. The fault variance derived from these components enables reliable identification of TPSS faults, effectively avoiding misjudgment caused by AT excitation inrush or harmonic disturbances from EMUs. Finally, real-time digital simulator experimental results verify the effectiveness of the proposed method. The fault identification method possesses high tolerance to transition impedance performance and does not require synchronized current measurements from both sides of the TPSS. Full article
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8 pages, 921 KB  
Proceeding Paper
Design of Complementary Metal–Oxide–Semiconductor Encoder/Decoder with Compact Circuit Structure for Booth Multiplier
by Yu-Nsin Wang and Yu-Cherng Hung
Eng. Proc. 2025, 103(1), 21; https://doi.org/10.3390/engproc2025103021 - 1 Sep 2025
Viewed by 202
Abstract
Multipliers are crucial components in digital processing and the arithmetic logic unit (ALU) of central processing unit (CPU) design. As the data bit length increases, the number of partial products in the multiplication process increases, resulting in an increased summation time for the [...] Read more.
Multipliers are crucial components in digital processing and the arithmetic logic unit (ALU) of central processing unit (CPU) design. As the data bit length increases, the number of partial products in the multiplication process increases, resulting in an increased summation time for the partial products. Consequently, the speed of the multiplier circuit is adversely affected by increased time delays. In this article, we present a combined radix-4 Booth encoding module that employs metal–oxide–semiconductor (MOS) transistors that share common control signals to reduce the transistor count. In HSPICE simulations, the functionality of the proposed circuit architecture was verified, and the number of transistors used was successfully reduced. Full article
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29 pages, 1990 KB  
Review
Real-Time Digital Twins for Intelligent Fault Diagnosis and Condition-Based Monitoring of Electrical Machines
by Shahin Hedayati Kia, Larisa Dunai, José Alfonso Antonino-Daviu and Hubert Razik
Energies 2025, 18(17), 4637; https://doi.org/10.3390/en18174637 - 31 Aug 2025
Viewed by 362
Abstract
This article presents an overview of selected research focusing on digital real-time simulation (DRTS) in the context of digital twin (DT) realization with the primary aim of enabling the intelligent fault diagnosis (FD) and condition-based monitoring (CBM) of electrical machines. The concept of [...] Read more.
This article presents an overview of selected research focusing on digital real-time simulation (DRTS) in the context of digital twin (DT) realization with the primary aim of enabling the intelligent fault diagnosis (FD) and condition-based monitoring (CBM) of electrical machines. The concept of standalone DTs in conventional multiphysics digital offline simulations (DoSs) is widely utilized during the conceptualization and development phases of electrical machine manufacturing and processing, particularly for virtual testing under both standard and extreme operating conditions, as well as for aging assessments and lifecycle analysis. Recent advancements in data communication and information technologies, including virtual reality, cloud computing, parallel processing, machine learning, big data, and the Internet of Things (IoT), have facilitated the creation of real-time DTs based on physics-based (PHYB), circuit-oriented lumped-parameter (COLP), and data-driven approaches, as well as physics-informed machine learning (PIML), which is a combination of these models. These models are distinguished by their ability to enable real-time bidirectional data exchange with physical electrical machines. This article proposes a predictive-level framework with a particular emphasis on real-time multiphysics modeling to enhance the efficiency of the FD and CBM of electrical machines, which play a crucial role in various industrial applications. Full article
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10 pages, 653 KB  
Article
A Novel QCA Design of Energy-Efficient Three-Input AND/OR Circuit
by Amjad Almatrood
Quantum Rep. 2025, 7(3), 38; https://doi.org/10.3390/quantum7030038 - 31 Aug 2025
Viewed by 203
Abstract
One of the nanoscale technologies that shows its capability of implementing integrated digital circuits with low power, high speed, and high density is quantum-dot cellular automata (QCA). The fundamental device for designing and implementing circuits in QCA is majority logic. In this paper, [...] Read more.
One of the nanoscale technologies that shows its capability of implementing integrated digital circuits with low power, high speed, and high density is quantum-dot cellular automata (QCA). The fundamental device for designing and implementing circuits in QCA is majority logic. In this paper, a novel energy-efficient QCA design of three-input AND/OR logic functions is proposed. This design can perform both AND and OR logic operations using the same structure with an achievement of 58% and 64% approximate reductions in power consumption compared to majority-based structures, and 31% and 32% approximate reductions in power consumption compared to the best available circuits, respectively. In addition, other physical constraints such as area and latency are improved and have better or similar results compared to the best existing circuits. The proposed circuit can be considered as a fundamental and better alternative to the majority gate for energy-efficient circuit design in QCA. This will pave the way for developing efficient large-scale QCA-based sequential and combinational circuits. Full article
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21 pages, 6240 KB  
Article
Real-Time Gain Scheduling Controller for Axial Piston Pump Based on LPV Model
by Alexander Mitov, Tsonyo Slavov and Jordan Kralev
Actuators 2025, 14(9), 421; https://doi.org/10.3390/act14090421 - 29 Aug 2025
Viewed by 300
Abstract
This article is devoted to the design of a real-time gain scheduling (adaptive) proportional–integral (PI) controller for the displacement volume regulation of a swash plate-type axial piston pump. The pump is intended for open circuit hydraulic drive applications without “secondary control”. In this [...] Read more.
This article is devoted to the design of a real-time gain scheduling (adaptive) proportional–integral (PI) controller for the displacement volume regulation of a swash plate-type axial piston pump. The pump is intended for open circuit hydraulic drive applications without “secondary control”. In this type of pump, the displacement volume depends on the swash plate swivel angle. The swash plate is actuated by a hydraulic-driven mechanism. The classical control device is a hydro-mechanical type, which can realize different control laws (by pressure, flow rate, or power). In the present development, it is replaced by an electro-hydraulic proportional spool valve, which controls the swash plate-actuating mechanism. The designed digital gain scheduling controller evaluates control signal values applied to the proportional valve. The digital controller is based on the new linear parameter-varying mathematical model. This model is estimated and validated from experimental data for various loading modes by an identification procedure. The controller is implemented by a rapid prototyping system, and various real-time loading experiments are performed. The obtained results with the gain scheduling PI controller are compared with those obtained by other classical PI controllers. The developed control system achieves appropriate control performance for a wide working mode of the axial piston pump. The comparison analyses of the experimental results showed the advantages of the adaptive PI controller and confirmed the possibility for its implementation in a real-time control system of different types of variable displacement pumps. Full article
(This article belongs to the Special Issue Advances in Fluid Power Systems and Actuators)
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16 pages, 7655 KB  
Article
A Low-Jitter Delay Synchronization System Applied to Ti:sapphire Femtosecond Laser Amplifier
by Mengyao Wu, Guodong Liu, Meixuan He, Wenjun Shu, Yunpeng Jiao, Haojie Li, Weilai Yao and Xindong Liang
Appl. Sci. 2025, 15(17), 9424; https://doi.org/10.3390/app15179424 - 28 Aug 2025
Viewed by 364
Abstract
Femtosecond lasers have evolved continuously over the past three decades, enabling the transition of research from fundamental studies in atomic and molecular physics to the realm of practical applications. In femtosecond laser amplifiers, to ensure strict synchronization between the seed laser pulse and [...] Read more.
Femtosecond lasers have evolved continuously over the past three decades, enabling the transition of research from fundamental studies in atomic and molecular physics to the realm of practical applications. In femtosecond laser amplifiers, to ensure strict synchronization between the seed laser pulse and the pump laser, enabling their precise overlap during the amplification process and avoiding a decline in pulse amplification efficiency and the generation of undesired phase noise, this study designed a synchronous timing signal generation system based on the combination of FPGA and analog delay. This system was investigated from three aspects: delay pulse width adjustment within a certain range, precise delay resolution, and external trigger jitter compensation. By using a FPGA digital counter to achieve coarse-delay control over a wide range and combining it with the method of passive precise fine delay, the system can generate synchronous delay signals with a large delay range, high precision, and multiple channels. Regarding the problem of asynchronous phase between the external trigger and the internal clock, a jitter compensation circuit was proposed, consisting of an active gated integrator and an output comparator, which compensates for the uncertainty of trigger timing through analog delay. The verification of this study shows that the system operates stably under an external trigger with a repetition frequency of 80 MHz. The output delay range is from 10 ns to 100 μs, the coarse-delay resolution is 10 ns, the fine-delay adjustment step is 1.25 ns, and the pulse jitter is reduced from a maximum of 10 ns to the hundred-picosecond level. This meets the requirements of femtosecond laser amplifiers for synchronous trigger signals and offers essential technical support and fundamental assurance for the high-power and high-efficiency amplification of Ti:sapphire ultrashort laser pulses. Full article
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13 pages, 4031 KB  
Article
A Low-Power Comparator-Based Automatic Power and Modulation Control Circuit for VCSEL Drivers
by Yejin Choi and Sung-Min Park
Photonics 2025, 12(9), 844; https://doi.org/10.3390/photonics12090844 - 24 Aug 2025
Viewed by 293
Abstract
This paper proposes an automatic power and modulation control (APMC) circuit that can directly detect the degradation of vertical cavity surface emitting laser (VCSEL) diodes by utilizing a novel voltage sensing mechanism, thereby eliminating the need for costly external monitoring photodiodes. Notably, the [...] Read more.
This paper proposes an automatic power and modulation control (APMC) circuit that can directly detect the degradation of vertical cavity surface emitting laser (VCSEL) diodes by utilizing a novel voltage sensing mechanism, thereby eliminating the need for costly external monitoring photodiodes. Notably, the proposed APMC architecture facilely observes the performance degradation by sampling the voltage values at the upper node of the VCSEL diode during both modulation on and off states. The APC loop can perceive a 25 mV voltage drop that corresponds to a 0.5 mA increase in the threshold current, providing a 4-bit digital switch signal. Thereafter, it is delivered to the VCSEL diode driver to initiate compensation of the bias current. In the AMC loop, a 50 mV voltage drop equivalent to a 1 mA reduction in the modulation current is similarly detected to produce another 4-bit digital code. The proposed APMC IC is designed by using a 180 nm CMOS process and consumes a total power of 18.2 mW from a single 3.3 V supply. Full article
(This article belongs to the Section Optoelectronics and Optical Materials)
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34 pages, 3670 KB  
Review
Electronic Artificial Intelligence and Digital Twins in Industry 5.0: A Systematic Review and Perspectives
by Alessandro Massaro
Machines 2025, 13(9), 755; https://doi.org/10.3390/machines13090755 - 23 Aug 2025
Viewed by 588
Abstract
This review analyzes the Electronic Digital Twin (EDT) tools characterizing the industrial transformation phase from Industry 4.0 to Industry 5.0. The goal is to provide innovative research EDT solutions to integrate in manufacturing production processes. Specifically, this research is focused on the possibility [...] Read more.
This review analyzes the Electronic Digital Twin (EDT) tools characterizing the industrial transformation phase from Industry 4.0 to Industry 5.0. The goal is to provide innovative research EDT solutions to integrate in manufacturing production processes. Specifically, this research is focused on the possibility of combining the advanced technologies and electronics and mechatronics of industrial machines with Artificial Intelligence (AI) algorithms. Furthermore, this review provides important elements about possible future implementations of AI-EDTs and some circuital examples to support the understanding of the concept of circuit simulation in EDT models. EDTs are useful to comprehend the modeling concepts functional to the AI application using the output of the circuit simulations. The output of the circuit is used to train the AI model, thus strengthening the capability to classify and predict the real behavior of production machines with a good accuracy. This review discusses perspectives, limits, and advantages of EDTs and is useful to define new research patterns integrating structured EDTs in advanced industrial environments. The focus of this paper is the definition of possible perspectives of EDT implementations, including AI, in data-driven processes in specific strategic areas of industrial research by classifying the scientific topics in six main pillars. This paper is also suitable for the researcher to develop innovative topics for projects scaled into different work packages based on EDT facilities. Full article
(This article belongs to the Special Issue Design and Manufacturing: An Industry 4.0 Perspective)
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20 pages, 3234 KB  
Article
Thermal Performance Enhancement in Pool Boiling on Copper Surfaces: Contact Angle and Surface Tension Analysis
by Robert Kaniowski and Sylwia Wciślik
Energies 2025, 18(17), 4471; https://doi.org/10.3390/en18174471 - 22 Aug 2025
Viewed by 513
Abstract
The electronics industry has significantly contributed to the development of efficient heat dissipation systems. One widely used technique is pool boiling, a simple method requiring no moving parts or complex structures. It enables the removal of large amounts of heat at relatively low [...] Read more.
The electronics industry has significantly contributed to the development of efficient heat dissipation systems. One widely used technique is pool boiling, a simple method requiring no moving parts or complex structures. It enables the removal of large amounts of heat at relatively low temperature differences. Enhancing pool boiling performance involves increasing the critical heat flux and the heat transfer coefficient, which defines how effectively a surface can transfer heat to a cooling fluid. This method is commonly applied in cooling electronic devices, digital circuits, and power systems. In this study, pool boiling at atmospheric pressure was investigated using copper surfaces. To validate the Rohsenow model used to estimate the maximum bubble departure diameter, a planimetric approach was applied. Measurements included average contact angle (CA), surface tension (σ), and droplet diameter for four working fluids: deionised water, ethanol, Novec-649, and FC-72. For each fluid, at least 15 measurements of CA and σ were conducted using the Young–Laplace model. This study provides a comprehensive analysis of the influence of contact angle and surface tension on nucleate boiling using four different fluids on copper surfaces. The novelty lies in combining high-precision experimental measurements with validation of the Rohsenow model, offering new insights into surface-fluid interactions critical for thermal system performance. Full article
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21 pages, 1182 KB  
Review
Review of Digital Twin Technology in Low-Voltage Distribution Area and the Implementation Path Based on the ‘6C’ Development Goals
by Yuxiang Peng, Feng Zhao, Ke Zhou, Xiaoyong Yu, Qingren Jin, Ruien Li and Zhikang Shuai
Energies 2025, 18(17), 4459; https://doi.org/10.3390/en18174459 - 22 Aug 2025
Viewed by 776
Abstract
Low-voltage distribution area is the “last kilometer” connecting the distribution network and users, and the traditional distribution system is difficult to digitally manage in the low-voltage area, resulting in untimely and imprecise handling of voltage overruns, short-circuit outages, and other abnormal problems. With [...] Read more.
Low-voltage distribution area is the “last kilometer” connecting the distribution network and users, and the traditional distribution system is difficult to digitally manage in the low-voltage area, resulting in untimely and imprecise handling of voltage overruns, short-circuit outages, and other abnormal problems. With the deployment of smart meters, new sensors, smart gateways, and other devices in distribution areas, digital intelligent monitoring and management based on digital twins in LV distribution areas has gradually become the focus of distribution network research. In view of the profound changes that are taking place in the low-voltage distribution area, this paper first summarizes the characteristics and shortcomings of the existing digital twin research in the low-voltage distribution area, then puts forward the ‘6C’ development goals for the digital transformation of the low-voltage distribution area, introduces the practice work of Guangxi Power Grid Corporation around the ‘6C’ development goals in the low-voltage distribution area. Finally, the future research work of the ‘6C’ development goals for the digital transformation of the low-voltage distribution area is promising. Full article
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23 pages, 5636 KB  
Article
Design and Implementation of Novel DC-DC Converter with Step-Up Ratio and Soft-Switching Technology
by Kuei-Hsiang Chao and Thi-Thanh-Truc Bau
Electronics 2025, 14(16), 3335; https://doi.org/10.3390/electronics14163335 - 21 Aug 2025
Viewed by 397
Abstract
This paper focuses on the development of a high-conversion-efficiency DC/DC boost converter, which features high-voltage boost ratio conversion and employs soft-switching technology to reduce conversion losses. In the proposed design, the conventional energy storage inductor used in traditional boost converters is replaced with [...] Read more.
This paper focuses on the development of a high-conversion-efficiency DC/DC boost converter, which features high-voltage boost ratio conversion and employs soft-switching technology to reduce conversion losses. In the proposed design, the conventional energy storage inductor used in traditional boost converters is replaced with a coupled inductor, and an additional boost circuit is introduced. This configuration allows the converter to achieve a higher voltage conversion ratio under the same duty cycle, thereby enhancing the voltage gain of the converter. Additionally, a resonance branch is incorporated into the converter, and by applying a simple switching signal control, zero-voltage switching (ZVS) of the main switch is realized. To decrease the switching losses typically found in hard-switching high-voltage boost ratio converters, the proposed design enhances overall power conversion efficiency. The operation principle of this novel high-voltage boost ratio soft-switching converter is first examined, followed by the component design process. The converter’s effectiveness is then confirmed through simulation in PSIM. Finally, experimental testing using the TMS320F2809 digital signal processor demonstrates that the main switch achieves ZVS, validating the practical viability of the design. The converter operates under a full load of 340 W, achieving a conversion efficiency of 92.7%, demonstrating the excellent conversion performance of the developed converter. Full article
(This article belongs to the Special Issue New Horizons and Recent Advances of Power Electronics)
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32 pages, 2273 KB  
Article
Improving the Reliability of the Protection of Electric Transport Networks
by Boris V. Malozyomov, Evgeniy V. Khekert, Nikita V. Martyushev, Vladimir Yu. Konyukhov, Valentina V. Chetverikova, Vladimir I. Golik and Vadim S. Tynchenko
World Electr. Veh. J. 2025, 16(8), 477; https://doi.org/10.3390/wevj16080477 - 20 Aug 2025
Viewed by 436
Abstract
In traction networks of mining enterprises, ensuring selective and sensitive protection remains an urgent task, especially in conditions of frequent starts of electric transport and possible cases of short circuits, lack of reliable grounding and increased spreading resistance. Standard methods—maximum current protection (MCP) [...] Read more.
In traction networks of mining enterprises, ensuring selective and sensitive protection remains an urgent task, especially in conditions of frequent starts of electric transport and possible cases of short circuits, lack of reliable grounding and increased spreading resistance. Standard methods—maximum current protection (MCP) and differential current protection (DCP)—demonstrate limited efficiency at operating currents less than 800 A, which is typical for remote sections of the contact network. The objective of this study is to develop and experimentally verify a method for adjusting the parameters of current and impulse protection, ensuring reliable shutdown of accidents at low values of short-circuit current without the need to replace equipment. The proposed method is based on transient processes modeled using differential equations and the introduction of a dynamic sensitivity coefficient reflecting the dependence of the setting on the circuit time constant. Universal response characteristics were constructed in normalized coordinates for BAT-49 and VAB-43 switches and RDSh-I and RDSh-II relays. Experiments have confirmed that the application of the method allows for reducing the tripping threshold to 600–650 A, increasing the selectivity of protection to 95% and reducing the probability of false tripping by more than two times compared to MCP/DCP. The response time remained within 35–45 ms, which meets the requirements for high-speed systems. The developed method is adapted to different network sections using the relative coordinates of the energy consumer on the supply section of the traction network and does not require complex digital equipment. This makes it especially effective in field conditions, where it is impossible to upgrade the protection using intelligent adaptive systems. Full article
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17 pages, 1720 KB  
Article
A Hybrid Quantum–Classical Network for Eye-Written Digit Recognition
by Kimsay Pov, Tara Kit, Myeongseong Go, Won-Du Chang and Youngsun Han
Electronics 2025, 14(16), 3220; https://doi.org/10.3390/electronics14163220 - 13 Aug 2025
Viewed by 380
Abstract
Eye-written digit recognition presents a promising alternative communication method for individuals affected by amyotrophic lateral sclerosis. However, the development of robust models in this field is limited by the availability of datasets, due to the complex and unstable procedure of collecting eye-written samples. [...] Read more.
Eye-written digit recognition presents a promising alternative communication method for individuals affected by amyotrophic lateral sclerosis. However, the development of robust models in this field is limited by the availability of datasets, due to the complex and unstable procedure of collecting eye-written samples. Previous work has proposed both conventional techniques and deep neural networks to classify eye-written digits, achieving moderate to high accuracy with variability across runs. In this study, we explore the potential of quantum machine learning by presenting a hybrid quantum–classical model that integrates a variational quantum circuit into a classical deep neural network architecture. While classical models already achieve strong performance, this work examines the potential of quantum-enhanced models to achieve such performance with fewer parameters and greater expressive capacity. To further improve robustness and stability, we employ an ensemble strategy that aggregates predictions from multiple trained instances of the hybrid model. This study serves as a proof-of-concept to evaluate the feasibility of incorporating a compact 4-qubit quantum circuit within a lightweight hybrid model. The proposed model achieves 98.52% accuracy with a standard deviation of 1.99, supporting the potential of combining quantum and classical computing for assistive communication technologies and encouraging further research in quantum biosignal interpretation and human–computer interaction. Full article
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