Search Results (1,387)

Achieving a high frame rate and high dynamic range (HDR) under complex illumination remains a significant challenge for airborne push-broom visible-near-infrared (VNIR) hyperspectral cameras. Problematic scenarios typically include high-contrast scenes, such as ocean whitecaps alongside deep water or concurrently sunlit and shadowed urban surfaces. To address this, a real-time HDR acquisition system based on a dual-gain complementary metal–oxide–semiconductor (CMOS) image sensor is proposed. Specifically, a four-pixel HDR fusion method is developed, utilizing an optical calibration setup to accurately determine the fusion parameters and configure the spectral region of interest (ROI) for reduced data volume. The complete workflow, encompassing spectral–spatial four-pixel binning and piecewise dual-gain fusion, is implemented on a field-programmable gate array (FPGA) using a dual-port RAM-based buffering strategy and a low-latency five-stage pipeline. Experimental results demonstrate a minimal processing latency of 0.0183 ms and a maximum frame rate of 290 frames/s. By extending the output bit depth from 11 to 15 bits, the system achieves a digital dynamic range of the final output of 2.03 × 10⁴:1, representing a 9.58-fold improvement over the original low-gain data. The fused HDR data maintain high linearity and good spectral fidelity, with spectral angle mapper (SAM) values at the 10⁻³ level. Featuring a compact and low-power design, this system provides a practical engineering solution for efficient airborne VNIR hyperspectral acquisition. Full article

As the number of elderly individuals living alone increases, the risk of fall-related accidents correspondingly rises, underscoring the need for rapid fall detection systems. Because falls are difficult to predict in terms of location, detection systems must be deployed in a distributed manner, which in turn requires compact and low-power implementations. Unlike camera sensors, radar sensors do not raise privacy concerns and are not limited by line-of-sight constraints. Moreover, compared with wearable sensors, radar enables continuous monitoring without user intervention. However, prior radar-based approaches incur high computational complexity, leading to increased power consumption and larger hardware area, thereby necessitating efficient hardware design. This paper proposes a lightweight fall detection system based on continuous-wave (CW) radar and a binarized convolutional neural network (BCNN). Radar signals are preprocessed using short-time Fourier transform (STFT) to generate binary spectrograms, which are then fed into a BCNN-based classification network. The proposed system performs binary classification of five fall activities and seven non-fall activities with an accuracy of 96.1%. The preprocessing module and classification network were implemented as hardware accelerators and integrated with a microprocessor in a system-on-chip (SoC) architecture on a field-programmable gate array (FPGA). Compared with the software implementation, the proposed hardware achieved speedups of 387.5× and 86.7× for the preprocessing and classification modules, respectively. Furthermore, the overall system processing time was 2.58 ms, corresponding to an 89.5× speedup over the software baseline. Full article

This paper presents a comparative evaluation of a wave union (WU) time-to-digital converter (TDC) implemented on two Microchip flash-based field-programmable gate arrays (FPGAs): the radiation-tolerant RTG4 (RT4G150-1CG) and the low-power SmartFusion2 (M2S150TS-1FCG1152). Both implementations use an identical VHDL architecture consisting of parallel tapped delay lines (TDLs) each with a WU pattern generator, edge-coded logic encoding, and real-time statistical bin width calibration. Single-shot precision (SSP), defined as the standard deviation of consecutive period measurements derived from calibrated timestamps, is evaluated across four independent input channels. Measurements are performed at five input frequencies (1, 2, 10, 20, and 40 MHz) and six ambient temperatures ranging from 20 °C to 60 °C. At a low input frequency, the RTG4 implementation achieves a mean SSP of 6.97 ps, while IGLOO2 yields 10.12 ps under identical conditions. As the input frequency increases, the SSP of both platforms decreases and converges to approximately 4.5 ps. However, at elevated temperatures, both devices experience observable degradation in SSP. To quantify thermal robustness, a thermal sensitivity coefficient (TSC) is introduced, defined as the rate of SSP variation with temperature. The results show that the same WU TDC core implemented on a space-graded FPGA exhibits improved thermal stability and reduced channel-to-channel variance compared to its equivalent on a commercial platform. Full article

Cotton, a globally significant crop grown in over 100 countries, sustains a $40 billion market and provides employment for over 350 million people worldwide. However, plastic contamination remains a persistent challenge within the industry, degrading cotton fiber quality and disrupting ginning. Manual inspection and optical machine-vision systems struggle when plastic fragments are concealed by fibers or lack sufficient color contrast. To address these challenges, we developed an ultrasonic phased-array imaging system operating at 40 kHz under field-programmable gate array (FPGA) control. Transmitter elements emit pulsed ultrasound along radial paths, separate reflection receivers record echo amplitudes to form acoustic images, and a set of transmission receivers captures signal attenuation, which is overlaid onto the reflection-based image to highlight potential contaminants. In preliminary laboratory-based tests on both seed cotton and lint samples, the system successfully detected visually obscured plastic fragments as small as $2\mathrm{cm}\times 2\mathrm{cm}$ with an angular resolution limit of $\pm 3°$. Distinct reflection peaks and corresponding attenuation overlays were produced across the field of view, validating the system’s detection capabilities. These results demonstrate the feasibility of using ultrasonic imaging to reveal concealed plastics in cotton processing. Integrating this approach with existing optical methods could enhance contaminant-removal workflows and improve overall fiber quality and processing efficiency. Full article

This paper presents a high-performance and resource-efficient Field Programmable Gate Array (FPGA)-based architecture for satellite telemetry transmission systems. The proposed design implements a flexible channel coding chain, including Reed–Solomon (R-S) encoding, convolutional encoding, symbol interleaving, pseudo-randomization, and Attached Synchronization Marker (ASM) insertion, in accordance with CCSDS recommendations. The architecture is fully integrated and configurable, allowing dynamic selection of coding schemes without requiring structural modifications. The system is implemented on a modern FPGA platform with a 32-bit AXI4-Stream interface at 110 MHz, reaching an effective throughput of up to 1.76 Gbps. Experimental results demonstrate reliable timing with positive setup and hold margins, allowing the system to operate at approximately 130 MHz. Power consumption is measured using Switching Activity Interchange Format (SAIF)-based switching activity, providing a realistic estimate of programmable logic power consumption. The total on-chip power is about 1.77 W for individual coding modes. It rises to 1.91 W in the concatenated setup, which is the worst-case scenario. The results show that the proposed architecture efficiently uses resources, runs reliably at high speeds, and exhibits predictable power consumption. This makes it well suited for high-reliability and energy-constrained satellite communication systems. resources are used. Full article

With the growing importance of personal information security, numerous methods have been proposed for data encryption. To ensure system safety, ciphers must be unpredictable and robust. In modern Rivest–Shamir–Adleman (RSA) encryption systems, two prime numbers are required for key generation, and their randomness and unpredictability are essential for security. In this study, we propose a secure system for generating the prime numbers used in RSA encryption. The inherent properties of chaotic systems are employed as a Pseudo Random Number Generator (PRNG), while a Ring Oscillator is utilized as a True Random Number Generator (TRNG). The Miller–Rabin algorithm is further applied to verify the primality of the numbers produced by the PRNG. The entire design is implemented on a Field Programmable Gate Array (FPGA) to achieve a fully hardware system. Full article

Stereo matching constitutes a critical technology in applications such as autonomous driving and robot navigation. Conventional algorithms, however, often encounter limitations in real-time performance and resource efficiency when deployed on embedded platforms. This paper presents a real-time stereo matching system implemented on a Field-Programmable Gate Array (FPGA), which is built around a lightweight, hardware-optimized dual-path Semi-Global Matching (SGM) algorithm. The proposed method simplifies the traditional eight-path cost aggregation into horizontal and vertical dual-path aggregation, substantially reducing hardware resource consumption while preserving matching accuracy. The system employs a pipelined architecture that integrates image capture, DDR3 caching, and HDMI display output. Experimental results demonstrate that under the configuration of a 5 × 5 matching window and a disparity range of 64, the system generates stable disparity maps at 60 frames per second, with total power consumption below 2.2 W and FPGA core logic utilization under 30%. Compared to the conventional eight-path SGM, the dual-path strategy incurs only a marginal 6% increase in average bad pixel rate on standard stereo datasets while reducing Block RAM (BRAM) usage by approximately 30%. This achieves an effective practical balance between accuracy, computational efficiency, and power consumption. Full article

This study presents a nanosensor network system for autonomous microclimate optimization in precision horticulture, leveraging a field-programmable gate array (FPGA)-based control architecture that is integrated with an edge-level machine learning inference. Unlike the conventional greenhouse automation systems, which exhibit thermal and hygroscopic hysteresis often exceeding 32 °C and 78% relative humidity, the proposed framework embeds a random forest regression (RFR) model directly within the Altera DE2-115 FPGA fabric to enable predictive environmental regulation. The model achieved an R² of 0.985 and root mean square error (RMSE) of 0.28 °C, allowing proactive compensation for the thermodynamic disturbances from the high-intensity light-emitting diode (LED) lighting with a 120 s predictive horizon. The real-time monitoring and remote supervision were supported via a NodeMCU-based IoT gateway, achieving a 140 ms mean communication latency and a 99.8% packet delivery reliability. The preliminary validation using lettuce (Lactuca sativa) optimized the environmental parameters, while the subsequent experiments with pepper (Capsicum annuum), a commercially important and environmentally sensitive crop, demonstrated system performance under real-world conditions. The control system maintained a temperature and humidity within ±0.3 °C and ±1.2% of the setpoints, respectively, and outperformed the baseline rule-based control with a 28% increase in fresh biomass, a 22% improvement in dry matter accumulation, a 25% reduction in actuator duty-cycle switching, and an 18% decrease in overall energy consumption. These results highlight the efficacy of FPGA-integrated edge intelligence combined with low-latency IoT telemetry as a scalable, energy-efficient, and high-fidelity solution for sub-degree environmental control in next-generation, controlled-environment, and vertical farming systems. Full article

High-precision time and frequency references are essential for satellite navigation, deep-space exploration, and space science missions. To address the large size, high power consumption, and limited integration of conventional Passive Hydrogen Maser (PHM) servo electronics based on discrete analog chains, this paper proposes a miniaturized digital servo architecture for PHMs based on software-defined radio (SDR) and a field-programmable gate array (FPGA). The AD9364 is used as an integrated RF front end for microwave interrogation signal generation, receiver down-conversion, and analog-to-digital conversion (ADC), while digital demodulation, discriminator construction, and closed-loop control are implemented in the FPGA. A dual-frequency interrogation and time-division multiplexing scheme is introduced to separate the atomic and cavity responses, and an oversampling-based processing method combining outlier rejection and averaging decimation is adopted to improve the observation accuracy and noise immunity of weak error signals. Experimental results demonstrate stable closed-loop locking of the atomic transition spectrum, achieving a frequency stability of 1.46 × 10⁻¹² at 1 s, while significantly improving the compactness and integration level of the servo electronics. Full article

In conventional infrared imaging systems, non-uniformity correction typically involves continuously reading correction parameters from double data rate (DDR) memory. For high-frame-rate short-wave infrared imaging systems to achieve real-time non-uniformity correction, it is essential to minimize the reading time of correction parameters. Due to the narrow dynamic range of two-point correction and the large parameter storage required by two-point multi-segment correction, it is difficult to simultaneously achieve good correction performance and short parameter reading time under limited hardware resources. To address the above issues, this paper proposes a real-time non-uniformity correction method suitable for high-frame-rate short-wave infrared images. Based on a field-programmable gate array (FPGA), improvements are made to quadratic polynomial correction through the design of quantization methods for different parameters to enhance storage bit-width utilization; dynamic allocation of bit-widths between parameters to improve correction performance; and ping-pong buffering for DDR reading to avoid the impact of DDR read latency on parameter reading time. The storage size of the improved correction parameters is comparable to that of conventional two-point correction. Experiments were conducted on a hardware system based on the XC7A100T-2FGG484I FPGA. The experimental results show that the average non-uniformity of images after the improved quadratic polynomial correction is 0.4818%, significantly better than 0.5930% after two-point correction and slightly better than 0.4891% after two-point eight-segment correction. Blind pixel compensation was completed simultaneously with the correction. Using a 640 × 512 area array InGaAs short-wave infrared detector, the highest real-time processing frame rate reaches 800 frames per second (FPS). Full article

The rapid growth of 5G necessitates wireless receivers capable of high-speed, low-latency communication under complex channel conditions. Traditional receivers struggle with the performance–complexity trade-off in massive MIMO systems, where linear detectors underperform and maximum likelihood (ML) detection becomes computationally prohibitive. Deep-learning-based model-driven approaches have demonstrated a favorable balance between detection performance and computational cost. However, despite their algorithmic promise, the transition of these learned detectors into practical, real-time systems is critically hampered by inefficient hardware mapping, resulting in suboptimal throughput, high resource overhead, and limited scalability. To bridge this gap, this paper presents LwAMP-Net, a dedicated FPGA accelerator for a lightweight learned AMP detector. We propose a modular and multi-mode hardware architecture for LwAMP-Net, featuring an outer-product-based dataflow that mitigates pipeline stalls and multi-mode processing elements that adapt to diverse computation patterns. These innovations jointly enhance computational parallelism and resource utilization on the FPGA. Implemented on a Xilinx XC7VX690T FPGA for a 128 × 8 MIMO system with 16QAM, the accelerator achieves a 49.2% higher normalized throughput per iteration, an 85.4% improvement in throughput per LUT slice, and a 12.7% improvement in throughput per DSP compared to the state-of-the-art methods. This work provides a complete architectural solution for deploying high-performance, hardware-efficient learned MIMO detectors in real-world systems. Full article

Peripheral Component Interconnect Express (PCIe) is a critical interface for FPGA-based accelerators, yet existing controller solutions are often proprietary, costly, and/or incompatible with open-source workflows. We present a fully open-source PCIe controller, written in synthesizable Verilog and optimized for Field-Programmable Gate Array (FPGA) deployment. The core is verified using a Python-based cocotb_2.0.1 and pyuvm_4.0.0 testbench with a modeled Root Complex (RC), complete with data packet generation, automated checks for enumeration, flow control, and retry mechanisms. On an AMD Xilinx AC701 (XC7A200T), the design achieves less than 6% LUT utilization, timing closure at 100 MHz user clock, and demonstrates compatibility with vendor transceivers. Reference builds also meet timing on Altera Agilex devices with similar resource utilization. All RTL, verification infrastructures, and example designs are publicly released, enabling reproducible research and accelerating the development of PCIe-enabled systems for high-speed data acquisition, NVMe front-ends, and custom FPGA accelerators. Full article

Droplet manipulation constitutes a fundamental operation in numerous bio-microfluidic applications, including but not limited to medical diagnostics and targeted drug delivery. Among the various technologies developed for this purpose, magnetic digital microfluidics (MDMF) has emerged as a compelling approach due to its inherent advantages of contamination-free actuation, low cost, and configurational flexibility. Nevertheless, conventional MDMF remains constrained by its reliance on bulky instrumentation and substantial power consumption for generating controllable magnetic fields, which limit its in-field applications. To address these limitations, this work presents a programmable and portable electromagnetic microfluidic droplet manipulation platform that synergistically integrates static and dynamic magnetic fields to enable non-contact, high-precision droplet control under ultra-low power conditions. The proposed system comprises an electromagnetic actuation module, a permanent magnet, and a glass substrate coated with Teflon film. The entire system is secured by a PMMA support structure, within which a glass substrate is mounted and spatially separated from the permanent magnet. The PMMA support is fabricated using a milling process, offering a simple manufacturing procedure and high structural reusability and reproducibility. The control logic is implemented on a field-programmable gate array (FPGA) development board, facilitating fully autonomous operation powered by a standard battery. The platform operates at a low voltage of 3.5 V and a driving current of 180 mA, corresponding to a total power consumption of merely 0.63 W, while achieving robust manipulation of droplets in the volume range of 0.5 to 5 μL. A maximum average droplet velocity of up to 0.6 cm/s was attained under optimal conditions. The proposed platform offers a scalable and energy-efficient solution for portable droplet-based assays and holds significant promise for integration into point-of-care diagnostic tools and field-ready biochemical analysis systems. The platform demonstrates excellent operational stability and reproducibility, as validated by repeated actuation experiments with a positioning deviation of approximately 0.1 mm under optimized conditions. The fabrication process also exhibits high reliability with consistent performance across multiple experimental runs. Full article

Selectively modulating specific brain-rhythm bands with physical stimuli helps both to reveal neural mechanisms and to provide non-pharmacological treatment avenues for brain disorders. This study proposes and implements a multi-channel transcranial magneto-acoustic stimulation driving system based on amplitude-modulated (AM) sine waves (AM-TMAS) intended to supply a reliable hardware platform for noninvasive, focal low-frequency rhythmic electrical stimulation of deep-brain structures. The driving system implements a 64-channel AM module based on an FPGA plus high-speed DACs. Multi-channel precision is achieved via a unified high-speed clock and a global UPDATE trigger. To overcome the large separation between envelope and carrier frequencies, we developed a high-fidelity AM waveform generation method based on DDS + LUT + envelope multiplication. The algorithm first centers the carrier samples to preserve waveform symmetry, then applies LUT-based envelope coefficients and fixed-point envelope multiplication, enabling high-precision AM outputs with carrier frequencies from 100 kHz to 2 MHz and envelope frequencies from 0.1 Hz to 100 kHz. We tested the system’s rhythmic multi-channel AM output performance across frequencies and also measured magneto-acoustic-coupled rhythmic electrical signals produced by the AM-TMAS driving setup. Any single channel reliably produced high-fidelity AM waveforms with a 500 kHz carrier and 8 Hz/40 Hz envelopes; the measured carrier was 499.998 kHz with excellent frequency stability. Both envelope and carrier frequencies are flexibly tunable. At the nominal 500 kHz carrier, envelope fidelity was further quantified: the extracted envelopes achieved NRMSEs of 1.0795% (8 Hz) and 1.9212% (40 Hz), confirming high-fidelity AM synthesis. Under a 0.3 T static magnetic field, the AM-TMAS driving system generated rhythmic electrical responses in physiological saline that carried the expected 40 Hz envelope. The proposed AM-TMAS driver achieves high accuracy in AM waveform generation and robust multi-channel performance, and—when combined with an external static magnetic field—can produce rhythmically modulated magneto-acoustic electrical stimulation. This platform provides a practical technical tool for brain-function research and the development of rhythm-targeted neuromodulation therapies. Full article

Externally excited synchronous machines (EESMs) are a rare-earth-free solution for traction applications. However, variable field excitation and magnetic coupling increase control complexity. Efficient validation of the resulting control functionalities can be carried out using hardware-in-the-loop (HIL) testing, which requires high-fidelity real-time simulation models. This paper presents a semi-analytical, discrete-time EESM model tailored for HIL applications. Nonlinear magnetic saturation and magnetic coupling are captured using an inverted flux–current characteristic combined with a rotating coordinate transformation, which improves resource utilization. Spatial harmonics are included through a Fourier decomposition of the angle-dependent inverse characteristics. Additionally, different loss mechanisms are considered to accurately represent the physical behavior of the machine. The model is parameterized using finite element analysis (FEA) results from a 100$\mathrm{k}$$\mathrm{W}$ salient-pole EESM. It is implemented on a field-programmable gate array to achieve real-time capability at a simulation frequency of $2.5$$\mathrm{M}$$\mathrm{Hz}$. Validation results for the typical operating range show deviations below $0.1$% compared to detailed FEA results, demonstrating accurate real-time simulation of the electromagnetic behavior. Full article