Search Results (985)

The cascaded H-bridge static synchronous compensator (STATCOM) has been widely employed in medium- and high-voltage reactive power compensation applications due to its high modularity, fast response speed, and direct grid connection capability. However, the DC-link voltage exhibits an inherent double-frequency ripple, which poses a serious challenge to power quality. Therefore, numerous Active Power Decoupling (APD) techniques have been proposed. However, existing schemes still exhibit certain limitations: independent APD topologies are associated with higher costs, whereas single bridge-arm multiplexed APD topologies are confronted with issues such as elevated DC-side voltage and increased current stress on the multiplexed arm. Consequently, comprehensive optimization is difficult to achieve in terms of the number of power devices, decoupling accuracy, level of capacitor multiplexing, and device stress. To address the above issues, this paper proposes a DC split capacitor (DC-SC)-based dual bridge-arm multiplexed cascaded H-bridge STATCOM with active power decoupling capability, along with its corresponding control method. By constructing a fundamental-frequency common-mode voltage on the decoupling capacitor, this method effectively suppresses the double-frequency ripple in the DC-side voltage and reduces the current stress on the switching devices. The simulation and experimental results have verified the correctness and effectiveness of the proposed topological structure and control method. Full article

Reinforcement learning (RL) agents are increasingly deployed for voltage control in power distribution networks. However, their opaque decision-making creates a significant trust barrier, limiting their adoption in safety-sensitive operational settings. This paper presents XRL-LLM, a novel framework that generates natural language explanations for RL control decisions by combining game-theoretic feature attribution (KernelSHAP) with large language model (LLM) reasoning grounded in power systems domain knowledge. We deployed a Proximal Policy Optimization (PPO) agent on an IEEE 33-bus network to coordinate capacitor banks and on-load tap changers, successfully reducing voltage violations by 90.5% across diverse loading conditions. To make these decisions interpretable, KernelSHAP identifies the most influential state features. These features are then processed by a domain-context-engineered LLM prompt that explicitly encodes network topology, device specifications, and ANSI C84.1 voltage limits.Evaluated via G-Eval across 30 scenarios, XRL-LLM achieves an explanation quality score of 4.13/5. This represents a 33.7% improvement over template-based generation and a 67.9% improvement over raw SHAP outputs, delivering statistically significant gains in accuracy, actionability, and completeness ($p<0.001$, Cohen’s d values up to 4.07). Additionally, a physics-grounded counterfactual verification procedure, which perturbs the underlying power flow model, confirms a causal faithfulness of 0.81 under critical loading. Finally, five ablation studies yield three broader insights. First, structured domain context engineering produces synergistic quality gains that exceed any single knowledge component, demonstrating that prompt composition matters more than the choice of foundational model. Second, even an open source 8B-parameter model outperforms templates given the same prompt, confirming the framework’s backbone-agnostic value. Most importantly, counterfactual faithfulness increases alongside load severity, indicating that post hoc attributions are most reliable in the high-stakes regimes where trustworthy explanations matter most. Full article

A novel modular multilevel converter (MMC)-based spark-gap trigger generator for high-voltage pulsed-power applications has been developed and presented in this work. It fully exploits the inherent modularity of MMC topology to generate high-voltage trigger pulses in a flexible and scalable manner. A prototype based on insulated gate bipolar transistors (IGBTs) was constructed to effectively trigger the breakdown of the spark gaps of a Marx Bank consisting of four capacitors charged to 50 kV. It is characterized by a fast rise time and produces pulses of 15 kV with a duration of ~200 ns. Using semiconductors and foil capacitors, the new trigger generator successfully replaces the thyratron-based generator. Full article

The widespread development of medium-voltage and high-voltage direct current transmission systems has highlighted the modular multilevel converter (MMC) as a crucial enabling technology. However, the overall performance and lifetime of the MMC strongly depend on the integrity of its submodules (SMs), making online capacitance condition monitoring a critical requirement. Unlike recent related studies that rely on computationally heavy matrix-based algorithms or “black-box” artificial neural networks requiring massive offline training datasets, this paper proposes a parametric, adaptive linear neuron network. Mapped directly to the physical equations of the MMC, the method simultaneously exploits the arm current, SM switching state, and capacitor voltage to identify online parametric variations caused by aging or harsh conditions. The proposed scheme is fully non-intrusive, requiring no additional hardware sensors or signal injections, thereby reducing implementation complexity. The simulation results obtained in MATLAB/Simulink (vR2024b) demonstrate the method’s fast convergence and a quantified steady-state estimation error within ±1%. Furthermore, the estimator exhibits strong robustness under severe operating conditions, successfully maintaining accuracy during a 20% capacitance reduction, a 100% active power step variation, dc-link voltage fluctuations, measurement noise, grid unbalances, and harmonic perturbations. Full article

This paper explores a new switching strategy for a recently proposed quadratic boost converter. The topology under study is a high-step-up DC–DC converter with a configuration that allows a portion of the processed energy to be used in what we call a non-series transfer. This characteristic reduces the amount of power processed redundantly. This converter, called a Quadratic Boost Converter based on Non-Series Energy Transfer (QBC-NSET), also has a non-pulsating input current, which is especially desirable for applications like photovoltaic and fuel-cell sources. This paper proposes a different switching strategy that reduces the output voltage ripple without increasing the switching frequency and without increasing the stored energy (inductance in inductors or capacitance in capacitors). The converter has two transistors, originally operated with synchronized signals; the proposed strategy provides independent switching signals with a phase shift between them. This enables the output capacitor to charge in a different switching state, producing a smaller voltage ripple while preserving the advantages of the topology originally presented. Steady-state analysis and voltage gain derivations confirm that the fundamental conversion characteristics remain unchanged. Experimental results obtained from a laboratory prototype validate the effectiveness of the proposed approach, demonstrating the reduction in the output voltage ripple. Full article

In low-voltage-input, high-voltage-output applications, the input-parallel output-series (IPOS) LLC resonant converter experiences voltage and current imbalances due to parameter mismatches in resonant tank components. To address this issue, a self-balancing IPOS LLC resonant converter based on a shared inductance–capacitance (shared L-C) network is proposed. This topology achieves passive voltage and current self-equalization with an interconnection network of resonant inductors and capacitors between modules that does not need additional active components or complex control strategies. An analytical model based on the fundamental harmonic approximation (FHA) is developed to quantitatively assess the balancing performance, and a comparison is made with traditional structures and IPOS structures with only shared inductance. A 1.25 kW two-phase LLC resonant converter prototype is built for experimental validation. The results demonstrate that the balancing errors of the traditional structure and the shared inductance structure reach up to 25.43% and 17.63%, respectively, whereas the proposed structure significantly reduces the balancing error to only 0.43%. This study confirms that this structure provides a simple and reliable solution for voltage and current equalization in high-gain DC–DC conversion systems. Full article

Modular multilevel converters (MMCs) for high-voltage direct current (HVDC) transmission require substantial submodule (SM) capacitance to limit capacitor voltage ripple, resulting in bulky and costly converter valves. The integrated gate-commutated thyristor (IGCT), with its higher voltage rating and lower conduction loss compared to the insulated-gate bipolar transistor (IGBT), enables a significant reduction in the number of SMs per arm, offering a pathway toward compact converter design. This paper investigates how the reduced SM count of IGCT-based MMCs affects the feasibility and benefit of operating with elevated capacitor voltage ripple to further decrease SM capacitance. An analytical framework is developed to evaluate the modulation boundary under increased ripple, explicitly accounting for the voltage ripple coupling (CVR) effect and circulating-current suppression. A ripple-tolerance coefficient κ is introduced, and its optimal value is determined by identifying the inflection point beyond which the achievable AC voltage output begins to decline. For a ±500 kV/2000 MW IGCT-MMC case study using 6.5 kV devices with 250 SMs per arm, the proposed method reduces the per-unit energy storage requirement by up to 39.4% compared with conventional-ripple operation. Simulation and prototype experimental results on a 400 V, 3 kW, 4-SM/arm test bench validate the analytical predictions and confirm the practical feasibility of the approach. Full article

Maintaining voltage stability and minimizing power losses for remote marine loads powered by long submarine cables is the challenging context of this paper. Flexible Alternating Current Transmission Systems (FACTS) are well-studied for terrestrial grids. However, their comparative performance and efficiency in the context of high-capacity submarine links remain a gap in the literature. This paper presents a rigorous analysis of the performance of a Unified Power Flow Controller (UPFC), Static Synchronous Series Compensator (SSSC), and Thyristor Controlled Series Capacitor (TCSC). A mathematical framework is developed to introduce the “solution circle” concept, which demonstrates that the series impedance values required to maintain a specific load voltage define a circle in the complex plane. A theoretical analysis is performed, revealing that the UPFC, with its two degrees of freedom, is significantly more efficient because it can select the minimum impedance magnitude on this circle. In contrast, SSSC and TCSC are limited to the reactive axis, which, under certain operating conditions, may not cross the solution circle; therefore, they may not meet the power quality objective. The results of a practical case study show that UPFC requires approximately half the rated power (22.4 MVA) compared to its counterparts (39.4 MVA) to achieve the same control objectives. Full article

This paper presents a systematic experimental comparison of three sliding-mode-based current control strategies—traditional sliding mode control (SMC), fast terminal sliding mode control (FTSMC), and super-twisting sliding mode control (STSMC)—applied to a grid-connected five-level active neutral point clamped flying capacitor (5L-ANPC-FC) inverter. Unlike existing studies that typically investigate a single controller or topology, this work provides a fair, hardware-validated benchmark under identical operating conditions, enabling a clear assessment of convergence speed, harmonic performance, robustness, and implementation complexity. All controllers are designed within a unified framework and their stability is rigorously analyzed using Lyapunov theory. Experimental evaluations are conducted under steady-state operation, step changes in reference current, grid-voltage sag/swell, and DC-link voltage variations. The results demonstrate that while all three controllers ensure robust current tracking and inherent DC-side capacitor voltage balancing without additional control loops, FTSMC achieves the lowest grid-current total harmonic distortion (THD) and fastest convergence. STSMC effectively suppresses chattering, and traditional SMC offers a simple yet reliable baseline solution. The presented findings provide practical design guidelines for selecting appropriate sliding-mode controllers in high-performance multilevel inverter applications. Among the assessed control techniques, FTSMC has the most rapid dynamic response, characterized by a rise time of 0.1 ms and a minimal grid-current THD of 1.95%, indicating exceptional steady-state and transient performance. STSMC markedly diminishes chattering and ripple, attaining a THD of 2.04% with enhanced waveform smoothness relative to traditional SMC. Conversely, traditional SMC offers a more straightforward implementation but demonstrates elevated ripple and THD levels of around 2.29%, along with a peak current inaccuracy of 6–8%. The results underscore the trade-offs between implementation simplicity, dynamic responsiveness, and harmonic performance of the evaluated control techniques. Full article

This paper presents a quadruple step-down (QSD) trans-inductor voltage regulator (TLVR) converter to accommodate the high-current and fast-transient requirements of processor power supplies. Evolved from dual-step-down (DSD) topology, the QSD configuration offers stronger load capacity; three additional flying capacitors are introduced between adjacent phases to break the 25% duty cycle constraint, thereby extending the output voltage range and accelerating the transient response. Moreover, the converter’s transient response is optimized to its full potential through both multi-phase simultaneous operation and the incorporation of the dedicated TLVR architecture. A modified adaptive on-time (AOT) controller supporting four-phase simultaneous operation is employed. Designed and verified via post-layout simulation in a 180 nm BCD process with all 6 V power transistors, the converter achieves a peak efficiency of 96.1% at 24 V input and 3 V output, as well as a maximum load capacity of 20 A. Under a 19 A load current step with a 19 ns rise time, it exhibits only a 37 mV output voltage droop and a 2 μs settling time, even with a 100 μF output capacitor. Full article

Wind energy harvesting based on triboelectric nanogenerators (TENGs) is a promising solution for powering distributed Internet of Things (IoT) nodes, yet its practical efficiency and stability are often hindered by the fluctuating and unpredictable nature of wind. Here, we propose a self-regulating TENG (SR-TENG) that leverages the synergistic effects of centrifugal, elastic, and frictional forces to automatically switch between non-contact and contact modes based on wind speed. This configuration achieves an ultra-low start-up wind speed of 0.86 m/s, ensures sustainable high-performance output across a broad wind speed range, and exhibits excellent durability with no observable performance degradation during 23,000 s of continuous operation at 375 rpm. Systematic structural optimization enables the SR-TENG to reach a peak open-circuit voltage of 140 V, a short-circuit current of 12.5 μA, and a transferred charge of 300 nC at 375 rpm. When integrated with a customized power management circuit, the system delivers a 30.39-fold increase in effective output power at a 1 MΩ load and a 4-fold faster charging rate for a 10 μF capacitor. For practical validation, the harvested ambient wind energy successfully powers a wireless temperature-humidity sensor for real-time cloud data transmission. These results highlight that the SR-TENG holds great potential for advanced wind energy harvesting and self-powered sensing applications in distributed IoT systems. Full article

This paper reviews circuit topologies in the literature that aim to suppress submodule (SM) capacitor-voltage ripple of modular multilevel converters (MMCs), since this low-frequency ripple largely determines the required SM capacitance and thus the overall converter volume, cost, and reliability. The circuit topologies covered in this review include high-frequency (HF) magnetic or switched power channels, transformerless active channel or bridging cells with mid-cell connections, hybrid-MMC and DC-bus management options, SM-level active power decoupling (APD) and active power filters (APF), and structural modifications. Physical power-channel topologies (HF magnetic or switched auxiliary paths) suppress the $2\omega$ capacitor-voltage ripple by transferring the associated low-frequency ripple power to an auxiliary high-frequency path. Hybrid-MMC and direct-current (DC) bus management reduce the required capacitance with only a modest increase in hardware requirements. SM-level APD and APF cells transfer the ripple power into auxiliary storage. Structural and topological arrangements modify the converter architecture itself, leading to architectural simplification, passive attenuation, and a reduced need for measurement or balancing. The reviewed topologies are then compared in terms of ripple reduction, hardware complexity, additional components, cost, and control complexity, and the resulting evidence is synthesised into application-driven design trade-offs and selection guidelines. In addition, DC–DC MMC topologies are discussed separately in a contextual overview. Full article

The full-bridge LLC resonant converter is one of the most suitable converters for high-power, high-efficiency applications. Although the design methodologies for full-bridge LLC resonant converters are already well-established, the development of the fractional-order domain has brought new flexibility to converter design. Based on the fact that inductors and capacitors have fractional-order characteristics, this paper presents a de-normalized fractional-order FHA gain model, which reveals the impact of fractional-order characteristics of practical inductors and capacitors on the converter gain. By maintaining the convenience of the FHA design method, this work identifies the fractional orders of a resonant tank inductor and capacitor and incorporates them into the parameter design as part of the design requirements, making the design results more accurate than the conventional FHA design method. Specifically, compared with the conventional FHA-based design, the proposed approach improves the DC voltage gain margin of the full-bridge LLC converter by 26% and expands the ZVS operating range margin by 23.3%. Full article

This paper presents an in-depth analysis of a non-isolated buck–boost DC–DC converter which uses coupled inductors. The converter is designed to achieve a high static conversion ratio while using a moderate number of semiconductor devices. The proposed topology, originally introduced in a former paper of the authors, under ideal operating conditions, is now evaluated taking into account non-ideal components, modeling the conduction losses of the semiconductor devices and the equivalent series resistance of the output capacitor. In order to get a regulated output voltage, closed-loop behavior is also investigated. By using the state-space modeling approach, the calculation of the converter static conversion ratio and control-to-output transfer functions is performed. Because the topology is of fourth order, a procedure for controller design is provided. A type III error amplifier is chosen, and the pole-zero placement technique is used for its design, demonstrating that the classical control strategy still works even with this fourth-order converter. Thus, a good phase margin of 62.3 degrees is achieved. The theoretical results are validated both on open-loop and closed-loop operation, in the presence of conduction losses. Furthermore, a laboratory prototype is implemented, and it validates the theoretical and simulation results. The study demonstrates that the proposed coupled inductors buck–boost converter is a good choice for step-up applications that need a large difference between input and output voltages. Full article

Pulse thyristors are extensively utilized in pulsed plasma discharge applications. In this study, a pulse switch prototype is built using two parallel valve groups, each consisting of seven series-connected thyristors. Each thyristor is equipped with an anti-parallel protection diode, a static voltage-sharing resistor, and an RCD (resistor-capacitor-diode) dynamic voltage-sharing circuit. The prototype withstands 24 kV, delivers 150 kA peak current, operates at 10 Hz, and can run continuously for 1 s. Thermal analysis is essential under narrow-pulse high-current conditions to avoid failure from localized overheating. By investigating the expansion process of the conduction zone during thyristor turn-on, a single-thyristor turn-on model and a finite-element model of the multi-layer series thyristor module are established to analyze transient temperature distributions. Results show a non-uniform temperature profile across the silicon wafer, with the hottest zone near the gate ring. During repetitive pulses, the silicon temperature fluctuates rapidly, while the copper base heats up gradually. At a spreading speed of 30 m/s, the gate terminal temperature rises about 38 °C—within safe limits for now, but projected to exceed them under future operating conditions. Thus, improved thermal management will be critical in further development. Full article