Search Results (5)

An extreme step-down ratio buck converter is proposed using a double step-down (DSD) buck converter architecture and a single time-based current mode PWM controller able to generate two non-overlapping control signal phases. Current sampling for two inductors is implemented with a multiplexer and a pair of VCOs only, which treats the two inductors as one inductor operating at double the frequency. This is achieved without the use of any large external passive components in the controller while remaining stable. The type-II time-based controller uses a VCO, a frequency difference phase adder (FDPA), and a phase detector, generating a control signal with fully integrated components with minimum area. FDPA for proportional control also significantly limits the signal delay of the high gain controller, allowing the use of time-based control technique at <10 MHz, which improves converter efficiency. The proposed time-based current mode controller DSD buck converter is simulated in 130 nm BCD technology operating at 1 MHz for 10 V to 1 V conversion. The simulated peak efficiency is 82.2% at 0.4 A, and recovers from a 1.8 A loading and unloading current step in 5.75 $\mathrm{\mu }$s and 9.9 $\mathrm{\mu }$s, respectively. Full article

In the context of locomotive traction systems, the power electronic traction transformer (PETT) represents a pivotal component, fulfilling essential functions pertaining to electrical isolation and power control. The majority of existing PETT prototypes employ a combination of a cascade structure and an ISOP structure. The aforementioned scheme effectively reduces the voltage withstand level of the power devices on the input side, yet it also necessitates the utilisation of a greater number of power devices and passive components within the PETT. In order to further reduce the number of power devices used, this paper proposes a new cascaded PETT design. The proposed PETT will adopt a scheme combining a cascade structure and a hardware circuit multiplexing. This paper first analyses the operation principle of the new circuit under non-single frequency PWM control. It then derives the design equations for some hardware parameters and control circuits. Finally, it verifies the effectiveness of the proposed PETT through simulation analysis. Full article

Single-phase AC–AC converters with a direct power conversion approach are receiving rapid development as they have the ability to produce the regulated non-inverting and inverting form of the input voltage at the output. This feature enables them to correct the line voltage profile once they are used as dynamic voltage restorers if there is an issue of voltage sag or swell in the power distribution system. The regulated non-inverting and inverting form of the output voltage may also be used to obtain the step change in the output frequency, as it is required in many industrial drive systems. However, the realization of such existing circuits needs a large number of components and semiconductor devices, especially switching transistors. The operating control (on and off) of the transistors is directly associated with the use of gate control circuits. The count of such circuits is critical as their volume and cost are much greater than the operating transistors. The number of conducting semiconductor devices in the existing converters is also a big source of high conversion losses, thus leading to lower efficiency. This article introduces a new circuit topology realized only with the use of one full bridge of four IGBTs and a full bridge of four diodes. The use of four switching transistors only requires four gate control circuits that drastically reduce the overall volume and size. All the operating modes of the proposed topology require the conduction of fewer semiconductor devices, which helps to lower the conduction losses. Detailed analysis and description were carried out to validate the attractive features of the developed circuit once compared with the existing circuit topologies. For validation purposes, the computer simulation was carried out on Simulink software. The results obtained from this environment were compared with the real results gained from a practically developed laboratory test bench. The voltage regulation characteristics of the output voltage by employing pulse width modulation (PWM) were confirmed for two values of the non-inverting and inverting outputs. Full article

Single-phase direct frequency converters are gaining attraction at the research and academic level as they are rapidly getting space over conventional multistage converters. The converters developed with a rectification and inversion process using a DC-link level are examples of multistage converters with some serious concerns such as an increase in the overall weight, losses, and cost. They also suffer from the low-reliability issue due to the issues involved with DC-link capacitors and problems linked with electromagnetic interference (EMI) caused by high-frequency pulse width modulation (PWM) switching. These problems are addressed with line frequency switching cycloconverters. In these converters, the power quality of the output voltage is improved by governing the amplitude of some selected output pulses or half-cycles. For this purpose, a low-frequency multiple tapping transformer may be used to obtain various voltage levels. However, its use is the main source of increased overall weight, losses, cost, and volume. In transformer eliminated topologies, high-frequency PWM control can be employed to control the magnitude of some selected half cycles of the output voltage. However, this approach may arise some problems related to EMI. In both control techniques, the attention is focused on the power quality of the output voltage only. The concern for the input current is ignored and not yet analyzed. This is one of the critical power quality concerns and requires further investigation. The magnitude control of the output half-cycles causes the variation in the amplitude of some half cycles of the input currents. As a result, all half cycles of the input current become non-symmetric. It generates harmonics that are always of low frequency and cannot be easily filtered out. It results in a high value of the harmonic factor (HF) of the input current. The improvement in the power quality of the output voltages severally degrades the power quality of the input currents. In this research, this problem is investigated with mathematically computed harmonic coefficients with a pulse selective approach. Also, a simple single-phase cycloconverter is introduced to improve the power quality index of the input current. The overall analysis is supported by the results obtained from a Simulink-based environment and a practically constructed prototype. Full article

Piezoelectric energy harvesters (PEHs) are a reduced, but fundamental, source of power for embedded, remote, and no-grid connected electrical systems. Some key limits, such as low power density, poor conversion efficiency, high internal impedance, and AC output, can be partially overcome by matching their internal electrical impedance to that of the applied resistance load. However, the applied resistance load can vary significantly in time, since it depends on the vibration frequency and the working temperature. Hence, a real-time tracking of the applied impedance load should be done to always harvest the maximum energy from the PEH. This paper faces the above problem by presenting an active control able to track and follow in time the optimal working point of a PEH. It exploits a non-conventional AC–DC converter, which integrates a single-stage DC–DC Zeta converter and a full-bridge active rectifier, controlled by a dedicated algorithm based on pulse-width modulation (PWM) with maximum power point tracking (MPPT). A prototype of the proposed converter, based on discrete components, was created and experimentally tested by applying a sudden variation of the resistance load, aimed to emulate a change in the excitation frequency from 30 to 70 Hz and a change in the operating temperature from 25 to 50 °C. Results showed the effectiveness of the proposed approach, which allowed to match the optimal load after 0.38 s for a ΔR of 47 kΩ and after 0.15 s for a ΔR of 18 kΩ. Full article