MDPI - Publisher of Open Access Journals

20 pages, 6756 KB

Open AccessArticle

Optimization of Film Thickness Uniformity in Hemispherical Resonator Coating Process Based on Simulation and Reinforcement Learning Algorithms

by Jingyu Pan, Dongsheng Zhang, Shijie Liu, Jianguo Wang and Jianda Shao

Coatings 2025, 15(6), 700; https://doi.org/10.3390/coatings15060700 - 10 Jun 2025

Viewed by 734

Abstract

Hemispherical resonator gyroscopes (HRGs) are critical components in high-precision inertial navigation systems, typically used in fields such as navigation, weaponry, and deep space exploration. Film thickness uniformity affects device performance through its impact on the resonator’s Q value. Due to the irregular structure of the resonator, there has been limited research on the uniformity of film thickness on the inner wall of the resonator. This study addresses the challenge of thickness non-uniformity in metallization coatings, particularly in the meridional direction of the resonator. By integrating COMSOL-based finite element simulations with reinforcement learning-driven optimization through the Proximal Policy Optimization (PPO) algorithm, a new paradigm for coating process optimization is established. Furthermore, a correction mask is designed to address the issue of low coating rate. Finally, a Zygo white-light interferometer is used to measure film thickness uniformity. The results show that the optimized coating process achieves a film thickness uniformity of 11.0% in the meridional direction across the resonator. This study provides useful information and guidelines for the design and optimization of the coating process for hemispherical resonators, and the presented optimization method constitutes a process flow framework that can also be used for precision coating engineering in semiconductor components and optical elements. Full article

(This article belongs to the Special Issue AI-Driven Surface Engineering and Coating)

► Show Figures

Figure 1

17 pages, 2258 KB

Open AccessArticle

Nonlinearity Harmonic Error Compensation Method Based on Intelligent Identification for Rate Integrating Resonator Gyroscope

by Xiaodi Yi, Gongliu Yang, Qingzhong Cai and Yongqiang Tu

Actuators 2025, 14(2), 68; https://doi.org/10.3390/act14020068 - 3 Feb 2025

Cited by 1 | Viewed by 2913

Abstract

This paper presents an improved intelligent optimizing algorithm based on parameter identification and drift compensation for the rate-integrating resonator gyroscope (RIRG). Besides damping and frequency imperfections, the RIRG measurement accuracy still suffers from limitations due to nonlinear error. Therefore, the dynamic nonlinear error model for RIRG has been established to reveal the relationship between the pattern angle and harmonic drifts. Based on this, a dynamic analysis of the gyroscope operating state is carried out using nonlinear motion equations. The optimal harmonic error parameters are then identified by a particle swarm optimization (PSO) algorithm for the drift error compensation. To further improve the measurement accuracy, chaotic technology is integrated with PSO, leading to more precise identification. Subsequently, the harmonic parameters of the bias drifts are efficiently compensated. Experimental results demonstrate that the bias drift is reduced by over 90% after harmonic error compensation, demonstrating the validity of the proposed method in enhancing the measurement accuracy of RIRGs. Full article

(This article belongs to the Section Precision Actuators)

► Show Figures

Figure 1

18 pages, 6283 KB

Open AccessArticle

A Low-Noise Interface ASIC for MEMS Disk Resonator Gyroscope

by Wenbo Zhang, Liang Yin, Yihang Wang, Risheng Lv, Haifeng Zhang, Weiping Chen, Xiaowei Liu and Qiang Fu

Micromachines 2023, 14(6), 1256; https://doi.org/10.3390/mi14061256 - 15 Jun 2023

Cited by 6 | Viewed by 2593

Abstract

This paper proposes a low-noise interface application-specific integrated circuit (ASIC) for a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) which operates in force-to-rebalance (FTR) mode. The ASIC employs an analog closed-loop control scheme which incorporates a self-excited drive loop, a rate loop and a quadrature loop. A ΣΔ modulator and a digital filter are also contained in the design to digitize the analog output besides the control loops. The clocks for the modulator and digital circuits are both generated by the self-clocking circuit, which avoids the requirement of additional quartz crystal. A system-level noise model is established to determine the contribution of each noise source in order to reduce the noise at the output. A noise optimization solution suitable for chip integration is proposed based on system-level analysis, which can effectively avoid the effects of the 1/f noise of the PI amplifier and the white noise of the feedback element. A performance of 0.0075°/√h angle random walk (ARW) and 0.038°/h bias instability (BI) is achieved using the proposed noise optimization method. The ASIC is fabricated in a 0.35 μm process with a die area of 4.4 mm × 4.5 mm and power consumption of 50 mW. Full article

► Show Figures

Figure 1

Search Results (3)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI

Saved Queries

Search Filter Reset All

Years

Feature Papers

Subjects

Journals

Article Types

Countries / Regions

Search Results (3)

Further Information

Guidelines

MDPI Initiatives

Follow MDPI