Search Results (166)

Capacitive sensing offers a low-power, non-optical route for automated insect monitoring, but architecture-level benchmarking under shared geometry remains limited. Rather than presenting a general framework, this study proposed a configuration-specific laboratory benchmark comparing four sigma-delta and charge-transfers in a 6 mm dual-arc conduit at 25 °C, targeting six adult terrestrial arthropod species spanning a 25-fold range of the body cross-sectional area. Static measurements showed a strong linear relationship between ΔC_static and body cross-sectional area (17.96 fF/mm², r = 0.995), supporting first-pass conduit sizing and detectability screening. In contrast, transit amplitudes were not monotonic with body size because posture, motion, and gap occupancy affected waveform shape. Under chamber conditions, static sensitivity degraded by less than 3.2% across all architectures from RH 40% to 80%. However, under the deployment-oriented noise model, SNR_FR degradation was substantially higher for charge-transfer devices (64.8–66.8%) than for Σ–Δ devices (≤35.5%), because the composite noise floor amplifies the effect of humidity-induced baseline drift. These results generated a conduit-specific reference dataset for preliminary capacitance-to-digital converter (CDC) selection within the tested 6 mm dual-arc geometry. In addition, the experimental validation focused on laboratory baseline noise characterization, long-term drift, and trap-integrated testing in temperature-controlled environments and natural-locomotion trials, providing critical information on configuration-specific architectures and body-size-scaling reference. This study serves as an initial step toward real-world capacitive insect sensing. Future studies will investigate additional conduit geometries and insect species to improve the robustness of the proposed framework. Full article

The cigarette beetle, Lasioderma serricorne, is a globally important pest of stored products, and prolonged fumigant use has accelerated resistance development. Glutathione S-transferases (GSTs) are key phase II detoxification enzymes that mediate insect tolerance to xenobiotics. In this study, we identified nine GST genes (LsGSTs) in L. serricorne and classified them into four cytosolic classes, namely epsilon, delta, theta, and sigma, based on phylogenetic analysis. Most LsGSTs were predominantly expressed during larval stages, while LsGSTs7 showed peak expression in adults. Tissue-specific profiling revealed predominant expression in metabolically active organs, including the fat body, Malpighian tubules, and midgut. Inhibition of GST activity using diethyl maleate (DEM) significantly increased larval susceptibility to three emerging fumigants: ethyl formate, benzothiazole, and methyl isothiocyanate. Exposure to LC₃₀ and LC₅₀ concentrations of these fumigants induced up-regulation of multiple LsGSTs, highlighting fumigant-specific detoxification responses. RNA interference targeting nine fumigant-inducible LsGSTs markedly elevated mortality and decreased total GST activity under fumigant stress. Furthermore, recombinant LsGSTs6 protein effectively metabolized methyl isothiocyanate, confirming their direct role in fumigant detoxification. Collectively, these findings provide novel insights into the molecular mechanisms underlying GST-mediated tolerance in L. serricorne and identify specific GST isoenzymes as promising molecular targets for innovative resistance management strategies in stored-product pest control. Full article

Introduction: Caffeine is the most widely consumed psychoactive stimulant worldwide and acts primarily through antagonism of adenosine A1 and A2A receptors, thereby reducing sleep pressure and promoting wakefulness. Although its alerting and performance-enhancing effects are well established, its influence on sleep-related electroencephalography (EEG) has been investigated across diverse paradigms with substantial methodological heterogeneity. This systematic and mechanistic review aimed to synthesize human evidence on how caffeine affects sleep architecture, quantitative sleep EEG, and neurophysiological markers of sleep homeostasis, and to interpret these findings within current models of adenosine-mediated sleep–wake regulation. Materials and Methods: A systematic search of PubMed/MEDLINE, Web of Science, Scopus, Embase, PsycINFO, ResearchGate, and Google Scholar was conducted for studies published between January 1980 and January 2026, with the final search performed on 10 January 2026. Eligible studies were original human investigations examining caffeine exposure or administration and reporting sleep-related EEG outcomes, including polysomnographic sleep staging, spectral EEG analyses, or other EEG-derived sleep metrics. Two reviewers independently screened records and assessed eligibility, with disagreements resolved by consensus. Data on study design, participant characteristics, caffeine interventions, EEG methodology, and outcomes were extracted using a predefined form. Risk of bias was evaluated using the RoB 2 and ROBINS-I tools. Owing to marked heterogeneity across studies, findings were synthesized narratively within a mechanistic interpretive framework. Results: Thirty-two studies were included. Across highly heterogeneous paradigms—including acute bedtime or evening dosing, daytime or repeated caffeine use before nocturnal sleep, administration during prolonged wakefulness followed by recovery sleep, withdrawal protocols, and ambulatory/home EEG monitoring—the most consistent finding was suppression of low-frequency NREM EEG activity, particularly slow-wave activity and the lowest delta frequencies. Caffeine frequently increased faster EEG activity, including sigma/spindle and beta ranges, producing a lighter, more aroused, and more wake-like sleep EEG profile. These effects were especially prominent during early-night NREM sleep and in recovery sleep after sleep deprivation, where caffeine attenuated the expected homeostatic rebound in low-frequency power. REM-related effects were less consistent, but some studies reported delayed REM timing and subtler alterations in REM EEG. Emerging evidence further suggests that caffeine increases EEG complexity and shifts sleep dynamics toward a more excitation-dominant state. Several studies indicated that quantitative EEG measures were more sensitive than conventional sleep-stage variables in detecting caffeine-related sleep disruption. Dose, timing, habitual caffeine use, withdrawal state, age, circadian context, and adenosinergic genetic variation, particularly involving ADORA2A, moderated the magnitude of effects. We also highlighted the connection between current results and sports and sports science. Conclusions: Caffeine reliably alters the neurophysiological architecture of human sleep in a direction consistent with reduced sleep depth and weakened homeostatic recovery. The overall evidence supports a mechanistic model centered on adenosine receptor antagonism, attenuation of sleep-pressure build-up and expression, and a shift toward greater cortical arousal during sleep. Sleep EEG appears to be a sensitive marker of these effects, often revealing physiological disruption even when conventional sleep architecture changes are modest. Future research should prioritize larger and more diverse samples, pharmacokinetic and pharmacogenetic characterization, and ecologically valid high-resolution sleep monitoring to clarify the real-world and functional consequences of caffeine-induced EEG changes. Full article

For next-generation biomedical and biochemical sensor nodes, the analog front-end demands a direct interface with current-output sensors, extreme miniaturization, and nanowatt power consumption to enable energy autonomy. This work directly addresses these needs by presenting a comparative analysis of four minimalist, first-order, current-mode $\Delta \Sigma$ modulator ($\Delta \Sigma$M) architectures. Optimized for ultra-low-voltage operation (supply $\le 0.5$ V), the investigated topologies—including resistive, switched-capacitor, and current-reference-based cores—exploit passive integration and charge-domain feedback, eliminating the need for power-hungry active blocks. Detailed circuit-level simulations confirm that, with ad hoc techniques, it is possible to achieve stable first-order noise shaping in the deep near-threshold region, delivering up to 10-bit resolution while consuming less than 10 nW at a 0.5 V supply voltage achieving a signal bandwidth in the sub-10 hertz range. This study validates that robust $\Delta \Sigma$ conversion is feasible under extreme area and power constraints by leveraging architectural simplicity. The clear performance–complexity trade-offs outlined make these current-mode architectures ideal candidates for monolithic integration within miniaturized, energy-autonomous sensing systems. Full article

This paper presents an all-digital fractional-N phase-locked loop (ADPLL) operating in the 2.86–3.2 GHz range, optimized for IoT and high-frequency RF transceiver applications demanding stringent phase noise performance, fast settling time, and high integration capability. The key innovation lies in the introduction of a bandpass delta-sigma time-to-digital converter (BPDSTDC) that achieves high-resolution phase detection, an extended detection range of ±2$\pi$, and superior noise-shaping characteristics, completely eliminating the complex calibration procedures typically required in conventional TDC designs. The proposed architecture synergistically combines the BPDSTDC with digital down-conversion blocks to extract phase error at baseband, a divider chain integrated with phase interpolators achieving 1/4 fractional resolution to suppress in-band quantization noise, and a wide-bandwidth digital loop filter (>1 MHz) ensuring fast dynamic response and robust stability. The bandpass delta-sigma modulator is implemented with compact resonator structures and a flash quantizer, achieving an optimal balance among resolution, power consumption, and silicon area. The incorporation of highly linear phase interpolators extends fractional frequency synthesis capability without requiring complex digital-to-time converters (DTCs), significantly reducing design complexity and calibration overhead. Fabricated in a 180-nm CMOS technology, the proposed chip demonstrates robust measured performance. The band-pass delta-sigma TDC achieves a low integrated rms timing noise of 183 fs within a 1-MHz bandwidth. Leveraging this low TDC noise, the complete ADPLL exhibits a measured in-band phase noise of −120 dBc/Hz at a 1-MHz offset for a 3.2-GHz output frequency while operating with a loop bandwidth exceeding 1 MHz. This corresponds to a normalized phase noise of −216 dBc/Hz. The system operates from a 1.8-V supply and consumes 10 mW, achieving competitive performance compared with prior noise-shaping TDC-based all-digital PLLs. Full article

This paper presents a low-power high-precision Discrete-Time Delta–Sigma (DT-DS) analog-to-digital converter (ADC) for a Battery Management System (BMS), which is critical for monitoring key battery parameters such as voltage, current, and temperature. This design employs a second-order Cascade of Integrators FeedForward (CIFF) architecture using a hybrid chopping technique to effectively suppress 1/f noise and offset. Fabricated in a 180 nm Bipolar-CMOS-DMOS (BCD) process, the ADC achieves a peak signal-to-noise ratio (SNR) of 91.2 dB and a peak signal-to-noise-and-distortion ratio (SNDR) of 90.6 dB within a 600 Hz bandwidth, while consuming only 35 µA from a 1.8 V supply. This corresponds to a figure-of-merit (FoM) of 160.4 dB, calculated based on the SNDR, bandwidth, and power dissipation. Full article

Reliable and low-latency seizure detection from electroencephalography (EEG) is critical for continuous clinical monitoring and emerging wearable health technologies. Spiking neural networks (SNNs) provide an event-driven computational paradigm that is well suited to real-time signal processing, yet achieving competitive seizure detection performance with constrained model complexity remains challenging. This work introduces a hybrid spike encoding scheme that combines Delta–Sigma (change-based) and stochastic rate representations, together with two spiking architectures designed for real-time EEG analysis: a compact feed-forward HybridSNN and a convolution-enhanced ConvSNN incorporating depthwise-separable convolutions and temporal self-attention. The architectures are intentionally designed to operate on short EEG segments and to balance detection performance with computational practicality for continuous inference. Experiments on the CHB–MIT dataset show that the HybridSNN attains 91.8% accuracy with an F1-score of 0.834 for seizure detection, while the ConvSNN further improves detection performance to 94.7% accuracy and an F1-score of 0.893. Event-level evaluation on continuous EEG recordings yields false-alarm rates of 0.82 and 0.62 per day for the HybridSNN and ConvSNN, respectively. Both models exhibit inference latencies of approximately 1.2 ms per 0.5 s window on standard CPU hardware, supporting continuous real-time operation. These results demonstrate that hybrid spike encoding enables spiking architectures with controlled complexity to achieve seizure detection performance comparable to larger deep learning models reported in the literature, while maintaining low latency and suitability for real-time clinical and wearable EEG monitoring. Full article

High-nitrogen austenitic stainless steels (HNASS) require compositional strategies that simultaneously maximize corrosion resistance and microstructural stability while suppressing delta (δ) ferrite and deleterious precipitates. Here, an explainable multi-objective design workflow is developed that couples thermodynamic descriptors from the Calculation of Phase Diagrams (CALPHAD) approach—using both equilibrium and Scheil solidification calculations—with machine learning surrogate models, random forest (RF) and Extreme Gradient Boosting (XGBoost), trained on 60,480 compositions in the Fe–C–N–Cr–Mn–Mo–Ni–Si space. The physics-informed feature set comprises phase fractions; transformation and precipitation temperatures for δ-ferrite, chromium nitride (Cr₂N), sigma (σ) phase and M₂₃C₆ carbides; liquidus and solidus temperatures; and the pitting-resistance equivalent number (PREN). The RF model achieves consistently low prediction errors, with a PREN root-mean-square error (RMSE) of ≈0.004, and exhibits strong generalization. Shapley additive explanations (SHAP) reveal metallurgically consistent trends: increasing nitrogen (N) suppresses δ-ferrite and promotes Cr₂N; carbon (C) promotes M₂₃C₆; molybdenum (Mo) promotes the σ-phase; and C and silicon (Si) widen the freezing range. Using the trained surrogate as the objective evaluator, the non-dominated sorting genetic algorithm III (NSGA-III) builds Pareto fronts that minimize the δ-ferrite range, Cr₂N, σ-phase, M₂₃C₆ and the freezing range (ΔT) while maximizing PREN. The Technique for Order Preference by Similarity to Ideal Solution (TOPSIS) is then applied to rank the Pareto-optimal candidates and to select compositions that combine elevated PREN with controlled precipitation windows. This workflow is efficient, reproducible and interpretable and provides actionable composition candidates together with a transferable methodology for data-driven stainless steel design. Full article

Solenoid valves are widely used for pressure regulation in soft pneumatic robots, but their inherent electromechanical nonlinearities—such as dead zones, saturation, and pressure-dependent dynamics—pose significant challenges for accurate control. Conventional pulse modulation techniques, including pulse-width modulation (PWM), often exacerbate these effects by neglecting valve-switching transients. This paper presents a physics-informed dynamic modelling framework that captures transient and pressure-dependent behaviours in solenoid valve-driven soft pneumatic systems operating under pulse modulation. The model is experimentally validated on a soft pneumatic actuator (SPA) platform using four modulation schemes: PWM, integral pulse frequency modulation (IPFM), its inverted variant (IIPFM), and $\Delta$$\Sigma$ modulation. Results demonstrate that only the IIPFM scheme produces near-linear input–pressure characteristics, in close agreement with model predictions. The proposed framework provides new physical insights into valve-induced nonlinearities and establishes a systematic basis for high-fidelity modelling and control of soft pneumatic robotic systems. Full article

This paper proposes a sub-sampling phase-locked loop (SSPLL) that combines a time-to-digital converter (TDC)-free digital coarse loop with a high-gain analog SSPD fine loop. The coarse loop follows a counter-assisted, frequency-domain DPLL framework with an auxiliary FLL, enabling wide capture range and fast initial acquisition. Precise fractional-N operation without a TDC is achieved by reusing the fine loop delta–sigma modulator (DSM) and digital-to-time converter (DTC) in the coarse loop: the DSM maps the frequency control word (FCW) fraction to a variable integer sequence for integer-domain fractional synthesis, while the DTC aligns reference clock to the nearest oscillator edge to cancel DSM-induced quantization error. An LMS-based DTC gain calibration is enabled in the coarse loop, and its calibrated gain is handed off to the fine loop, stabilizing loop switching despite the narrow locking range of the SSPD. Constraining arithmetic to the integer path eliminates a need of TDC and simplifies hardware, improving area efficiency while preserving accurate frequency/phase alignment. Simulations in 28 nm CMOS over 4–5 GHz with a 104 MHz reference demonstrate 177-fs RMS jitter, −245.6 dB FoM, 0.146-mm² active area, and 8.94 mW power, validating wide capture, low in-band phase noise, and robust coarse-to-fine handover. Full article

Spiking neural networks (SNNs) provide a biologically inspired, event-driven alternative to artificial neural networks (ANNs), potentially delivering competitive accuracy at substantially lower energy. This tutorial-study offers a unified, practice-oriented assessment that combines critical review and standardized experiments. We benchmark a shallow fully connected network (FCN) on MNIST and a deeper VGG7 architecture on CIFAR-10 across multiple neuron models (leaky integrate-and-fire (LIF), sigma–delta, etc.) and input encodings (direct, rate, temporal, etc.), using supervised surrogate-gradient training implemented in Intel Lava, SLAYER, SpikingJelly, Norse, and PyTorch. Empirically, we observe a consistent but tunable trade-off between accuracy and energy. On MNIST, sigma–delta neurons with rate or sigma–delta encodings achieve 98.1% accuracy (ANN baseline: 98.23%). On CIFAR-10, sigma–delta neurons with direct input reach 83.0% accuracy at just two time steps (ANN baseline: 83.6%). A GPU-based operation-count energy proxy indicates that many SNN configurations operate below the ANN energy baseline; some frugal codes minimize energy at the cost of accuracy, whereas accuracy-oriented settings (e.g., sigma–delta with direct or rate coding) narrow the performance gap while remaining energy-conscious—yielding up to threefold efficiency compared with matched ANNs in our setup. Thresholds and the number of time steps are decisive factors: intermediate thresholds and the minimal time window that still meets accuracy targets typically maximize efficiency per joule. We distill actionable design rules—choose the neuron–encoding pair according to the application goal (accuracy-critical vs. energy-constrained) and co-tune thresholds and time steps. Finally, we outline how event-driven neuromorphic hardware can amplify these savings through sparse, local, asynchronous computation, providing a practical playbook for embedded, real-time, and sustainable AI deployments. Full article

This paper presents a low-power continuous-time delta-sigma (CT-DS) analog-to-digital converter (ADC) for use in high-sensitivity automotive-grade sub-1 GHz receivers in emerging wireless sensors network applications. The proposed ADC employs a third-order Cascade of Integrators FeedForward and Feedback (CIFF-B) loop filter operating at a sampling frequency of 150 MHz to achieve high energy efficiency and robust noise shaping. A low-noise phase-locked loop (PLL) is integrated to provide high-precision clock signals. The loop filter combines active-RC and GmC integrators with the source degeneration technique to optimize power consumption and linearity. To minimize complexity and enhance stability, a 1-bit quantizer with isolation switches and return-to-zero (RZ) digital-to-analog converters (DACs) are used in the modulator. With a 500 kHz bandwidth, the sensitivity of the receiver is −105.5 dBm. Fabricated in a 180 nm standard CMOS process, the prototype achieves a peak signal-to-noise ratio (SNR) of 76.1 dB and a signal-to-noise and distortion ratio (SNDR) of 75.3 dB, resulting in a Schreier figure of merit (FoM) of 160.7 dB based on SNDR, while consuming only 0.8 mA from a 1.8 V supply. Full article

This article presents a comprehensive modeling and simulation framework for a capacitive MEMS accelerometer integrated with a sigma-delta analog-to-digital converter (ADC), with a focus on applications in wearable health and motion monitoring devices. The accelerometer used in the system is connected to a smartphone equipped with dedicated software and will be used to assess the risk of falling, which is crucial for patients with balance disorders. The authors designed the accelerometer with special attention paid to the specification required in a system, where the acceleration is ±2 g and the frequency is 100 Hz. They investigated the sensor’s behavior in the DC, AC, and time domains, capturing both the mechanical response of the proof mass and the resulting changes in output capacitance due to external acceleration. A key component of the simulation is the implementation of a second-order sigma-delta modulator designed to digitize the small capacitance variations generated by the sensor. The Simulink model includes the complete signal path from analog input to quantization, filtering, decimation, and digital-to-analog reconstruction. By combining MEMS+ modeling with MATLAB-based system-level simulations, the workflow offers a fast and flexible alternative to traditional finite element methods and facilitates early-stage design optimization for MEMS sensor systems intended for real-world deployment. Full article

Electromagnetic interference (EMI) remains a difficult task in the design and operation of contemporary power electronic systems, especially in those applications where signal quality has a direct impact on the overall performance and efficiency. Conventional control schemes that have evolved to counteract the effects of EMI generally tend to have greater design complexity, greater error rates, poor control accuracy, and large amounts of harmonic distortion. In order to overcome these constraints, this paper introduces an intelligent and advanced control approach founded on the signal randomization principle. The suggested approach controls the switching activity of a DC–DC converter by dynamically tuned parameters like duty cycle, switching frequency, and signal modulation. A boost interleaved topology is utilized to maximize the current distribution and minimize ripple, and an innovative space vector-dithered sigma delta modulation (SV-DiSDM) scheme is proposed for cancelling harmonics via a digitalized control action. The used modulation scheme can effectively distribute the harmonic energy across a larger range of frequencies to largely eliminate EMI and boost the stability of the system. High-performance analysis is conducted by employing significant measures like total harmonic distortion (THD), switching frequency deviation, switching loss, and distortion product. Verification against conventional control models confirms the increased efficiency, less EMI, and greater signal integrity of the proposed method, and hence, it can be a viable alternative for EMI-aware power electronics applications. Full article

This paper presents a successive approximation register (SAR) and incremental sigma-delta modulator (ISDM) hybrid analog-to-digital converter (ADC) that operated at a minimum voltage supply of 0.575 V. A thorough analysis of the non-linearities caused by PVT variations and common-mode voltage (VCM) shifts in the ISDM stage is presented. The ADC employs an improved high-precision double-bootstrapped switch, and the synchronous clock is also double-bootstrapped to work under the low supply voltage. A modified merged capacitor switching (MCS) approach is presented to maintain a stable VCM at the differential input. The chip was fabricated using a 0.18 µm CMOS process, with a core area of 0.21 mm². It consumed only 0.42 µW at a 0.6 V supply and a sampling rate of 10 kS/s, which achieved an effective number of bits (ENOB) of 11.03. The resulting figure of merit (FOM_W) was 20.05 fJ/conversion-step, which is the lowest reported for ADCs of this architecture in a 0.18 µm process. Full article