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Sensors 2013, 13(3), 3014-3027; doi:10.3390/s130303014

SAD-Based Stereo Vision Machine on a System-on-Programmable-Chip (SoPC)

State Key Laboratory of Fluid Power Transmission and Control, Zhejiang University, Hangzhou 310027, China
School of Computer, Hangzhou Dianzi University, Hangzhou 310018, China
Author to whom correspondence should be addressed.
Received: 20 December 2012 / Revised: 29 January 2013 / Accepted: 26 February 2013 / Published: 4 March 2013
(This article belongs to the Section Physical Sensors)
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This paper, proposes a novel solution for a stereo vision machine based on the System-on-Programmable-Chip (SoPC) architecture. The SOPC technology provides great convenience for accessing many hardware devices such as DDRII, SSRAM, Flash, etc., by IP reuse. The system hardware is implemented in a single FPGA chip involving a 32-bit Nios II microprocessor, which is a configurable soft IP core in charge of managing the image buffer and users’ configuration data. The Sum of Absolute Differences (SAD) algorithm is used for dense disparity map computation. The circuits of the algorithmic module are modeled by the Matlab-based DSP Builder. With a set of configuration interfaces, the machine can process many different sizes of stereo pair images. The maximum image size is up to 512 K pixels. This machine is designed to focus on real time stereo vision applications. The stereo vision machine offers good performance and high efficiency in real time. Considering a hardware FPGA clock of 90 MHz, 23 frames of 640 × 480 disparity maps can be obtained in one second with 5 × 5 matching window and maximum 64 disparity pixels.
Keywords: stereo vision; system-on-programmable-chip; FPGA; disparity; SAD stereo vision; system-on-programmable-chip; FPGA; disparity; SAD
This is an open access article distributed under the Creative Commons Attribution License (CC BY 3.0).

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Zhang, X.; Chen, Z. SAD-Based Stereo Vision Machine on a System-on-Programmable-Chip (SoPC). Sensors 2013, 13, 3014-3027.

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