Resonant Rectifier ICs for Piezoelectric Energy Harvesting Using Low-Voltage Drop Diode Equivalents

Abstract

Herein, we present the design technique of a resonant rectifier for piezoelectric (PE) energy harvesting. We propose two diode equivalents to reduce the voltage drop in the rectifier operation, a minuscule-drop-diode equivalent (MDDE) and a low-drop-diode equivalent (LDDE). The diode equivalents are embedded in resonant rectifier integrated circuits (ICs), which use symmetric bias-flip to reduce the power used for charging and discharging the internal capacitance of a PE transducer. The self-startup function is supported by synchronously generating control pulses for the bias-flip from the PE transducer. Two resonant rectifier ICs, using both MDDE and LDDE, are fabricated in a 0.18 μm CMOS process and their performances are characterized under external and self-power conditions. Under the external-power condition, the rectifier using LDDE delivers an output power P_OUT of 564 μW and a rectifier output voltage V_RECT of 3.36 V with a power transfer efficiency of 68.1%. Under self-power conditions, the rectifier using MDDE delivers a P_OUT of 288 μW and a V_RECT of 2.4 V with a corresponding efficiency of 78.4%. Using the proposed bias-flip technique, the power extraction capability of the proposed rectifier is 5.9 and 3.0 times higher than that of a conventional full-bridge rectifier.

1. Introduction

There is increasing demand for autonomous sensing devices, deployed in various applications, such as medical, healthcare, and environmental monitoring [1]. To enable uninterrupted data gathering from a large population of sensing devices, e.g., the Internet of Things (IoT), a long lifetime is critical. Although there are continued innovations in battery capacity, battery lifetime is still finite. To extend the lifetime of sensing devices, energy can be acquired from ambient sources. There exist various sources from which energy can be extracted, including thermal, solar, vibrations, and wind. Among those energy sources, vibrations can provide a relatively large amount of energy through highly-efficient piezoelectric (PE) transducers.

The equivalent electrical model of a PE transducer is represented as a sinusoidal current source I_P(t) = I_Psin(ω_pt) in parallel with a capacitor C_p and a resistor R_p, where ω_p = 2πf_p is the angular frequency. In general, R_p is very large during low-frequency transducer operation, and the open-circuit voltage can be expressed as V_p = I_P/ω_pC_p. The output of a PE transducer is alternating current (AC) and, thus, needs conversion to direct current (DC). The commonly used AC-DC converters are full-bridge rectifiers (FBRs) and voltage doubler rectifiers (VDRs). Both FBR and VDR deliver a similar maximum output power when ideal diodes are used [2]. The operation of an FBR is well understood, which provides current for every half-cycle only after charging C_p to ±(V_RECT + 2V_D). Here, V_RECT is the rectified output voltage and V_D is the diode voltage drop. The VDR provides current to the output only during the positive half-cycle. In the negative half-cycle, a diode in parallel with the PE transducer provides a path to discharge C_p to the ground. During the positive half-cycle, I_P only needs to charge C_p from −V_D to (V_RECT + V_D) before current can flow into the output.

In the rectifier, a commonly used figure-of-merit is the power transfer efficiency, which is defined as the ratio of the output power P_OUT to the input power P_IN, which can be delivered by the PE transducer. Rectifying a low voltage from a PE transducer may induce significant power losses due to the diode voltage drop. An effective way to increase the efficiency of the rectifier is (1) reducing the diode’s voltage drop; and (2) increasing the input voltage by implementing the bias-flip strategy.

Figure 1 shows several reported techniques for improving the efficiency [2,3,4,5,6]. The switch-only rectifier is introduced to reduce the power to charge C_p (not delivered to output) during the negative cycle of the VDR. In this approach, a switch M₁ is shunted across the PE transducer, as shown in Figure 1a. The purpose of this switch is to discharge C_p instantaneously when I_P crosses zero. Since the switch is on at the zero crossing, the initial voltage to charge C_p starts from 0 rather than −V_D. This modification reduces the charge which is not delivered to the output and increases the extracted power.

During the period when C_p is charged, however, there is still a large portion of I_P that is not delivered to the output. The highlighted portion of I_P, shown in Figure 1a, indicates the portion of I_P, which is used to charge C_p from 0 to ±(V_RECT + 2V_D). To reduce the charge, the work in [2] introduces a bias-flip technique, shown in Figure 1b. An inductor L_P is shunted across the PE transducer through the switches realized with M₂ and M₃. When I_P crosses zero, the pulse signal V_SW briefly turns M₂ and M₃ on. At this time, the resonant loop formed by C_p and L_P flips the voltage, V_PN = V_P − V_N across the transducer. Then, the charging starts from the flip-voltage V_f rather than from 0 V. Since flipping reduces the amount needed to charge C_p from 0 to V_f, this technique increases the extracted power. However, we note that there exists power loss from the voltage drop of the two switches. In addition, the body diode of switches may be conducting for a large V_PN (This observation also applies to M₁ in Figure 1a. To reduce the voltage drop, current paths for positive and negative cycles are split [4,5,6]. Sharing a single inductor L_P as shown in Figure 1c, this approach provides two branches for the bias-flip using two diodes and two shunt switches. The transducer voltage is flipped alternatively through two paths. Then, the voltage drop by the switch is reduced from two to one, but with an additional diode voltage drop. The drawback of this approach is that the two bias-flip voltages, V_f1 and V_f2 for positive and negative cycles, respectively, are different, i.e., V_f1 ≠ V_f2. This is because the impedance at V_P and V_N seen from the flipping path is different, and we observe asymmetric flipping in the waveform. The asymmetry results in fluctuation of the extracted power and increased output ripple.

The diode voltage drop V_D existing in the rectifier loop is the third reason for the low efficiency. The V_D drop can be reduced by adding a bias voltage between the gate and drain terminal of a transistor [7]. To generate the bias voltages for a multi-stage rectifier, an extra bias distributor is required, which increases circuit complexity and the losses associated with it. In [3], an active diode, based on an op-amp with a pre-set DC offset, is used to reduce V_D and the leakage current. Another method to reduce V_D is by using a comparator-controlled switch [8]. This approach requires approximately one threshold voltage V_TH plus two overdrive voltages to power up, limiting the input voltage for start-up to 1.2 V using a 0.35 µm CMOS process. Usually, the comparator is powered up from the output storage capacitor. If there is not enough voltage to power up, the comparator will not be readily activated.

Herein, we propose two resonant rectifiers using low-voltage drop diode equivalents to overcome the limitations that exist in previous studies. We propose two diode equivalents, a minuscule-drop-diode equivalent (MDDE) and a low-drop-diode equivalent (LDDE), which effectively reduces the V_D of the rectifying stage. The diode equivalents are efficiently combined with a symmetric and low-loss resonant loop to realize the bias-flip technique. Harnessing MDDE and LDDE, two resonant rectifier integrated circuits (ICs) having self-startup capabilities are designed. To improve the efficiency under the self-power condition, the rectifier using MDDE includes synchronous bootstrap pulse generators (SBPGs). The SBPG provides boosted bias-flipping pulses that are synchronized with the frequency of the PE transducer. Two resonant rectifier ICs using both MDDE and LDDE, are fabricated in a 0.18 μm CMOS process. The rectifier using LDDE shows measured P_OUT of 564 μW under an external-powered condition with a corresponding efficiency of 68.1%. The rectifier using MDDE shows enhanced efficiency under the self-powered condition. It delivers a P_OUT of 288 μW with a corresponding efficiency of 78.4% and this result compares favorably with results from previous works.

2. Design

For an energy harvester, the capability for self-startup is one of the critical functions and several techniques have been reported [9,10,11,12]. In [9], the authors introduce a cold startup technique using a transformer. For high voltage boosting, this approach needs a transformer with a large turn ratio, which can increase the overall size of the harvester. In [10], the authors propose a mechanical switch that provides an instant power jerk to kick start the harvester. In [11], the authors present a low-voltage startup technique using a V_TH-tuned oscillator and a capacitor pass-on technique. Although a low startup voltage of 95 mV is achieved, the drawback is that this approach requires external programming of a body voltage after fabrication. In [12], a charge pump with a switched body-biasing technique is presented. Since the body terminal of a transistor is connected to a high voltage when it is turned off, the reverse leakage is effectively suppressed. In these previous works, except [11], the self-startup function, which is vital to autonomous operation, is not fully supported. In this work, we embed a simple, yet efficient, approach for self-startup into the two resonant rectifiers.

2.1. Resonant Rectifier Using LDDE

Figure 2a shows the block diagram of the resonant rectifier IC using LDDE. The rectifier consists of a three-stage voltage multiplier (VM), an oscillator (OSC), a bootstrap pulse generator (BPG), a symmetric bias-flip circuit, and a full-bridge rectifying stage. The BPG provides the bootstrapped pulse signals V_SW1 and V_SW2 for the bias-flip circuit. The clock (CLK) signal for the BPG is generated by the OSC with a frequency that can be tuned using a ring oscillator. The supply voltage of the OSC is driven by the output V_VM of the voltage multiplier shown in Figure 2b. For efficient operation, the VM uses Schottky diodes (D_V1–D_V6) realized in a standard CMOS process, which shows a low V_D of 160 mV at 1 µA [13]. Since the VM and OSC are powered from the PE transducer, the rectifier provides the self-startup function.

Figure 2c shows the schematic of the BPG which generates V_SW1 and V_SW2. The amplitudes of these signals are increased to almost 2V_VM, which provide the high overdrive voltage needed to fully turn on the switches in the bias-flip circuit, shown in Figure 2d. The bias-flip circuit consists of Schottky diodes (D_G1, D_G2), inductors (L_G1, L_G2), and transmission (T)-gate transistors (T_G1, T_G2). The T-gate is used to reduce the on-resistance of the switch [14]. The size of NMOS and PMOS transistors in the T-gate are W/L = 1000 µm/0.2 µm and 2000 µm/0.18 µm, respectively, with values optimized by using a circuit simulator. When I_P crosses zero, the bias-flip circuit changes the polarity of V_PN using two separate paths. The positive cycle uses the path formed by T_G1, L_G1, and D_G1, while the path formed by T_G2, L_G2, and D_G2 is used in the negative cycle. Inductors are bulky and expensive; the bias-flip circuit shown in Figure 2d is improved to use only one inductor (see Section 2.2).

Figure 3 shows a detailed schematic of the rectifying stage using four LDDEs. LDDE_1,3 are NMOS-based LDDEs and the LDDE_2,4 are PMOS-based LDDEs. When V_P > V_N, LDDE₁ and LDDE₄ conduct and form a closed loop. LDDE₄ consists of a main transmission transistor MP₁ and control circuit (MP₂, MN₁, and MN₂). The LDDE₁ consists of the main transistor MN₃ and control circuit (MN₄, MP₃, and MP₄). In a previous work [15], the control circuit for the LDDE is implemented using discrete bipolar junction transistors (BJTs). In this work, we remove the base current of the BJT using metal-oxide field effect transistors (MOSFETs) realized in IC technology. A voltage polarity sense circuit is formed by the diodes D_S1–D_S4 and C_S. The circuit detects the positive (V_P > V_N) and negative (V_P < V_N) cycles using four terminal voltages, V_R1, V_R2, V_C1, and V_C2. Using the four voltages, the sense circuit controls the conduction of the main transistor while blocking reverse leakage current. The voltage at nodes V_C1 and V_C2 control the conduction of LDDE₁ and LDDE₄ in the positive cycle (LDDE₂ and LDDE₃ in the negative cycle), respectively. The voltage at nodes V_R1 and V_R2 blocks reverse conduction of LDDE₄ and LDDE₁ in the negative cycle (LDDE₃ and LDDE₂ in the positive cycle), respectively.

The operation of the LDDE is described using four states, shown in Figure 3b. When I_P crosses zero from negative to positive, D_S2 and D_S4 are forward-biased forming the conducting path D_S2 – C_S – D_S4. The terminal voltages detected by the sense circuit satisfy the condition (V_C1 = V_P) > (V_R2 = V_P − V_D1) > (V_R1 = V_N + V_D1) > (V_C2 = V_N), where V_D1 is the forward voltage drop of a diode in the sense circuit. We consider four operation states for LDDE₄ as follows.

(1)

State-1: In the positive cycle when V_P > V_N, we have the condition of (V_P = V_C1) > (V_C2 = V_N). Terminal V_C2 is connected to the negative terminal V_N of the PE transducer through MN₂. Then MP₂ turns on and subsequently turns on MN₂, as well. The C_SG of MP₁ is charged by V_PN.

(2)

State-2: The source and gate terminals of MP₁ are approximately V_P and V_N + V_DS,MN2, respectively. Here, V_DS,MN2 is the drain-source voltage of MN₂. The voltage at node V_P keeps increasing. Then, MP₁ begins conducting when V_SG > |V_TH|. The voltage across C_SG of MP₁ keeps increasing and MP₁ enters the triode from the saturation mode. Using the rectifier operation, V_RECT increases. Then, the condition (V_PN − V_DS,MN2 − |V_TH|) > (V_P − V_RECT) allows MP₁ to enter the triode mode, which can be written as V_RECT > (V_N + |V_TH| + V_DS,MN2).

(3)

State-3: When the V_SD of MP₁ decreases by increasing V_RECT, it turns MP₂ off. When MP₂ is off, C_SG of MP₁ stops charging and it maintains the V_SG of MP₁. This allows MP₁ to continue conducting in the triode mode. When MP₂ is off, the gate of MN₂ has no path to conduct and, therefore, MN₂ is kept on. This state is different from the BJT version of the LDDE [15]; the base current of a BJT provides a path to discharge while the MOSFET MN₂ is kept on.

(4)

State-4: When i_p changes direction (V_P < V_N), the current direction in the sense circuit is reversed. Then, the terminal voltages detected by the sense circuit satisfy the condition (V_C2 = V_N) > (V_R1 = V_N − V_D1) > (V_R2 = V_P + V_D1) > (V_C1 = V_P). This condition turns on MN₁. By discharging the C_GD of MP₁, MN₁ subsequently turns off MP₁ to prevent reverse leakage. Since V_C2 is positive and increasing, MN₂ is turned off, which prevents the discharging of V_RECT through MN₁.

In the case of V_P < V_N, LDDE₂ and LDDE₃ conduct. During the zero-crossing of I_P from positive to negative, D_S1 and D_S3 are forward-biased, forming the conduction path D_S3–C_S–D_S1. The operation of LDDE₂ and LDDE₃ follow four states in a manner similar to that described above. As other sensor-free bias-flip rectifiers, the frequency control method of the rectifier using LDDE is not adaptive to the f_p of PE transducer. If f_p changes by aging or other reasons, the bias-flip operation may not occur at the exact zero crossing of I_P. To handle this issue, a simple yet effective frequency tracking method is implemented in the rectifier using MDDE, as explained in the next section.

2.2. Resonant Rectifier Using MDDE

Figure 4a shows the block diagram of the resonant rectifier using MDDE. The rectifier IC includes two synchronous bootstrap pulse generators (SBPGs), dual voltage doublers, a symmetric bias-flip circuit, and a rectifying stage using MDDE. Instead of using VM and OSC for frequency generation, the pulse signals V_SW1 and V_SW2 for the bias-flip circuit are directly derived from the PE transducer. For efficient bias-flipping, the V_SW1 and V_SW2 are bootstrapped by the SBPG, which is driven by the output V_DBL from a voltage doubler. The dual voltage doublers are realized using the Schottky diodes D_D1–D_D4. Without an external power supply, the SBPG and doublers are driven by the PE transducer, realizing the self-startup function.

Figure 4b shows a schematic of the SBPG. The two SBPGs operate in a complementary manner, generating two opposite phase pulse signals, V_SW1 and V_SW2. In the SBPG, V_P is compared with V_N and the output of the comparator C_MP1,2 drives the BPG. In this way, the voltages V_SW1 and V_SW2 for the bias-flip circuit are generated in sync with the f_p of the PE transducer. The comparator C_MP1,2 is realized using a differential amplifier with a latched load for increased gain. It achieves an open-loop gain of 35 dB by consuming 770 nA. Two diodes, D_C1 and D_C2, are used to prevent reverse leakage current. By the BPG, the amplitudes of V_SW1 and V_SW2 are increased by about twice that of V_DBL, which effectively flips the voltage across the nodes V_P and V_N.

To compensate the time delay between V_SW1,2 and V_PN, a delay line consisting of R_DL and C_DL is added. This allows fine tuning of the delay, which aligns the pulses V_SW1 and V_SW2 with the zero crossing of I_P. Due to the power constraint for self-startup, the values of R_DL and C_DL, which depend on transducer parameters (R_L, I_P and f_P), are externally controlled (

Table 1. Values of the delay line depending on R_L, I_P, and f_P.

fp (Hz)		200			300			400
RL (KΩ)		100	50	20	100	50	20	100	50	20
RDL (MΩ)/CDL (nF)
IP (µA)	200	8/1	8/1	10/1	8/1	8/1	8/1	8/1	8/1	8/1
	300	10/1	14/1	12/1	8/1	4/1.5	4/1.5	5/0.5	5/0.5	5/0.5
	400	10/1	14/1	14/1	8/1	8/1	5/1	8/0.5	8/0.5	3/1.2
	600	16/1	16/1	14/1	8/1.5	8/1.5	7/1.5	8/1	8/1	5/1.2

). We perform circuit simulations and the results show that the f_P from 100 to 800 Hz can be handled using this approach. The minimum delay determined by the comparator, a buffer, and BPG sets the 800 Hz as the maximum input frequency. Figure 4c shows the schematic of the bias-flip circuit and the rectifying stage using the MDDEs. To control the path for bias-flip, the Schottky diodes D_G3 and D_G4 are used. Using a single inductor L_G3, two separate and symmetric paths are created for the positive (a path along T_G4, L_G3, and D_G3) and negative (a path along T_G3, L_G3 and D_G4) cycles. Compared to the bias-flip circuit for the rectifier using LDDE, the circuit for the MDDE is improved to use one shared inductor.

Figure 5 shows the operation of the rectifying stage using MDDEs. The bridge-type stage consists of two PMOS and NMOS-based MDDEs. MDDE_2,4 are PMOS-based MDDEs, where TP₂ and TP₄ are the main transmission transistors. MDDE_1,3 are NMOS-based MDDEs, where TN₁ and TN₃ are the main transistors. The control circuit, which consists of a diode and a transistor in each MDDE, reduces the V_D of the main transistor via the deep-triode mode while blocking the reverse leakage current. In the positive cycle (V_P > V_N), MDDE₂ and MDDE₃ close the loop, as shown in Figure 5a. The diode D₂ is forward biased, which turns on N₂. At this time, the gate of TP₂ is connected to V_N through N₂, which turns on TP₂. Since V_N is negative, it also turns on P₃ and D₃. The V_SG of TP₂ is determined by the voltage at the gate (V_N + V_DS,N2) and source (V_RECT). With the condition (V_RECT − V_N − V_DS,N2) > |V_TH|, TP₂ is turned on. The V_GS of TN₃ is determined by the voltage at the gate (V_P − V_SD,P3) and source (V_RECT − V_D,RL), where V_SD,P3 and V_D,RL are the source-drain voltage of P₃ and the voltage drop across R_L, respectively. With the condition (V_P − V_SD,P3 − V_RECT + V_D,RL) > V_TH, the TN₃ connects between V_N and V_RECT, closing the loop.

Next, we find the condition for TP₂ and TN₃ to operate in triode mode. In TP₂, we observe that the source-drain voltage is V_RECT − V_P and the source-gate voltage is V_RECT − (V_N + V_DS,N2). Therefore, the condition V_PN >> (|V_TH| + V_DS,N2) allows deep-triode operation of TP₂. For TN₃, we observe that the drain-source voltage is V_N − (V_RECT − V_D,RL) and the gate-source voltage is (V_P − V_SD,P3) − (V_RECT − V_D,RL). Then, the condition V_PN >> (V_TH + V_SD,P3) allows deep-triode mode operation for TN₂. In the negative cycle (V_P < V_N), D₂ and D₃ are reverse biased, and the voltage at the source terminal of N₂ is V_N > 0 (for P₃, it is V_P < 0). Therefore, both N₂ and P₃ are kept off and the reverse leakage through TP₂ and TN₃ is blocked. The operation of MDDE₁ and MDDE₄ in the negative cycle (V_P < V_N) can be similarly described, as shown in Figure 5b.

Figure 6 shows the comparison of V_D of the LDDE and MDDE as a function of I_P. The two R_L values and the size of the main transistor are chosen to match the result in [15]. Since the control circuit does not fully turn on with small I_P values, the results show that the V_D of both diode equivalents increases in the small I_P range from 20 to 40 µA. When I_P increases above 60 µA, V_D increases with I_P. The LDDE has a narrow window in the I_P range from 30 to 40 µA. In the case of MDDE, the V_D is below 50 mV in the I_P range from 30 to 60 µA. In order to investigate the performance for different PE transducer parameters, Figure 6b shows the comparison of V_D of the LDDE and MDDE for the different periphery. For a PE transducer having I_P = 600 µA, the V_D is 230 mV and 360 mV in case of MDDE and LDDE having the same size, respectively. The results show that the MDDE shows an overall smaller V_D than that of the LDDE over a broad range of I_P. The LDDE use three extra transistors to control the on-resistance of the main conducting transistor. In the case of the MDDE, the control is achieved using a transistor and a diode, which makes it simple, with a low loss.

2.3. Loss Calculation

Figure 7 shows the key waveforms of the resonant rectifier. When the PE element starts providing I_P, the rectifier enters a startup state. In this state, the BPG starts generating V_SW1 and V_SW2, which have amplitudes that increase with V_PN. A steady-state is assumed after t₁. Just before time t₁, C_p is pre-recharged to −(V_RECT + 2V_D). At time t₁, I_P changes direction and the bias-flip operation allows the charging of C_p from V_f to (V_RECT + 2V_D) until t₂. During this period, the output current I_o starts flowing to the load. In the negative cycle, C_p is discharged from −V_f to −(V_RECT + 2V_D). The effectiveness of bias-flip is usually expressed using a flipping efficiency η_f, defined as:

$${\eta }_f=\frac{V_f+V_{RECT}}{2V_{RECT}}$$

(1)

The amount of charge Q_Cp lost due to charging C_p during time interval [t₁, t₂] can be expressed as:

$$Q_{Cp}=[V_{RECT}+2V_D-V_f]C_p=[V_{RECT}+2V_D-V_{RECT}(2{\eta }_f-1)]C_p$$

(2)

Next, we consider the charge lost across R_p in the time interval [t₁, t_π]. Since V_PN varies during the time interval, we consider two cases of charge losses, Q_Rp1 during [t₁, t₂] and Q_Rp2 during [t₂, t_π], given by:

$$Q_{Rp}=Q_{Rp1}+Q_{Rp2}={\displaystyle {\int }_{t1}^{t2}\frac{V_{PN}(t)}{R_p}dt+}{\displaystyle {\int }_{t2}^{t\pi }\frac{V_{PN}(t)}{R_p}dt}$$

(3)

During the time interval [t₁, t₂], V_f is inverted via a bias-flip. In this period, V_PN(t) can be obtained by integrating I_P(t) as:

$$V_{PN}(t)=\frac{1}{C_p}{\displaystyle {\int }_{t1}^t{I}_p\sin \omega tdt}-V_f(t_1)=\frac{I_p}{\omega C_p}(\cos \omega t_1-\cos \omega t)-V_f(t_1)$$

(4)

Applying the boundary conditions $V_f=V_{RECT}(2{\eta }_f-1)$ and ωt₁ ≅ 0, Equation (4) can be expressed as:

$$V_{PN}(t)=V_p(1-\cos \omega t)-V_{RECT}(2{\eta }_f-1)$$

(5)

where V_P = I_P/(ω_pC_p) is the open-circuit voltage. Using Equation (5), Q_Rp1 is obtained as:

$$Q_{Rp1}={\displaystyle {\int }_{t1}^{t2}\frac{V_p(1-\cos \omega t)-V_{RECT}(2{\eta }_f-1)}{R_p}dt}\cong \frac{V_p}{\omega R_p}(\omega t_2-\sin \omega t_2)-\frac{V_{RECT}}{\omega R_p}(2{\eta }_f-1)\omega t_2$$

(6)

To find Q_Rp2 during the time interval [t₂, t_π], we need the value of ωt₂ and, thus, use the following relationship:

$$I_p\sin \omega t=C_p\frac{d{V}_p}{dt}=\omega C_p\frac{d{V}_p}{d\omega t}$$

(7)

Integrating Equation (7) over the time interval [t₁, t₂] when bias-flipping is performed, we obtain:

$$V_p(-\cos \omega t_2+\cos \omega t_1)=V_p(t_2)-V_p(t_1)$$

(8)

The values of V_p can be obtained from the waveform, which are $V_p(t_1)=V_f$ and $V_p(t_2)=(V_{RECT}+2V_D)$. Then, Equation (8) can be written as:

$$t_2=\frac{1}{\omega }{\cos }^{-1}(\frac{V_p-2V_{RECT}-2V_D+V_{RECT}2{\eta }_f}{V_p})$$

(9)

Using Equation (9), Q_Rp2 is obtained as:

$$Q_{Rp2}=\frac{(V_{RECT}+2V_D)}{R_p}(t_{\pi }-t_2)$$

(10)

where $t_{\pi }=\pi /\omega$.

The total charge produced by the PE transducer in every cycle is given by:

$$Q_{total}=2I_p/\omega =2C_p{V}_p$$

(11)

The theoretical extracted power P_OUT,calc from the PE transducer for every cycle is obtained by taking the available charge Equation (11) minus the various loss terms given by Equations (2), (6) and (10):

$$\begin{array}{l}{P}_{\text{OUT,calc}}=2f_p{V}_{RECT}(Q_{total}-Q_{Cp}-Q_{Rp1}-Q_{Rp2})\\ =2f_p{V}_{RECT}\{[2V_p{C}_p-[V_{RECT}+2V_D-V_{RECT}(2{\eta }_f-1)]C_p-[\frac{V_p}{\omega R_p}(\omega t_2-\sin \omega t_2)-\frac{V_{RECT}}{\omega R_p}\\ (2{\eta }_f-1)\omega t_2]-[\frac{V_{RECT}+2V_D}{R_p}(t_{\pi }-t_2)]\}\end{array}$$

(12)

3. Measured Results

The proposed rectifiers are fabricated in a one-poly six-metal 0.18 µm CMOS process with a top 2 µm thick metal option. Figure 8 shows the chip microphotographs. The size of the rectifiers using LDDE and MDDE are 0.26 mm × 0.19 mm and 0.51 mm × 0.46 mm, respectively. Figure 9 shows the experimental setup to characterize the rectifier using the PE transducer.

The bimorph of the transducer has a thickness, a length and a width of 0.33, 75, and 20 mm, respectively [16]. Each layer consists of a stainless steel (SUS) plate, a piezo ceramic, and an Ag electrode. The PE transducer is mounted on a vibrating motor for mechanical excitement [17]. The transducer is excited using 200 Hz with an acceleration of 1.8 g. Under this condition, the theoretical optimum loading resistance of the PE transducer is 7.2 kΩ. Two wires attached to both sides of the transducer are interfaced with a test board containing the rectifiers.

Table 2. Parameters for the experiment.

Parameters	Value
fp Cp	200 Hz 110 nF
Rp	1 MΩ
LG1, LG2, LG3	1000 µH
CL	1 µF
RL	10–200 KΩ

shows the parameters used for the experiment. The value of the inductor for bias-flip is selected considering the trade-off between size and the Q-factor. The maximum current available from the transducer is 600 µA, which corresponds to V_p = 4.34 V at 200 Hz. The equivalent circuit of a PE transducer can be represented as a mechanical spring-mass coupled to an electrical circuit. The current in the primary mechanical side corresponds to proof mass relative velocity, which is determined by such parameters as PE material, dimension, and acceleration. By the electromechanical coupling factor, which describes the effectiveness of the conversion from mechanical to electrical energies, the maximum current is determined.

Figure 10 shows the measured result of the rectifier using LDDE. It shows the input voltage V_PN, bootstrap pulse signals V_SW1 and V_SW2, and the output V_RECT. The transient during self-startup is shown in the inset. When V_PN is increased, the BPG starts generating V_SW1 and V_SW2. Then, V_RECT starts increasing and the steady-state condition is reached at about 20 s. After this time, V_SW1 and V_SW2 reach a value about twice that of the multiplier output and fully turn on the bias-flip circuit.

Figure 11 shows the measured and calculated P_OUT and efficiency versus V_RECT. We characterize the rectifier under external and self-power conditions. When it is externally powered, the VM provides power only to the BPG and the internal oscillator is turned off. The CLK frequency is supplied externally to match the f_p of the PE transducer. By receiving the CLK, the BPG generates V_SW1 and V_SW2. The V_RECT is measured with I_P = 600 µA. Since V_RECT depends on R_L, it is varied from 10 to 200 kΩ, searching for an optimum value. When V_RECT reaches 3.36 V, the measured peak P_OUT of 564 µW is achieved with an R_L of 20 kΩ. The P_OUT,calc obtained using Equation (12) is 626 µW, which indicates that the power consumed by the control circuit is 62 µW. The maximum input power which can be delivered by the PE transducer is obtained as P_IN = 2 C_pf_p(V_p)² = 828 µW. Using the definition for power transfer efficiency = P_OUT/P_IN, we obtain 68.1%. Using the measured V_f of 1.53 V in Equation (1), a flipping efficiency η_f of 72.8% is achieved. Under the same PE input condition and with V_D = 0.7 V, the maximum power that can be obtained using the FBR [2] is 190 µW. The results show that the rectifier using LDDE delivers three times higher P_OUT than that of the FBR.

Under the self-power condition, a resistive voltage divider is placed at the output of the VM. The role of the divider is controlling the supply voltage of OSC, which determines the CLK. The voltage divider is tuned so that the CLK frequency is closely matched to the f_p of PE transducer. The results show a P_OUT of 261 µW with a V_RECT of 2.8 V.

Figure 12 shows the measured waveform of the rectifier using MDDE. The result shows the initial transient waveform during self-startup. When V_PN starts increasing, the SBPG generates pulses for the bias-flip. After the steady-state condition is reached at about 2 s, V_PN flips abruptly. Figure 13 shows the measured and calculated P_OUT and efficiency versus V_RECT for two cases: I_P = 600 µA and 400 µA. The rectifier is characterized by varying R_L from 10 to 200 kΩ to find an optimum condition. Using I_P = 400 µA, a peak P_OUT of 288 µW and a V_RECT of 2.4 V are extracted with an R_L of 20 kΩ, which corresponds to an efficiency of 78.4%. The P_OUT,_calc obtained using Equation (12) is 386 µW, which indicates that the additional loss and control power is 98 µW. Since P_OUT depends on the PE transducer characteristics and the mechanical vibration [18,19], it is difficult to directly compare P_OUT performance (See

Table 3. Performance comparison with previous works.

	This Work		[2]	[3]	[21]	[22]	[23]	[24]
	Rectifier (MDDE)	Rectifier (LDDE)
Tech.	0.18 μm		0.35 μm	0.18 μm	0.18 μm	0.35 μm	0.35 μm	0.25 μm
Type	Bias-flip/diode equivalent		Bias-flip	Active FBR	S-SSHI	Energy Invest	Inductor-less	SSHI
VP (V)	2.89	4.34	2.8	2.8	2.2	2.6	2.5	4.9
f0 (Hz)	200		225	200	200	143	82	144
PE transducer	Thrive K7520BP2		V22B Mide	Circuit model	Circuit model	V22B Mide	V22W Mide	V22B Mide
Self-power	Y	N	N	N	Y	N	N	Y
VRECT (V)	2.4	3.36	3.2	2.78	3.6	3.7	1.0	3.9
POUT (μW)	288	564	53	81	74	52	35	136
Efficiency (%)	78.4	68.1	58	90	89.5	69	77	85

). However, the conventional FBR can be used as a common reference. Under the same conditions, the maximum power that can be obtained using the FBR is 48.8 µW. The results show that the rectifier using MDDE delivers 5.9 times higher P_OUT than that of the FBR. Using I_P = 600 µA, a P_OUT of 441 µW is extracted with a V_RECT of 2.1 V using an R_L of 10 kΩ. The result shows that efficiency is reduced when I_P is increased from 400 to 600 µA. This is related to the narrow working window where V_D is increased with I_P (See Figure 6).

Table 3 shows a performance comparison with previous works realized using IC technology. The work in [2] presents a resonant rectifier using the bias-flip technique. The bias-flip timing is controlled by a digital inverter delay line that can be programmed externally. Although the adjustable delay control provides flexibility to accommodate various PE transducers, self-startup is not supported. Further, the efficiency of 58% is rather low, which can be attributed to the voltage drop in bias-flip switches and rectifying stages. In [4], a passive differentiator is used to detect the I_P polarity change. In this work, two separate paths are used to reduce the voltage drop for bias-flip. A relatively high P_OUT of 1230 µW is achieved under externally-powered conditions. The work in [6] proposes a parallel synchronized switch harvesting on inductor (P-SSHI) technique which extracts 48 µW. The result in [20] shows a high efficiency of 91%. Including [20], however, the results in [4,6] are based on discrete realization and not included for comparison.

The work in [21] presents a series synchronized switch harvesting on inductor (S-SSHI) technique, which is applied to the conventional FBR. It shows a good efficiency of 89.5%. However, the results in [3,21] are obtained using an equivalent model of the PE transducer, therefore, its performance in a real environment is unknown. The work in [22] increases power extraction by investing energy from the battery to enhance the electromechanical coupling factor. The work in [23] presents a fully-integrated interface to a PE transducer which does not employ an inductor. By dynamically switching between parallel and series configurations of two PE transducers, this work achieves a peak efficiency of 77%. The work in [24] inserts an active diode in the resonant loop of the SSHI circuit which allows bias-flipping to occur at an optimal time without the need for complicated delay-tuning circuits. In the proposed rectifier using LDDE, we achieve an efficiency of 68.1% under the external-power condition. Under the self-power condition, the rectifier using MDDE delivers a P_OUT of 288 µW and a V_RECT of 2.4 V. This corresponds to an efficiency of 78.4%. Although this efficiency number is lower than the results of [24], a P_OUT of 441 µW is extracted using I_P = 600 µA, demonstrating the high power extraction capability of the proposed work. The results indicate the improvement is achieved using efficient bias-flipping with a low V_D of the MDDE.

4. Conclusions

In this work, we presented an efficient rectifier design technique for PE energy harvesting. To reduce the voltage drop in the rectifier, two diode equivalents are proposed. The diode equivalents are successfully embedded in two resonant rectifiers using the symmetric bias-flip technique. In addition, time synchronization of the bias-flip with the PE transducer is studied. Further, we propose a self-power boosted pulse generator that synchronously detects the zero crossing transition of the PE transducer. The measured results show that the proposed rectifiers significantly increase the extracted power and efficiency. The rectifier using LDDE delivers a P_OUT of 564 µW with a corresponding efficiency of 68.2%. The rectifier using MDDE delivers a P_OUT of 288 μW with a peak efficiency of 78.4%. Compared to the conventional FBR, these results show that the rectifier using MDDE and LDDE achieves a power extraction capability enhanced by factors of 5.9 and three times, respectively. The results indicate that an improvement is achieved with the proposed diode equivalents. This result can play a valuable role in various sensing applications that demand energy harvesting to obtain auxiliary power for extended battery lifetime.