Power Factor Corrector with Bridgeless Flyback Converter for DC Loads Applications

Abstract

Since power systems with a DC distribution method has many advantages, such as conversion efficiency increase of about 5–10%, cost reducing by about 15–20% and so on, the AC distribution power system will be replaced by a DC distribution one. This paper presents a DC load power system for a DC distribution application. The proposed power system includes two converters: DC/DC converter with battery source and power factor corrector (PFC) with a line source to increase the reliability of the power system when renewable energy or energy storage equipment are adopted. The proposed PFC adopts a bridgeless flyback converter to achieve power factor correction for supplying power to DC loads. When the bridgeless flyback converter is used to achieve PFC, it needs two transformers to process positive and negative half periods, respectively. In order to increase conversion efficiency, the flyback one can add two sets of the active clamp circuit to recover energies stored in leakage inductances of transformers in the converter. Therefore, the proposed bridgeless flyback converter can not only integrate two transformers into a single transformer, but also share a clamp capacitor to achieve energy recovery of leakage inductances and to operate switches with zero-voltage switching (ZVS) at the turn-on transition. With this approach, the proposed converter can increase conversion efficiency and decrease component counts, where it results in a higher conversion efficiency, lower cost, easier design and so on. Finally, a prototype with a universal input voltage source (AC 90–265 V) under output voltage of 48 V and maximum output power of 300 W has been implemented to verify the feasibility of the proposed bridgeless flyback converter. Furthermore, the proposed power system can be operated at different cases among load power P_L, output power P_DC1 of DC/DC converter and output power P_DC2 of the proposed PFC for supplying power to DC loads.

1. Introduction

Since power systems with a DC distribution method has many advantages, such as conversion efficiency increase of about 5–10%, cost reducing by about 15–20% and so on, the AC distribution power system will be replaced by a DC distribution one [1]. Figure 1 shows a block diagram of a power system for DC load applications. The power sources of the power system can adopt utility line, solar arrays, battery or wind turbine, etc. The power system using a power processor is widely applied to the general electrical or electronic equipment. In order to obtain a lighter weight and a smaller volume, a switching-mode converter is regarded as the power processor of the power system. When a power factor corrector (PFC) is used for the AC/DC power system [2,3,4,5,6,7,8,9,10,11,12] to protect the line source from harmonic current pollution, it has to meet the recommended limits of harmonics in supply current by various international power quality standards, such as the International Electrotechnical Commission (IEC) 61000-3-2 [2]. Therefore, the AC/DC converter adopts PFC techniques to increase power factor (PF), in which input voltage waveform can be made to be completely in phase with the input current one, implying approximately unity power factor.

In general, a boost converter, as shown in Figure 2, or buck-boost converter is adopted in the PFC system. In order to reduce the conduction losses of diodes, a bridgeless boost converter is adopted to achieve a higher power factor, as shown in Figure 3. Due to the universal input voltage source (AC 90–265 V), its output voltage is regulated at approximately 400 V. For a power system under a lower level output voltage condition, it needs an extra DC/DC converter as a step-down converter. Therefore, the topology of two stages is used to achieve a lower output voltage, resulting in a higher cost and a lower conversion efficiency. Single stage topology with buck-boost converter has been an alternative solution in various power conversions. In order to further increase the step-down ratio, a bridgeless flyback converter is regarded as the power processor because of its topological advantages, such as simple circuit structure, low cost, and galvanic isolation, as depicted in Figure 4. It is adopted in not only low power isolated single-stage single-phase AC/DC converters which is regarded as the front end of the switching-mode power supply, but also uninterrupted power supplies (UPS), induction heating, electronic ballast, telecom power supplies, light emitting diode drivers [13,14,15], etc.

Since a flyback converter adopts a transformer to be regarded as a stored inductor and an isolated transformer, a leakage inductance exists in the primary side, resulting in a higher voltage stress across switches of the converter when switches are turned off. In order to limit a high voltage stress across switches, a resistor-capacitor-diode (RCD) clamp circuit is used to reduce switch voltage spike. Although the RCD circuit can smooth out the voltage spike, the energy stored in leakage inductance is released to the clamp resistor. As a result, the conversion efficiency of the flyback converter does not increase. For improving conversion efficiency of the one with the RCD clamp circuit, an active clamp circuit is used to replace the RCD clamp circuit, as shown in Figure 5. With this approach, the energy stored in leakage inductance can be recycled and switches in the converter can be operated with zero-voltage switching (ZVS) at the turn-on transition [16,17].

When the PFC adopts a bridgeless flyback converter, it needs to process power in a positive and negative half periods of the line source, resulting in that its component counts almost need twofold of its counterpart circuit [18,19]. Particularly, using more than one magnetic device in the bridgeless flyback converter impacts the advantage, which is the circuit simplicity. In order to further simplify the circuit structure, two transformers in the bridgeless flyback converter is replaced with a three-winding transformer, as illustrated in Figure 6. Furthermore, two active clamp circuits share a capacitor. It will reduce weight, volume and component counts, significantly.

This paper proposes a bridgeless flyback converter, illustrating that the proposed one is without bridge diodes to remove the diode conduction loss and increase conversion efficiency. In addition, the proposed one adopts a three-winding transformer to substitute for two transformers. When the output maximum power of the proposed bridgeless flyback is the same as that of the conventional bridgeless flyback converter, as shown in Figure 5, its maximum input current I_i is also the same as each other, and maximum working flux B_pk of the transformer in the proposed converter is also the same as that in the conventional bridgeless flyback converter. Figure 7 shows a B-H curve of the transformer T_r in the flyback converter. Since the conventional flyback converter uses a bridge rectifier to rectify input current I_i, the rectified input current I_i can be obtained by a positive value during a complete switching cycle. Its B-H curve is illustrated in Figure 7a. As a result, the conventional flyback converter can use a set of transformers to implement PFC function. While, the bridgeless flyback converter, as shown in Figure 5, needs two sets of transformers to process energy under the positive half period and the negative half period. Its B-H curve is illustrated in Figure 7b. Due to the proposed bridgeless flyback converter with a three-winding transformer, its B-H curve is the same as the conventional flyback one, as shown in Figure 7a. Therefore, the proposed bridgeless converter can save a set of transformers. It can simplify the circuit structure, significantly. Therefore, the proposed bridgeless flyback converter for the PFC power system can achieve a higher power factor to avoid the line source from harmonic pollution, possesses soft-switching features in which switches are operated in ZVS at turn-on transition to increase conversion efficiency. It is suitable for a low power level application. This paper focuses on design and analysis of the proposed bridgeless flyback converter and power management for DC loads of power system.

2. Control Algorithm of the Proposed System for DC Load Applications

The proposed bridgeless PFC is applied to a DC load power system. In order to implement a DC load power system, the proposed one and a DC/DC converter with a battery source connected in parallel to supply power for DC loads. Its block diagram is shown in Figure 8. The control algorithm of the proposed power system for DC load applications is described in the following sections.

1. Circuit Topology of the Proposed Power System

The proposed DC load power system consists of a DC/DC converter with a battery source and a bridgeless PFC and single-chip control circuit. The output voltage V_DC2 of the bridgeless PFC is close to and is greater than the output voltage V_DC1 of the DC/DC converter. Therefore, the diode D_B is used to block the voltage difference between voltages V_DC2 and V_DC1. The DC load R_L is supplied power from the proposed PFC and the DC/DC converter. When the load power P_L is less than or equal to P_DC2(max) which is the maximum output power of the proposed PFC, the proposed PFC supplies power to load. If P_L is greater than P_DC2(max), the proposed PFC and the DC/DC converter supply power to load for achieving a DC load power system.

2. Control Algorithm of Each Unit

● DC/DC converter

The DC/DC converter adopts a boost converter with a single-capacitor snubber [20]. It can transfer power from the battery to load. Since its output voltage V_DC1 is less than the voltage V_DC2, a diode D_B is used to protect the DC/DC converter. Therefore, the protection diode with the output diode of boost converter is replaced by the extra diode D_B. If the operational state is in the 0 < P_L ≤ P_DC2(max) state, the battery with the DC/DC converter can be operated in the charging mode. It needs an extra charger to charge the battery. When the proposed power system is operated in an abnormal state, the single-chip control circuit sends a shutdown signal S_D1 under a high level to the pulse width modulation (PWM) control circuit of the DC/DC converter. The DC/DC converter can be operated in the shutdown state to protect the DC/DC one.

● The Proposed PFC

The proposed PFC uses a bridgeless flyback converter which is regarded as a power factor corrector for increasing power factor between input voltage and input current of a line source. Its control circuit adopts a PWM IC for PFC control. Figure 9 illustrates conceptual waveforms of voltage V_C1 and current I_D1. Variation of current I_D1 follows the sine waveform of input voltage V_C1. Figure 9a shows concept waveforms under a complete line period, while Figure 9b depicts those waveforms under a positive half period. From Figure 9b, it can be seen that the proposed flyback converter can be operated in discontinuous conduction mode (DCM) or continuous conduction mode (CCM) under a positive half period. When the proposed one is operated in the A and C areas, inductor current I_LK is in the DCM state due to a lower voltage level of input voltage V_C1. If input voltage V_C1 is during the B area interval, the proposed converter is operated in CCM. According to the operational method of the proposed one as mentioned above, input voltage V_in and current I_i are in phase. Therefore, the proposed flyback converter can increase PF and reduce total harmonic distortion (THD).

In Figure 8, when output current I_DC2 of the proposed PFC is less than or is equal to the maximum output current I_DC2(max), the output feedback voltage V_F is equal V_DC2 (diode D_P1 is forward biased). The proposed PFC is operated as the voltage regulator. If I_DC2 is greater than I_DC2(max), the output current I_DC2 is regulated at I_DC2(max). That is, the proposed one is operated as the current regulator. The voltage V_F is equal to I_DC2(max) and the diode D_P2 is in the forwardly bias state. In addition, when the proposed power system has an abnormal operational condition, the shutdown signal voltage S_D2 is changed from a low level to a high level. The proposed PFC is shut down to protect the proposed one.

3. Single-Chip Control Circuit

The single-chip control circuit includes three units: The battery protection unit, line source protection unit and output protection unit. According to the operational relationships between DC/DC converter and the proposed PFC, the operational cases are divided into four cases, as listed in

Table 1. Operational conditions of the proposed power system for DC load applications.

Cases	Power Distribution		Operational Conditions
	DC/DC Converter with Battery Source	The Proposed PFC	DC/DC Converter with Battery Source	The Proposed PFC
PL = 0 W	PB = 0 W	PDC2 = 0 W	shutdown	shutdown
0 < PL ≤ PDC2(max)	PB = 0 W	PDC2 = PL	work	work
PDC2(max) < PL ≤ PDC2(max) + PB(max)	PB = PL − PDC2(max)	PDC2 = PDC2(max)	work	work
PL > PDC2(max) + PB(max)	PB = 0 W	PDC2 = 0 W	shutdown	shutdown

. Symbol definition of the proposed power system is listed in

Table 2. Symbol definition of the proposed power system for DC load applications.

Symbol	Definition	Expression
PB	Output power of the DC/DC converter with battery source	PB = VBIB
PL	Load power	PL = VDCIDC
IDC2	Output current of the proposed PFC	IDC2 ≤ IDC2(max)
IDC2(max)	Output maximum current of the proposed PFC	-
VB	Voltage of battery	VB ≥ VB(min)
VB(min)	The minimum work voltage of battery	-
IB	Discharge current of battery	IB ≤ IB(max)
IB(max)	The maximum discharge current of battery	-
PB(max)	The maximum output power of battery	PB(max) = VBIB(max)
Vi	Input voltage of the line source	-
Vi(min)	The minimum input voltage of the line source	Vi(min) < AC 90 V
Ii	Input current of the line source	Ii ≤ Ii(max)
Ii(max)	The maximum work current of the line source	-
VDC	Output voltage of the proposed power system	-
IDC	Output current of the proposed power system	IDC ≤ IDC(max)
IDC(max)	Output maximum current of the proposed power system	-
PDC2(max)	The maximum output power of the proposed PFC	PDC2(max) = VDC2IDC2(max)
PDC2	Output power of the proposed PFC	PDC2 = VDC2IDC2

. Their operational conditions are described in the following section.

● Case I: P_L = 0 W

When P_L = 0 W, the DC/DC converter with battery source and the proposed PFC are operated in the shutdown mode.

● Case II: 0 < P_L ≤ P_DC2(max)

When 0 < P_L ≤ P_DC2(max), P_B = 0 W and P_DC2 = P_L. The DC/DC converter with battery source and the proposed PFC with line source are operated in the working state.

● Case III: P_DC2(max) < P_L ≤ P_DC2(max) + P_B(max)

When P_DC2(max) < P_L ≤ P_DC2(max) + P_B(max), P_DC2 = P_DC2(max) and P_B = P_L − P_DC2(max). The DC/DC converter and the proposed PFC are in the working state.

● Case IV: P_L > P_DC2(max) + P_B(max)

When P_L > P_DC2(max) + P_B(max), the proposed power system is operated in the over-load state. Therefore, the DC/DC converter and the proposed PFC are in the shutdown state.

There are three protection units in the proposed power system: Battery protection, line source protection and output protection units. In order to increase protections of the proposed power system, hardware and software methods are adopted to protect the proposed one. Due to the same protection functions between hardware and software methods, the operation of hardware protection circuit is introduced in this paper. Figure 10 shows a block diagram of the single chip control circuit for the hardware protection circuit. In the battery protection unit, when I_B > I_B(max), the discharging current I_B is in the over-current state. Voltage V_B1 is changed from a low level to a high level. Voltage S_D1 is equal to V_S1 (=V_B1). The DC/DC converter is shut down to protect the battery. If V_B < V_B(min), the battery is in the under-voltage state. Voltage single V_B2 is changed from a low level to a high level, and signal S_D1 is the same as V_S1 (=V_B2). Therefore, the DC/DC converter is also shut down.

In the line source protection unit, when V_i < V_i(min) (=AC 90 V), the proposed PFC is shut down by S_D2. In this case, the line source is in the under-voltage state, and voltage signal V_i1 varies from a low level to a high level. Since V_i1 = V_S3 = S_D2, the proposed PFC is shut down by signal S_D2, which is in a high level state. If I_i > I_i(max), the signal V_i2 is equal to V_S3 (=S_D2), and V_i2 is in a high level state. The proposed PFC is operated in the over-current state and it is shut down by S_D2. In the output protection unit, there are two cases to protect the proposed power system. One is that output voltage is in the under-voltage state. The other one is that output current is in the over-current state. When two protection cases occur, the proposed power system is shut down. In the under voltage state, V_DC < V_DC(min), voltage V_D1 = V_S2 = S_D1 = V_S4 = S_D2 is changed from a low level to a high level to shut down the proposed one. When I_DC > I_DC(set), voltage V_D2 = V_S2 = S_D1 = V_S4 = S_D2 is varied from a low level to a high level. The proposed one is shut down. Therefore, the proposed power system can use the battery protection unit, line source protection unit and output protection unit to avoid the abnormal operational condition in the proposed power system.

3. Operational Principle of the Proposed PFC

The proposed bridgeless flyback converter uses a three-winding transformer to achieve operations of the positive and negative half periods of the line source, as depicted in Figure 6. Its equivalent circuit is illustrated in Figure 11a,b, respectively. When the line source enters the positive half period, switches M₁ and M₂ are operated in complementary. During this time interval, switches M₃ and M₄ are always turned off, as shown in Figure 11a. The input energy supplied by the line source is transferred to load through windings N₁ and N₃ of the transformer. Furthermore, when the proposed converter is operated in the negative half period, switches M₁ and M₂ are turned off and switches M₃ and M₄, in turn, are operated in complementary, as depicted in Figure 11b.

The operational principle of the proposed flyback converter is divided into two different half periods: Positive and negative half periods. According to operational principle of equivalent circuit shown in Figure 11a,b, operational modes of the proposed one operated in the positive period are similar to those modes in the negative period, except that switches M₁ and M₂ are changed to switches M₃ and M₄. Furthermore, since the period T_l of the line source is much greater than T_s of switching converter, the input voltage is regarded as a constant value during each switching period T_s. Therefore, the operational principle of the proposed bridgeless flyback converter can adopt, that input voltage is a constant DC voltage and the proposed one is operated in the positive half period of the line source, to explain its operational principle. According to the operational principle of the proposed converter, operational modes of the proposed one are divided into seven modes. Each operational mode is shown in Figure 12 over one switching cycle, and its key waveforms are illustrated in Figure 13. Its operational principle is described in the following.

• Mode 1 [Figure 12a; t₀ ≤ t < t₁]: Before t₀, switch M₁ is kept in the turn-on state, while M₂ is in the turn-off state. When t = t₀, current I_DS1 of switch M₁ reaches to the initial current which is the minimum inductor current I_L(0) of the proposed converter operated in continuous conduction mode (CCM). Within this time interval, the inductor current I_LK linearly increases and current I_DS1 is equal to I_LK. Since the diode D₂ is reverse biased, the capacitor C_o supplies the load with energy. In this interval, inductance L_m1 is in the stored energy state.
• Mode 2 [Figure 12b; t₁ ≤ t < t₂]: At t = t₁, switch M₁ is turned off and M₂ is operated in the off state. The energies stored in leakage inductor L_k and magnetizing inductor L_m1 are transferred to capacitors C_M1 and C_M2. Voltage V_DS1 across switch M₁ is charged from 0V to (V_in + V_o/N) and voltage V_DS2 across switch M₂ is charged from (V_in + V_o/N) to 0 V. Since the charge time is very small, capacitor C_M1 is in an approximately linear charging state and C_M2 is in an approximately linear discharging state. The output capacitor C_o maintains output voltage V_o at a desired value.
• Mode 3 [Figure 12c; t₂ ≤ t < t₃]: When t = t₂, switch voltage V_DS1 is equal to (V_in + V_o/N) and V_DS2 equals to 0 V. Diode D₂ and D_M2 starts to forwardly bias. Voltage of secondary winding in transformer T_r is clamped to output voltage V_o. Within this time interval, inductance L_k and capacitor C_c are in a resonant manner. Furthermore, magnetizing inductor L_m1 releases the energy through transformer T_r to load.
• Mode 4 [Figure 12d; t₃ ≤ t < t₄]: At t₃, switch M₂ is turned on and switch M₁ is kept in the off state. Since the body diode D_M2 is forward biased before switch M₂ is turned on, switch M₂ is operated with ZVS at turn-on transition. Inductance L_k and capacitor C_c are kept in the resonant state. The energy stored in L_m1 is transferred to load by means of transformer T_r.
• Mode 5 [Figure 12e; t₄ ≤ t < t₅]: When t = t₄, switch M₂ is turned off. A new resonant network is formed between inductance L_k and capacitors C_M1 and C_M2. Capacitor C_M1 is discharged and C_M2 is charged through inductance L_k. As a sequence, switch voltage V_DS2 changes from 0 V to (V_in + V_o/N), while V_DS1 varies from (V_in + V_o/N) to 0 V. Magnetizing inductance L_m1 is in the released energy state. Diode D₂ maintains in the forwardly bias state.
• Mode 6 [Figure 12f; t₅ ≤ t < t₆]: At t₅, switch voltage V_DS1 is equal to 0 V. Inductance current I_Lk equals a negative value. Voltage across inductance L_k is equal to (V_in + V_o/N). The operational states of magnetizing inductance L_m1 and diode D₂ are the same as those states of mode 5.
• Mode 7 [Figure 12g; t₆ ≤ t < t₇]: When t = t₆, switch M₁ is turned on. Since body diode D_M1 is forward biased before t = t₆, switch M₁ is operated with ZVS at turn-on transition. Inductance current I_Lk varies from a negative value to the initial current which is the minimum current value of inductance L_m1 when the proposed converter is operated in CCM. When t = t₇, current of magnetizing inductance L_m1 reaches its minimum value again, a new switching cycle will start.

4. Design of the Proposed PFC

Due to the input voltage with a sine wave, the input current I_in is time dependent. A function of peak current of switch M₁ or M₂ is, in turn, a function of duty cycle of the converter. Therefore, peak switch current I_DS1 needs to be determined as a function of which the instantaneous operating point is on the input line period. Neglecting ripple current in the switch, switch current I_DS1(ϕ) can be determined by

$$I_{DS1}(\varphi )=\frac{I_{av}(\varphi )}{D(\varphi )},$$

(1)

where I_av(ϕ) is the average input line current and D(ϕ) is an instantaneous duty cycle. In (1), one half of the line cycle period is considered to be normalized to the interval [0, π], and ϕ is an arbitrary point on that interval. I_av(ϕ) is given by

$$I_{av}(\varphi )=\frac{\sqrt{2}{P}_o}{\eta V_{rms}}\sin (\varphi ),$$

(2)

where P_o is the output power of the converter, $\eta$ indicates the conversion efficiency and V_rms is the input voltage of line source. The instantaneous duty cycle is

$$D(\varphi )=\frac{V_o}{V_o+\sqrt{2}N{V}_{rms}\sin (\varphi )},$$

(3)

where V_o is the output voltage and N is the turns ratio of transformer T_r. As mentioned above, D(ϕ) can vary from D_min to 1. In order to achieve systematic design of the proposed bridgeless flyback converter, its design is listed as follows:

● switches M₁–M₂

The turns ratio N of transformer is selected to accommodate a low voltage ratio device for minimum duty cycle of switch to realize reasonable values, when the active clamp circuit in the proposed converter can provide a perfect suppression of the spike voltage across the main switch M₁ or M₃ due to leakage inductance of transformer, the maximum off-state voltage V_DS1(max) can be determined by

$$V_{DS1\left(\max \right)}=\sqrt{2}{V}_{rms}^{HL}+V_O/N,$$

(4)

where $V_{rms}^{HL}$ is the high line voltage of input source which is equal to AC 265 V and V_o indicates the output voltage. The ranges of the minimum duty cycle can be given by

$$D_{\min }^{LL}=\frac{V_O}{V_O+\sqrt{2}N{V}_{rms}^{LL}},$$

(5)

And

$$D_{\min }^{HL}=\frac{V_O}{V_O+\sqrt{2}N{V}_{rms}^{HL}},$$

(6)

where $V_{rms}^{LL}$ is the low line voltage of the input source which is equal to AC 90 V. In general, the minimum duty cycle ranges are determined between 0.2 and 0.5 under the input source at high line or low line voltage.

The maximum switch average current $I_{DS1(av)}^{\max }$ occurs at the maximum load and the minimum line voltage, when power factor is approximately unity, the maximum switch average current $I_{DS1(av)}^{\max }$ is written by

$$I_{DS1(av)}^{\max }=\frac{\sqrt{2}{P}_O^{FL}}{\eta V_{rms}^{LL}},$$

(7)

where $P_O^{FL}$ is output power of the proposed converter operated in the full load condition. Its worst case maximum peak current also occurs under the same operating conditions as above. The peak current $I_{DS1(peak)}^{\max }$ can be calculated from

$$I_{DS1(peak)}^{\max }=\frac{\sqrt{2}{P}_O^{FL}}{\eta D_{\min }^{LL}{V}_{rms}^{LL}}+\frac{\sqrt{2}{V}_{rms}^{LL}{D}_{\min }^{LL}{T}_S}{2L_m},$$

(8)

where L_m is the magnetizing inductance of transformer T_r and T_S is the switching period of switch M₁ or M₃. For this particular design, since voltage stress and peak current of active clamp switch M₂ or M₄ are the same as that of switch M₁ or M₃, device selection of switch M₂ or M₄ is the same as M₁ or M_3.

● Transformer T_r

Since input voltage changes from a low line voltage $V_{rms}^{LL}$ to a high line voltage $V_{rms}^{HL}$, it will affect the minimum duty cycle $D_{\min }^{LL}$ and $D_{\min }^{HL}$. In order to obtain a reasonable value of $D_{\min }^{LL}$ or $D_{\min }^{HL}$ for active clamp flyback converter, $D_{\min }^{LL}$ or $D_{\min }^{HL}$ is designed at between 0.3 and 0.5. According to the reasonable ranges of $D_{\min }^{LL}$ or $D_{\min }^{HL}$, turns ratio N is determined by

$$N=\frac{(1-D_{\min }^{LL})V_O}{\sqrt{2}{D}_{\min }^{LL}{V}_{rms}^{LL}},$$

(9)

Or

$$N=\frac{(1-D_{\min }^{HL})V_O}{\sqrt{2}{D}_{\min }^{HL}{V}_{rms}^{HL}},$$

(10)

The input voltage V_in adopts a sine wave. During the positive half period or the negative half period, input voltage V_in can vary from 0 V to the maximum value, and then from the maximum value to 0 V. In order to determine magnetizing inductance L_m1(=L_m) or L_m2(=L_m), current variation value △I_Lm of magnetizing inductance L_m1 or L_m2 is determined with the worst case maximum peak switch current as a reference value. Therefore, △I_Lm can be written by

$$\Delta I_{Lm}=K{I}_{DS1(peak)}^{\max }=K(\frac{\sqrt{2}{P}_O^{FL}}{\eta D_{\min }^{LL}{V}_{rms}^{LL}}+\frac{\sqrt{2}{D}_{\min }^{LL}{V}_{rms}^{LL}{T}_S}{2L_m}).$$

(11)

For this particular design, K is determined at approximately 0.1.

● Clamp Capacitor C_C

Since switches M₁–M₄ are operated with ZVS at turn-on transition and the energy stored in leakage inductance L_K can be recycled, it is by means of leakage inductance L_K and clamp capacitor C_C operated in the resonant manner. A better design of the proposed converter is to select the clamp capacitor C_C value so that one half of the resonant period formed by the clamp capacitor C_C and leakage inductance L_K exceeds the maximum off time of switch M₁ or M₃. Therefore, clamp capacitor C_C can be determined by

$$C_C\approx \frac{{(1-D_{\min }^{LL})}^2{T}_S^2}{{\pi }^2{L}_K}$$

(12)

where L_K is equal to 1~5% of magnetizing inductance L_m1 or L_m2.

● Output Capacitor C_o

The output capacitor C_o is used to reduce output voltage ripple. Since the input voltage V_in of the proposed converter is a half-wave rectification waveform, output voltage V_o contains a voltage ripple with 120 Hz. When the maximum peak output voltage △V_o is specified, output capacitor C_o can be given by

$$C_o=K\frac{P_o^{\max }}{240\pi V_o\Delta V_O},$$

(13)

where $P_o^{\max }$ (=$P_o^{FL}$) is the maximum output power. Furthermore, the required ripple current rating $I_{CO(rms)}^{\max }$ for output capacitor is determined by

$$I_{CO(rms)}^{\max }=\frac{P_o^{\max }}{\sqrt{2}{V}_O}.$$

(14)

5. Measured Results

In order to verify performances of the proposed power system, as shown in Figure 8, a prototype with following specifications was implemented. The proposed power system includes two converters: The DC/DC converter with battery source and the proposed PFC with line source. Their specifications are respectively shown in the following:

• The DC/DC converter with battery source
  Input Voltage V_B: DC 20–26 V (two batteries connected in series),
  Switching frequency f_s: 50 kHz,
  Output Voltage V_DC1: DC 48 V,
  Maximum output current I_DC1(max): 2.5 A, and
  Maximum output power P_DC1(max): 120 W,
• The proposed PFC with line source
  Input voltage V_in: AC 90–265 V,
  Switching frequency f_s: 50 kHz,
  Output Voltage V_DC2: DC 50 V,
  Maximum output current I_DC2(max): 6 A,
  Maximum output power P_DC2(max): 300 W,

According to the previous specifications, the design values of the key components of the proposed power system can be determined. The DC/DC converter with battery source is shown in Figure 14 and the proposed PFC with line source is shown in Figure 6. According to design of the proposed flyback converter, parameter values in the proposed one is listed in

Table 3. Parameter values of the proposed flyback converter.

Parameter	Design Value	Experimental Value	Design Value by Equation	Conditions
Iav(Φ)	5.55sin(Φ) A	-	(2)	η = 85%, Vrms = 90 V, PO = 300 W
$D_{\min }^{LL}$	0.43	-	(5)	VO = 48 V, $V_{rms}^{LL}$ = 90 V, N = 0.5
$D_{\min }^{HL}$	0.204	-	(6)	VO = 48 V, $V_{rms}^{HL}$ = 265 V, N = 0.5
$I_{DS1(av)}^{\max }$	5.5 A	-	(7)	η = 85%, $V_{rms}^{LL}$ = 90 V, $P_O^{\mathrm{F}L}$ = 300 W
$I_{DS1(peak)}^{\max }$	13.1 A	-	(8)	η = 85%, $V_{rms}^{LL}$ = 90 V, $P_O^{FL}$ = 300 W, Lm = 2.72 mH, $D_{\min }^{LL}$ = 0.43, TS = 20 μs
CC	0.41 μF	0.47 μF	(12)	LK = 32 μH, $D_{\min }^{LL}$ = 0.43, TS = 20 μs
CO	1730 μF	2200 μF	(13)	K = 0.1, VO = 48 V, ΔVO = 0.48 V, $P_O^{\max }$ = 300 W

. Semiconductor selection of the proposed one is illustrated in

Table 4. Semiconductor selection of the proposed flyback converter.

Component	Design Maximum Voltage/Current Ratings	Component Selection and Voltage/Average Current/Peak Current
M1–M4	470 V/13.1 A	IRG4PH50KDPbF 1200 V/24 A/90 A
D1–D3	375 V/13.1 A	HFA08TB60 600 V/8 A/60 A
D2	235 V/19.87 A	40EPF06PbF 600 V/10 A/40 A

. Their devices are determined as follows:

• The DC/DC converter with battery source
  Switches M₁, M₂: IRFP250,
  Diodes D₁, D₂: SR10100,
  Inductances L₁, L₂: 230 μH, and
  Capacitor C_DC1: 1000 μF,
• The proposed PFC with line source
  Switches M₁–M₄: IRG4PH50KDPbF,
  Transformer T_r core: EE-55,
  Diode D₂: 40EPF06PbF,
  Output capacitor C_O: 2200 μF/63 V
  Diodes D₁, D₃: HFA08TB60,
  Capacitors C₁, C₂: 0.1 μF/630 V,
  Clamp capacitor C_C: 0.47 μF,
  Turns ratio N of transformer T_r: 0.5,
  D^LL_min: 0.43, and
  Magnetizing inductances L_m1, L_m2: 2.72 mH,

Since this paper focuses on design and implementation of the bridgeless flyback converter, measured results of the DC/DC converter with battery source have only shown that output voltage V_DC1 and current I_DC1 under step-load changes and under supplying power to load in parallel connection. Measured output voltage V_DC1 and current I_DC1 waveforms under step-load changes between 10% and 100% of full load condition with duty ratio of 50% and repetitive period of 1s is shown in Figure 15. From Figure 15, it can be seen that the voltage regulation of output voltage V_DC1 has been limited within ±1%.

For the proposed PFC, since the input voltage V_in of AC 90 V is the worst case for operational states of the proposed one, the experimental results are shown with the input voltage of AC 90 V. Measured waveforms of input voltage V_in and current I_i is shown in Figure 16 under the line source of AC 90 V. Figure 16a shows those waveforms under 10% of full load condition and Figure 16b illustrates those waveforms under 100% of full load condition. From Figure 16, it can be found that input voltage V_in and current I_i are approximately in phase. Figure 17a illustrates measured waveforms of voltages V_C1, V_C2 and currents I_D1, I_D3 under 50% of full load condition and the input voltage of 90 V, while Figure 17b shows measured waveforms of voltage V_C1 and current I_D1. From Figure 17, it can be seen that waveforms of currents I_D1 and I_D3 follow ones of voltages V_C1 and V_C2 variation, respectively. Since duty ratio D varies from 0.204 to 1, and the proposed flyback converter is operated in DCM or CCM. Figure 18 and Figure 19 show measured waveforms of switch voltage V_DS and current I_DS under input voltage of 90 V. Figure 18 illustrates measured waveforms of switch voltage V_DS1 and current I_DS1, and switch voltage V_DS2 and current I_DS2 and current I_DS2 under 10% of full load condition and the input voltage of 90 V. From Figure 18, it can be found that the proposed flyback converter is operated in DCM. The active clamp capacitor can reduce the voltage spike and recover energy stored in leakage inductor of the transformer. Figure 19 depicts those waveforms under 30% of full load condition and the input voltage of 90 V, from which it can be seen that switches M₁ and M₂ are operated in ZVS at turn-on transition. In Figure 18 and Figure 19, voltage V_DS1 across switch M₁ has a ring voltage. The ring voltage is generated by leakage inductor of secondary winding of transformer and parasitic capacitor of diode D₂ when switch M₁ is turned on. It can be eliminated by snubber circuit applied to diode D₂.

Measured output voltage V_DC2 and current I_DC2 waveforms under step-load changes between 10% and 100% of full load condition with duty ratio of 50% and repetitive period of 1s as shown in Figure 20, from which it can be observed that the voltage regulation of output voltage V_DC2 has been limited within ±1%. Figure 21 depicts the measured efficiency of the proposed PFC from light load to heavy load under AC 90 V. When load is greater than 40% of full load condition, each efficiency is greater than 86%. For further increase in conversion efficiency of the proposed converter, switches M₁–M₄ can adopt a lower conduction resistance to reduce conduction loss. It also decreases the switching frequency of the switch to reduce switching loss. In order to verify a high PF, the plot of power factor of the proposed one from light load to heavy load illustrated in Figure 22, from which it can be found that power factor of the proposed one can be greater than 0.8 under different input voltages. In particular, when input voltage is at a high line level and load is in the light load, PF has a lower value. Due to a lower output current I_DC2, PFC control IC is difficult to control input current I_i, resulting in a lower PF. Figure 23 shows the harmonic current from light load to heavy load under different input voltage levels, illustrating that their harmonic current can meet requirements of IEC6100-3-2 class A.

According to operational cases of the proposed power system, there are four operational cases for DC load power variations. Figure 24 shows measured waveforms of voltages V_DC1 and V_DC2, and currents I_DC1 and I_DC2 from P_L = 0 W to P_L = 125 W. Due to P_DC2(max) = 300 W, operational case changes of the proposed one can be varied from case I to case II. When load power P_L is from 0 W to 325 W, operational case changes are from case I to case III. Those waveforms are shown in Figure 25. If P_L variations are from 0 W to 450 W, operational case charges are from case I to case IV. Those waveforms are shown in Figure 26. As mentioned above, the proposed power system can change operational case by the control algorithm of the proposed power system.

6. Conclusions

This paper proposes a power system for DC load applications. The proposed power system adopts the DC/DC converter with battery source and the proposed PFC to supply power for DC loads of 48 V power system. The proposed PFC uses a bridgeless flyback converter to achieve a high PF. In this paper, operational principle and design of the proposed one have been described in detail. According to the experimental results, switches M₁ and M₂ of the proposed PFC can be operated with ZVS at turn-on transition. Furthermore, the proposed one can also achieve a lower harmonic current, a higher conversion efficiency and a higher PF. Its harmonic current from light load to heavy load under different input voltage levels can meet the requirements of IEC6100-3-2 class A. Therefore, the proposed bridgeless flyback converter has been implemented to apply to the utility line system as a power factor corrector. In addition, the proposed power system for DC loads of 48 V power system also has been implemented to verify its feasibility. It is suitable for a DC distribution of 48 V power system application.