A Fast-Transient Output Capacitor-Less Low-Dropout Regulator Using Active-Feedback and Current-Reuse Feedforward Compensation

Abstract

In this paper, output capacitor-less low-dropout (LDO) regulator using active-feedback and current-reuse feedforward compensation (AFCFC) is presented. The open-loop transfer function was obtained using small-signal modeling. The stability of the proposed LDO was analyzed using pole-zero plots, and it was confirmed by simulations that the stability was ensured under the load current of 50 mA. The proposed compensation method increases gain-bandwidth product (GBW) and reduces the on-chip compensation capacitor. The proposed AFCFC technique was applied to a three-stage output capacitor-less LDO. The LDO has a GBW of 5.6 MHz with a small on-chip capacitor of 2.6 pF. Fast-transient time of 450 ns with low quiescent current of 65.8 μA was achieved. The LDO was fabricated in 130 nm CMOS process consuming 180 × 140 μm² of the silicon area.

1. Introduction

Development of miniature wireless communication chip has led to great development of mobile devices and internet of things (IoT) devices. These devices receive power from the limited battery. Various voltages which are optimized power and performance for each sub-circuit are required from a battery. Therefore, a power management integrated circuit (PMIC) for efficiently managing battery power and supplying various voltages has been attracting great interest [1,2,3,4,5,6,7,8,9,10]. As shown in Figure 1, the PMIC which is combined a switching DC-DC converter and low dropout linear regulator (LDO) is commonly used for converting DC voltage [6,7,8,9,10,11]. A high efficiency switching converter is used to convert DC voltage, and LDOs are used to remove the switching ripple and provide stable power to sub-circuits. Many systems-on-chips (SoC) require various supply voltages to separate power planes and reduce crosstalk arising from each sub-system, so that the required number of LDO is increasing. Traditional LDO has employed a large compensation capacitor to guarantee loop stability, but these bulky compensation capacitors are not feasible to be integrated on the chip. Thus, output capacitor-less LDO (OCL-LDO) [12,13,14,15,16] that can stabilize the feedback loop without external capacitors has attracted great attention for on-chip applications. The OCL-LDO can reduce the number of off-chip components and I/O pads, thus making the system more cost-effective.

The main design issues of the OCL-LDO are to increase power conversion efficiency, minimize dropout voltage, and reduce quiescent current without decreasing transient performance. For a heavy load current, a large pass transistor seems to be suitable for power efficiency by reducing dropout voltage. However, the parasitic capacitor of a large pass transistor can degrade the phase margin significantly. Low quiescent current increases the output resistance of the LDO under light load conditions, and it moves the output pole to be lower than the unity-gain-frequency (UGF), degrading the phase margin and causing instability as a result. Increasing power conversion efficiency and phase margin are a difficult design challenge while maintaining the transient performance [12,13,14,15,16].

The block diagram of the OCL-LDO regulator is shown in Figure 2. The OCL-LDO typically consists of a feedback resistor ladder (R_F1, R_F2), an error amplifier, a power transistor (M_PT), and a compensation network. The output voltage of the LDO, V_{LDO_OUT}, is determined by the resistance ratio of the feedback resistor ladder and the reference voltage (V_REF). In order to achieve high loop gain and excellent voltage regulation performance, usually a two-stage error amplifier is adopted. This amplifier compares V_REF with the feedback voltage (V_FB) from the output and amplifies the difference. The output signal of the error amplifier is the input signal of the power transistor (M_PT) to control the output current. Since the power transistor is a common source amplifier for a small signal, the LDO loop can be regarded as a multi-stage amplifier.

Multi-stage amplifiers which are more than two-stages should be frequency compensated and various frequency compensation methods for designing multi-stage amplifiers have been studied as shown in Figure 3 [17,18,19,20,21,22,23]. Nested Miller compensation (NMC) [17,18,19] in Figure 3a is a well-known technique which circuit parameters such as transconductance (g_m) and compensation capacitors have been well-explained in [18]. Miller capacitors are connected between the output node of the final stage and the output node of each stage. These capacitors split away poles from each other. However, this technique requires large on-chip compensation capacitors to obtain sufficient phase margin. Large compensation capacitors decrease gain-bandwidth product (GBW), resulting in slow transient response or increasing current consumption. Another popular compensation method is reverse NMC (RNMC) as shown in Figure 3b. Similar to the NMC technique, a Miller capacitor is used for pole-splitting. In contrast to NMC method, Miller capacitors are connected between the output node of the first stage and the output node of each stage. This method provides higher GBW than NMC because it has a smaller capacitance to be driven at the output node [20,21]. However, this method has two right-half-plane (RHP) zeros located near the UGF, same as the NMC method [20]. The low-frequency RHP zero degrades the phase margin significantly [23]. As shown in Figure 3c, based on RNMC structure, two current buffers with Miller capacitor feedback are used to shift the RHP zeros to the left-half plane (LHP), thus increasing the phase margin [22]. However, [22] is based on a large external capacitor in the range of hundreds of nanofarads (nF) to guarantee stability and reduce output voltage overshoot, thus it requires a large on-chip compensation capacitor. This large on-chip capacitor degrades the transient performance and consumes a large area. Thus, a new compensation strategy and analysis that can be employed to the on-chip applications is required.

In this work, an active-feedback and current-reuse feedforward compensation (AFCFC) is proposed to achieve fast transient response with a low quiescent current and small on-chip capacitor. The proposed AFCFC method enables frequency compensation with small on-chip capacitor by using active feedback. RHP zero can be moved to the LHP by removing the high-frequency feedforward path formed by the Miller compensation capacitor. Also, the current reuse feedforward path shifts LHP zero to a lower frequency, thus one of the non-dominant poles can be canceled. This allows a smaller compensation capacitor to maintain a sufficient phase margin, and GBW is further improved. The proposed compensation configuration is investigated with pole-zero analysis and verified with a three-stage OCL-LDO in Section 2. The circuit implementation of the three-stage OCL-LDO using the proposed AFCFC is described in Section 3. In Section 4, measurement results are discussed and the conclusion is presented in Section 5.

2. Analysis of the Proposed AFCFC LDO

Figure 4 shows the block diagram of a three-stage amplifier employing the proposed AFCFC. The transconductances, output impedances, and lumped output capacitors of the first, second, and output stages are represented by g_m1,2,L, R_o1,2,L, and C_1,2,L, respectively. The active-feedback paths are depicted with transconductances of g_mfb1,2 and compensation capacitors of C_m1,2. The feedforward paths are denoted by g_mff1,2.

Figure 5 shows the small-signal equivalent circuit of the proposed AFCFC amplifier, and the transfer function A(s) = V_out(s)/V_in(s) can be derived in (1),

$$A(s)=\frac{A_{DC}\left[1+s\left\{\frac{C_{m1}}{g_{mfb1}}+\frac{C_{m2}}{g_{mfb2}}+\frac{C_{m2}{g}_{mff2}\left(g_{m1}-g_{mff1}\right)}{g_{m1}{g}_{m2}{g}_{mL}}\right\}+s^2\left\{\frac{C_{m1}{C}_{m2}}{g_{mfb1}{g}_{mfb2}}+\frac{C_{m1}{C}_{m2}{g}_{mff2}\left(g_{m1}-g_{mff1}\right)}{g_{m1}{g}_{m2}{g}_{mL}{g}_{mfb1}}\right\}\right]}{\left(1+\frac{s}{p_{-3dB}}\right)\left[1+s\left\{\frac{C_L{C}_{m2}}{C_{m1}{g}_{mL}}+\frac{C_{m2}}{g_{mfb2}}+\frac{C_{m2}}{g_{mL}}+\frac{C_{m2}{g}_{mff2}}{g_{m2}{g}_{mL}}\right\}+s^2\frac{C_L{C}_{m2}}{g_{mfb1}{g}_{mL}}\right]}$$

(1)

where A_DC = g_m1·g_m2·g_mL·R_o1·R_o2·R_L is the DC voltage gain and p_−3dB = 1/(C_m1·g_m2·g_m3·R_o1·R_o2·R_L) is the −3 dB dominant pole frequency. To simplify the equations, two assumptions were considered. First, the gain of each stage is much larger than one. Second, two compensation capacitors and a load capacitor are much larger than the lumped output capacitors. These assumptions are represented in the equations:

$$g_{m1}{R}_{o1},g_{m2}{R}_{o2},g_{mL}{R}_L\gg 1$$

(2)

$$C_{m1},C_{m2},C_L\gg C_1,C_2$$

(3)

The proposed system has one dominant pole, a pair of non-dominant complex poles, and two left-half-plane (LHP) zeros. Assuming that the dominant pole frequency is much lower than the complex pole and LHP zero frequencies, the gain-bandwidth product (GBW) and second non-dominant complex poles (p_2,3) can be derived as:

$$GBW\equiv A_{DC}\cdot p_{-3dB}=g_{m1}/C_{m1}$$

(4)

$$\left|p_{2,3}\right|=\sqrt{g_{mfb1}{g}_{mL}/C_{m2}{C}_L}$$

(5)

In conventional frequency compensation methods [17,18,19,20,21,22], high frequency feedforward path is generated by Miller capacitor, thus generating RHP zeros. In the proposed AFCFC, active-feedback paths which are formed by g_mfb1 and g_mfb2 can effectively block the high frequency feedforward path generated by C_m1 and C_m2. Thus, the two RHP zeros are moved to LHP and the phase margin is increased.

In (1), the numerator is represented with second order terms. For a simple analysis, it assumes that the numerator of (1) has approximately two real zeros. When g_m1 is equal to g_mff1, two real LHP zeros can be expressed as:

$$z_1=1/[(C_{m1}/g_{mfb1})+(C_{m2}/g_{mfb2})]$$

(6)

$$z_2=g_{mfb1}/C_{m1}+g_{mfb2}/C_{m2}$$

(7)

When the first stage transconductance g_m1 and active-feedback transconductance g_mfb1,2 are equal, the two zeros can be simplified as:

$$z_1=g_{m1}/\left(C_{m1}+C_{m2}\right)$$

(8)

$$z_2=g_{m1}\left[\left(1/C_{m1}\right)+\left(1/C_{m2}\right)\right]$$

(9)

It has to be noted that, since the feedforward transconductance g_mff1 cancels the output stage transconductance components, the zero location is not a function of g_mL but g_mfb1,2, as represented in (6) and (7).

Figure 6 shows the pole-zero locations of the LDO. Figure 6a shows the pole-zero plot with two RHP zeros of NMC [17]. The RHP zeros degrade the phase margin of the LDO. The RHP zeros can be moved to the LHP using active-feedback compensation, as shown in Figure 6b. The zero variation is due to the pass transistor transconductance g_mL that varies from hundreds of μA/V to tens of mA/V depending on load conditions. Although the LHP zeros do not degrade the loop stability of the LDO, active-feedback compensation without feedforward paths places the zeros at a high frequency, thus these zeros cannot remove the negative phase shift due to non-dominant complex pole p_2,3. In the proposed AFCFC, the zeros are located at low frequency by adding feedforward paths, as represented in (8) and (9), due to the feedforward transconductance g_mff1,2.

Typically, phase margin of 60° can be obtained by setting UGF to be half of the second non-dominant complex pole p_2,3 (p_2,3 > 2 × UGF). In this work, LHP zero z₁ derived from (8) is located near the second complex pole p_2,3, as shown in Figure 6c. Since low frequency zero z₁ cancels out one of the complex pole p_2,3, larger UGF can be adopted while maintaining the phase margin of 60°. In other words, a larger UGF allows a small compensation capacitor C_m1 to be used for the same g_m1, so that the proposed LDO can achieve enhanced bandwidth and fast transient performance with small quiescent current. The high-frequency LHP zero z₂ is located at an at-least five times higher frequency than z₁, thus the z₂ has little effect on the open-loop response of the LDO. The complex pole p_4,5 and zero z₃ depicted in Figure 6 are non-dominant components generated by inter-stage parasitic capacitor C₁ and C₂ in Figure 4.

Figure 7 shows the simulated open-loop response of the proposed LDO at heavy load and light load conditions. The LDO has a high DC gain of >95 dB due to the three-stage configuration. The LDO achieves a phase margin of >62° even in the worst case, where the phase margin can be represented as:

$$PM={90}^{°}+{\tan }^{-1}\left(\frac{GBW}{z_1}\right)-{\tan }^{-1}\left(\frac{2\cdot \xi \cdot GBW/\left|p_2\right|}{1-{\left(GBW/\left|p_2\right|\right)}^2}\right)$$

(10)

The simulated GBW is 5.6 MHz for a light load and 4.2 MHz for a heavy load. The damping factor of p_2,3 is chosen to be 0.7 or higher value to avoid gain peaking near the UGF and rapid negative phase shift that can cause phase margin degradation.

3. OCL-LDO Circuit Implementation

Figure 8 shows a schematic of the three-stage AFCFC OCL-LDO. The LDO has seven transconductance blocks. The error amplifier consists of two stages. The first stage is a folded-cascode amplifier composed of transistors M₁–M₁₂. The second stage is a cascode amplifier with a positive gain using transistors M₁₃–M₂₀. Both the first and the second stages have four-stacked cascade structure, so that the LDO has very large overall loop gain, as shown in Figure 7. This large loop gain increases the regulation accuracy such as load and line regulation. The output stage is composed of a pass transistor M_PT, a transistor M₂₁ for the feedforward path, and feedback resistors R_F1 and R_F2.

The active-feedback paths are realized with two compensation capacitor C_m1 and C_m2, and two transconductance g_mfb1 and g_mfb2 which are implemented by M₈ and M₁₁, respectively. g_mfb1 is positive but g_mfb2 is negative. Since the loops formed by the active-feedback have approximately unity gain, due to the low input impedance 1/g_mfb1,2, there is no need to consider loop stability. Two feedforward transconductances, g_mff1 and g_mff2, are implemented with M₂₀ and M₂₁ respectively. Current-reuse structure is utilized with g_mff1 to reduce extra quiescent current of error amplifier. Unlike g_mff1, g_mff2 draws extra current to reduce the output resistance and guarantee loop stability at light or no load conditions, where output resistance R_out = r_oPT‖r_o21‖(R_F1 + R_F2)‖R_L. The feedforward transconductance g_mff2 also increases the transient performance of the LDO.

Figure 9 shows a simulated load transient with output capacitor of 100 pF. When the load current abruptly changes, the output voltage can be immediately recovered through the first stage of error amplifier and the feedforward transconductance g_mff2. The load transient simulations of two cases have been performed with the same quiescent current of 60 μA. g_m1,2, g_mfb1,2, and g_mff1 are chosen almost at the same value about 120 μA/V, and g_mff2 is selected to 250 μA/V. The compensation capacitors, C_m1 and C_m2, are chosen to be 1.6 and 1 pF, respectively. The size of pass transistor M_PT is 3000/0.385 μm for the maximum load current of 50 mA.

4. Implementation and Experimental Results

Figure 10 shows the chip photograph of the proposed AFCFC OCL-LDO, and it was fabricated using a TSMC 130 nm CMOS technology. The OCL-LDO occupies a small active area of 0.18 × 0.14 mm² due to small compensation capacitors of the proposed AFCFC configuration. The OCL-LDO is able to supply a load current from 0 to 50 mA with the minimum dropout voltage V_DO of 200 mV. The input voltage range is from 1.4 V to 2.7 V. Due to the high loop gain, the proposed OCL-LDO has good regulation accuracies such as line regulation and load regulation as shown in

Table 1. Performances Comparison with Recently-Reported OCL-LDOs

Parameter	This Work	2014 [13]	2013 [14]	2017 [15]
Technology	130 nm	180 nm	65 nm	180 nm
Active Area (mm2)	0.025	0.14	0.017	0.033
Iout (mA)	0–50	0–50	0–100	0–100
VDO (mV)	200	200	200	200
Vout (V)	1.2–2.5	1.6	1	1.6
Con-chip (pF)	2.6	28	4.5	12.7
CL,max (pF)	100	100	100	100
IQ (μA)	65.8	55	0.9–82.4	71–101
ΔVout,max (mV)	87.5	75	68.8	210
Line Reg. (mV/V)	1.23	N/A	4.7	131
Load Reg. (mV/mA)	0.048	0.14	0.3	N/A
PSR (dB)	−56@10 kHz 1	−62@10 kHz	−58@10 kHz	−76@1 MHz
Settling Time (μs)	<0.7	<6	6	0.2
F.o.M.	0.00395	0.00456	0.00321	0.00267

¹ Simulation results.

.

Figure 11a shows the measured load transient responses with an input supply voltage of 1.4 V and load capacitor of 100 pF. When the load current is turned-on and turned-off rapidly between 0 and 50 mA, settling times of 450 and 695 ns were obtained, respectively. The voltage overshoots of 87 mV and 38 mV were achieved for the turn-on and turn-off cases, respectively. Figure 11b shows the load transient responses with an input supply voltage of 2.7 V. The settling time is slightly enhanced to 415 and 615 ns for the turn-on and turn-off cases, respectively, due to the increased quiescent current of the error amplifier. The proposed LDO has a faster settling time compared to other works due to the proposed AFCFC.

The measured performances and comparisons of the previous-reported OCL-LDOs are summarized in Table 1. The figure-of-merit (F.o.M.) for the OCL-LDO in [12] is chosen for transient performance comparison. The F.o.M. is given as:

$$F.o.M.=\frac{C_{on-chip}}{C_{L,max}}\cdot \frac{\Delta V_{out,max}}{V_{out}}\cdot \frac{I_Q}{I_{out,max}}\cdot {10}^{(PSR[dB]/20)},$$

(11)

where C_L,max, ΔV_out,max, I_Q, and I_out,max are the maximum load capacitor, maximum voltage overshoot, quiescent current, and maximum output current of LDO, respectively. The smaller F.o.M. shows the better performance.

5. Conclusions

An active-feedback and current-reuse feedforward compensation (AFCFC) for output capacitor-less LDO using 0.13-μm CMOS technology has been presented. The stability of the proposed LDO was analyzed using pole-zero plots, and it was confirmed by simulation results that the stability was ensured regardless of the load condition. The proposed frequency compensation allows the use of a small on-chip compensation capacitor and extends gain-bandwidth product for LDO. The fabricated LDO has high loop gain due to the three-stage configuration, thus the LDO has good regulation accuracies. The proposed LDO also has high gain-bandwidth product with low quiescent current and fast transient performance. The LDO with proposed AFCFC achieves a settling time of 450 ns with maximum load capacitor of 100 pF. The proposed LDO consumes a low quiescent current of 65.8 μA.