Analysis of Asymmetric Hybrid Modular Multilevel Topology for Medium-Voltage Front-End Converter Applications

Abstract

Modular multilevel converters (MMCs) have been conceived as an alternative in front-end converter applications to enhance the converter system’s reliability, minimize total harmonic distortion, and improve power quality. These converters utilize several DC-link capacitors and power electronic switches, along with switches operating with high switching frequencies, to attain the desired characteristics. Thereby, this paper systematically proposes a novel three-phase asymmetric hybrid modular multilevel converter (AHMMC) for front-end converters used in lower-medium-voltage applications. The AHMMC configuration is based on a three-phase converter connected to a per-phase series arrangement with a cascaded converter module (CCM). The study investigates the AHMMC and proposes a control scheme, which minimizes the voltage range on switches and maintains the current to its reference value. Furthermore, the study also introduces an active balancing of voltage across DC-link capacitors based on the phase opposition disposition PWM (POD-PWM) method. Our new configuration has features such as low switching loss, reduced DC-link voltage, a wider modulation range for the unity power factor (PF), and low voltage and current harmonic distortion. The simulation results are added to verify the performance of the new AHMMC topology and the usefulness of the modular control scheme. In addition, a low-voltage laboratory prototype based on customized control and power boards is built to validate the proposed converter and its control scheme in practice.

1. Introduction

The pervasive use of power electronics and inductive loads highlights the need to focus on line pollution and the low power factor. Considering the power electronic system, diode and thyristor rectifiers are used commonly in front-end converters as an interface with the AC mains. However, the non-linear nature of these rectifiers produces harmonic currents in the AC mains, which result in various power quality issues. Due to these issues, some techniques, such as active, passive, and hybrid filters [1], have been developed for conventional rectifiers in existing installations; however, most use expansive and bulky filters.

To maintain power quality within acceptable limits, multilevel converters (MLCs) have recently attracted attention due to their ability to limit the current total harmonic distortion (THD) to 5%, as specified by IEEE-519. These MLCs have been extensively studied for high-power applications at medium voltages as they have several advantages, including low-stress voltage on their switches, minimum voltage harmonics, and low electromagnetic interference (EMI). Conventional MLCs can be classified as a flying capacitor (FC) [2,3], neutral point clamped (NPC) [4,5], or cascaded H-bridge (CHB) [6,7]. However, these MLC topologies have some disadvantages, for example, the NPC and FC converters have unequal voltages across switches and complex control for balancing the DC-link voltage, and the CHB requires more DC sources. Moreover, as the output voltage levels increase, the component count and voltage balancing control complexity increase, which affects the converter system’s efficiency and reliability.

Recently constructed hybrid multilevel converters using several conventional MLC topologies, which are also known as hybrid modular multilevel converters (HMMC), have been introduced. Some of these HMMCs are an H-bridge with an FC module [8], an NPC with an H-bridge converter [9], a traditional three-phase two-level converter with an H-bridge module [10], a generalized FC with an n-level and active NPC (ANPC) [11], an H-bridge with a half-bridge converter [12], an FC-based ANPC converter [13], a modular multilevel matrix converter, and a Hexverter [14]. In comparison with NPCs, FCs, and CHBs, HMMCs have the advantages of high efficiency, high reliability, and lower modulation complexity [15,16,17]. The modular multi-level converter (MMC) is a suitable topology for medium-power high-voltage applications such as HVDC transmission [18,19], motor-driven applications [20,21], and front-end converter applications [22,23,24]. Moreover, the majority of research is focused on various DC-link voltages to raise output voltage levels and lower redundancy with the same number of components. In the literature, these topologies are referred to as asymmetric converters [8,25].

This paper investigates the design and control of the proposed AHMMC topology. Improved output voltage levels with minimum components are realized using the AHMMC. To reduce the switch loss, the converter switches can be flexibly operated under the proposed hybrid modulation technique, which offers a lower switching frequency. The DC-link voltages are balanced to achieve the required output voltage level. Finally, a laboratory prototype is developed to experimentally validate the proposed converter and its control scheme. A customized control board is built, which utilizes a micro-controller unit (TMS320C28346 Delfino^TM), complex programmable logic device (EPM570 ALTERA®), and AD conversion to realize the control in practice.

This paper is arranged as follows. Section 2 demonstrates the proposed model configuration and its working principles. Section 3 discusses the employment of the hybrid modulation strategy and Section 4 describes a modular control scheme for tracking the current and maintaining the DC-link capacitor voltage at their respective references. Section 5 and Section 6 provide the simulation and experimental validation of the AHMMC and its modular control method, respectively. Finally, Section 7 provides the conclusions.

2. Proposed Model Configuration

Figure 1 presents the proposed AHMMC topology, which is based on a per-phase series configuration of the high-voltage two-level three-phase converter (fundamental converter) with a low-voltage cascaded converter module that generates five levels at the output. The two-level three-phase converter has three legs; each leg contains two alternately active switches, which are connected to a common DC source, E. Considering the a-phase leg, it generates an output voltage level of 0 and E at AC terminal Y. The series connecting the CCM to the a-phase leg contains six power switches (S${}_{\mathrm{a}}$, S${}_{\mathrm{b}}$, and S${}_{\mathrm{c}}$ and, respectively, S${}_{\mathrm{a}}^{\prime }$, S${}_{\mathrm{b}}^{\prime }$, and S${}_{\mathrm{c}}^{\prime }$) and two DC-link capacitors C${}_{h1}$ and C${}_{h2}$. The voltage of the DC-link capacitors is $V_{Ch1}$ = $V_{Ch2}$ = $V_{dc}$ = $0.275E$ (subscript h is either a, b, or c), which yields the maximum output voltage of five levels at the AC terminal $\left(V_{YZ}\right)$, i.e., $\pm 2V_{dc}$, $\pm 1V_{dc}$, and $0V_{dc}$. The cascaded converter module has redundant switching-state combinations of $\pm 1V_{dc}$ and $0V_{dc}$ of the output voltage levels, which are listed in

Table 1. Switching modes of CCM.

Modes	Switching States			Capacitor	Capacitor	CCM V${}_{\mathit{out}}$
	${\mathit{S}}_{\mathit{a}}$	${\mathit{S}}_{\mathit{b}}$	${\mathit{S}}_{\mathit{c}}$	${\mathit{C}}_{\mathrm{1}}$	${\mathit{C}}_{\mathrm{2}}$	${\mathit{V}}_{\left(\mathit{YZ}\right)}$
Table (a)				when $i_a>0$
1	1	1	1	charge	charge	$2V_{dc}$
2	1	1	0	discharge	bypass	$V_{dc}$
3	0	1	0	bypass	by pass	0
4	1	0	0	bypass	charge	$-V_{dc}$
5	0	0	0	charge	charge	$-2V_{dc}$
Table (b)				when $i_a>0$
1	1	1	1	charge	charge	$2V_{dc}$
2	0	0	1	bypass	discharge	$V_{dc}$
3	1	0	1	bypass	bypass	0
4	0	1	1	charge	bypass	$-V_{dc}$
5	0	0	0	charge	charge	$-2V_{dc}$

.

The AC-side dynamics of the AHMMC system in Figure 1 are expressed by a switched equivalent circuit in (1)–(3):

$$\frac{d{i}_h}{dt}=\frac{1}{L}(S_x{V}_{Ch1}+S_y{V}_{Ch2}\mp S_{z}E\pm V_{gho})$$

(1)

$$\frac{d{V}_{Ch1}}{dt}=\frac{S_{x}i}{C_{h1}}$$

(2)

$$\frac{d{V}_{Ch2}}{dt}=\frac{S_{y}i}{C_{h2}}$$

(3)

where $V_{gho}=Esin\left(wt\right)$ is a grid voltage with a frequency of 50Hz, $S_{zh}$ is the switching sequence for the different phases to neutral voltage of the three-phase two-level converter [26], and $S_{xh}$ and $S_{yh}$ are the switching functions of the AHMMC (subscript h is either a, b, or c), which can be expressed by (4) and (5):

$$S_{xh}={\mathrm{S}}_{\mathrm{a}}{\mathrm{S}}_{\mathrm{b}}-{\mathrm{S}}_{\mathrm{a}}^{\prime }{\mathrm{S}}_{\mathrm{b}}^{\prime }$$

(4)

$$S_{yh}={\mathrm{S}}_{\mathrm{b}}{\mathrm{S}}_{\mathrm{c}}-{\mathrm{S}}_{\mathrm{b}}^{\prime }{\mathrm{S}}_{\mathrm{c}}^{\prime }$$

(5)

3. Hybrid Modulation Strategy

For any given topology, the strategy used for pulse-width modulation (PWM) plays a decisive role in the switch loss. For the PWM method, the number of voltage pulses at the output is achieved by reference voltage approximation. The present study’s emphasis is on the modulation scheme, which should be designed so that the switches with the highest voltage stresses operate at low switching frequencies and the low-stress switches operate at high frequencies. The PWM modulation strategy is divided into two parts: a PWM strategy for the three-phase converter and a PWM strategy for the per-leg CCM. Since the switches of the three-phase inverter are under higher voltage stress, they should be operated at the lowest frequency with the fewest pulses possible in each fundamental cycle. The CCM’s switches are classified according to their voltage stresses, followed by the elaboration of the middle-leg switches and the outer-leg switches in a section (III-C). The approach used to determine the timing of these pulses is to alternate the PWM techniques [17,18]. In the literature, the modulation methods studied for MMCs include fundamental switching-frequency PWM [27], carrier-based PWM [28,29], space-vector PWM [30,31,32], and selective harmonic elimination (SHE) PWM [13]. The SV-PWM-based technique is widely used in applications, such as motor control, electric vehicles, and grid interfacing, due to its many advantages [33,34,35].

3.1. Three-Phase Converter Modulation

Since the stress on the three-phase converter is higher, SHE-PWM and SV-PWM are studied as low-frequency-switching modulation techniques. The increased switching transitions per fundamental cycle increase the zero crossing requirements in the harmonic reference signal, which are compensated for by the per-leg CCM. In SHE-PWM, the switching transitions of five angles ($\alpha$1–$\alpha$5) in the first-quarter cycle of the fundamental period are optimally chosen to eliminate the first four lower-order non-triplen harmonics [36]. As a result, the switching losses associated with the middle leg of the cascaded converter increase. Figure 2 depicts a fundamental signal comparison of the phase voltage of the three-phase converter, which is achieved using the SHE-PWM and SV-PWM methods, for the harmonic compensation reference signal calculation. To target minimum switching effort, SV-PWM operating at 150 Hz is suggested.

Referring to Figure 3, for different switch combinations of the three-phase converter in Figure 1, the output state voltage vector is mapped to distinct active vectors V${}_1$–V${}_6$ in the alpha-beta coordinates. Additionally, the space vectors V${}_0$ and V${}_7$ are zero vectors with zero magnitudes located at the center of the hexagon. In the proposed SV-PWM method, a hexagon is split into three sectors: sector I, which contains two active vectors V${}_1$ and V${}_2$; sector II (V${}_3$ and V${}_4$), and sector III (V${}_5$ and V${}_6$). Considering sector I, V${}_1$ and V${}_2$ are applied to the on-time interval T1, and the zero vectors V${}_0$ and V${}_7$ are applied to the off-time interval T0, where the vector application time T1 and T0 are calculated in terms of angles and can be equated as:

$$T_1={120}^o\times M_f$$

(6)

$$T_0={120}^o\times (1-M_f)$$

(7)

where $M_f$ is the modulation index of the two-level three-phase converter. In this method, the active vectors are placed in the center between the symmetric zero vectors. For this modulation strategy, as an example of a particular vector at a modulation index m = 0.9, the waveform appears as depicted in Figure 3b. The converter’s fundamental component is kept in phase with the grid voltage and only the time interval (on and off time intervals) changes, which varies according to the modulation depth.

The maximum voltage requirement of the summated DC-link voltage ($V_{C1}$ + $V_{C2}$) for harmonic compensation also depends on the modulation strategy of the fundamental converter. To compare the DC-link requirement, SHE-PWM is considered another possible candidate to operate the fundamental converter switches with 500 Hz low-frequency switching. For different modulation depths, the results in Figure 4 show the DC-link capacitors’ voltage (in the CCM) to compensate for the harmonics. However, the selection of the SHE-PWM technique as the modulation strategy for the fundamental converter requires a higher DC-link capacitor voltage than the SV-PWM technique. Based on the above discussions, the SV-PWM technique (150 Hz switching frequency) is chosen as the modulation technique for the fundamental three-phase converter.

3.2. Modulation Range

Considering the SV-PWM modulation strategy, the maximum output voltage of the cascaded converter module also relies on the modulation index $M_f$ of the two-level three-phase converter, as expressed by Equation (8):

$$M_f={\displaystyle \frac{\sqrt{3}(\mid {\overline{V}}_{a{n}_{\left(ref\right)}}\mid )}{\mathrm{E}}}$$

(8)

where ${\overline{V}}_{a{n}_{\left(ref\right)}}$ is the reference voltage vector and E is the magnitude of the DC bus. Slightly modifying the modulation index range results in a high impact on the DC-link voltage requirement for harmonic minimization. Figure 4 depicts the maximum CCM modulation index (m) of 10% that can be achieved. The maximum modulation index m = 1.10 requires a DC-link capacitor voltage of ($\frac{1}{3}$)E (DC-bus voltage). As the modulation index of the fundamental converter decreases to m = 0.88, the sum of the DC-link voltages of 0.47E is required to minimize the harmonics produced by the fundamental converter, as shown in Figure 4. Reducing the DC-link voltage requirements for harmonic compensation minimizes the voltage stress on the semiconductor switches, which provides an advantage over varying the switching frequency according to the system design.

3.3. Cascaded Converter Module Modulation

The switches used in cascaded converter modules are classified into two groups: (i) high-voltage low-frequency switches, and (ii) low-voltage high-frequency switches. For the design aspect, the middle-leg switches ${\mathrm{S}}_{\mathrm{b}}$ and ${\mathrm{S}}_{\mathrm{b}}^{\prime }$ of the cascaded converter module in Figure 1 handle high-voltage stress, i.e., 2$V_{dc}$. As the third harmonic forms a zero sequence, the resulting zero crossing frequency of these switches is 550 Hz, resulting in reduced switch loss. The outer-leg switches of the cascaded converter module are under low stress, i.e., $V_{dc}$, and as a result, they are switched at four times the frequency of the middle-leg switches. To generate all the levels and fulfill the requirements of balancing the DC-link capacitor voltages, a phase opposition disposition (POD) PWM method is employed in the cascaded converter module, as shown in Figure 5. In this method, the carrier signals have a level shift and a phase shift across the zero references. The resulting equivalent frequency using this method is 3.2 kHz, with the highest effective frequency being 1.6 kHz, which results in further distribution of losses in the system.

The complete modulation strategy for the AHMMC is as follows: (i) the high-voltage three-phase converter offers fundamental component support and is run at a low switching frequency, and (ii) the CCM as a series-active filter compensates the high harmonics generated by the fundamental converter. The output of the CCM depends on the magnitude of the reference modulating signal, as shown in Figure 4. As the CCM acts as a series filter, the reference modulating signal for this module is obtained from the phase output voltage by subtracting its fundamental component. Here, the maximum modulation index is considered for the three-phase converter. Therefore, the resulting reference modulating signal for the CCM generates an output voltage of three levels, as shown in Figure 5. Figure 6 depicts the output voltage of the a-phase leg $V_{an}$ of the AHMMC at different switching angles, as shown in

Table 2. AHMMC output phase voltage $\left(V_{an}\right)$.

Angle	${\mathit{V}}_{\mathit{YZ}}$	${\mathit{V}}_{\mathit{an}}^{\prime }$	${\mathit{V}}_{\mathit{an}}={\mathit{V}}_{\mathit{YZ}}+{\mathit{V}}_{\mathit{an}}^{\prime }$
$0\le \theta \le {\theta }_1$	0	$\frac{1}{3}$E	$\frac{1}{3}$E
${\theta }_1\le \theta \le {\theta }_2$	$V_{dc}$	$\frac{1}{3}$E	$\frac{1}{3}$E+ $V_{dc}$
${\theta }_2\le \theta \le {\theta }_3$	0	$\frac{2}{3}$E	$\frac{2}{3}$E
${\theta }_3\le \theta \le \pi /2$	$V_{dc}$	$\frac{2}{3}$E	$\frac{2}{3}$E+ $V_{dc}$

.

The overall output phase voltage of the a-phase $V_{an}$ is mathematically expressed by Equations (9)–(11):

$$V_{an}=V_{an}^{\prime }+V_{YZ}$$

(9)

$$V_{an}^{\prime }={\displaystyle \frac{4}{3\pi }}\mathrm{E}\sum _r^{\infty }{\displaystyle \frac{1}{r}}(cos({\displaystyle \frac{\pi }{3}}r+{\theta }_f)+M_f)(sin\left(r\omega t\right))$$

(10)

$$V_{YZ}=V_{an}^{\prime }-\left({\displaystyle \frac{4}{3\pi }}\mathrm{E}(cos({\displaystyle \frac{\pi }{3}}+{\theta }_f)+M_f)(sin\left(\omega t\right))\right)$$

(11)

where ${\theta }_f$ is calculated from the off-time interval T${}_0$ of SV-PWM applied to the fundamental converter, which varies with the modulation depth $M_f$ of the fundamental converter, and r is the harmonic component.

4. Control Scheme

Despite the aforementioned merits, MMCs require many DC-link capacitors to generate a multi-level output. A challenge for MMCs irrespective of the module type used is the voltage balancing [37,38] needed to enhance the converter’s reliability. In order to tackle this issue, various methods have been proposed in the literature. Voltage balancing techniques among phase clusters are proposed in [39]. One method for voltage balancing is the independent control of each phase cluster’s active power [40]. Another proposed method involves DC-link voltage balancing using negative-sequence currents [41].

To track the proposed converter current and regulate the DC-link capacitor voltage to their respective reference values, a control algorithm is employed, which consists of decoupled, current-control, and voltage-control techniques. The decoupled voltage-control technique is further classified into control objectives, which are (i) the average voltage control between the three-phase converter and the CCM, (ii) inter-module energy balancing among the CCMs, and (iii) individual capacitor voltage balancing in the CCM. The functions of blocks A, B, C, and D shown in Figure 7 are summarized as follows: (i) block A: feed-forward fundamental component support, (ii) block B: harmonic signal extraction for the CCM, (iii) block C: zero-sequence voltage calculation, and (iv) block D: controlled current signal from the decoupled control loop.

4.1. Decoupled Current Control Loop

The effectiveness of a converter system is determined by the performance of current control; therefore, the current control is required to respond fast to transients and exhibit satisfactory steady-state behavior. Current control in the synchronous reference frame (SRF) ($dq$ coordinates) offers attractive features, which are widely known and applied in most PWM schemes [42,43].

In this study, the output voltage generated by each phase-cascaded converter module determines the converter current control that is in use. This control strategy’s primary goal is to provide the required voltage for the needed output current. The current control has two main paths: the feed-forward fundamental component support, which is provided by the three-phase converter, and the harmonic and fast current control support, which is provided by the cascaded converter module, as depicted in Figure 7. The decoupled current control loop in Figure 8 is applied to the cascaded converter modules, as these converter modules provide high-frequency support. Thus, the reaction will be faster if the grid voltages change abruptly.

Referring to Figure 1, the following current-voltage equation (12) is deduced by ignoring the resistive components.

$$\left[\begin{array}{c}V{g}_{a0}\\ V{g}_{b0}\\ V{g}_{c0}\end{array}\right]-\left[\begin{array}{c}{V}_{an}\\ V_{bn}\\ V_{cn}\end{array}\right]=L{\displaystyle \frac{d}{dt}}\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right]$$

(12)

The Park transformation matrix attaining the d-q components of the three-phase currents $i_a$, $i_b$, and $i_c$, and voltages $V_{an}$, $V_{bn}$, and $V_{cn}$ is provided in [42] and in (13) and (15) as follows:

$$T_{\mathrm{P}}=\sqrt{{\displaystyle \frac{2}{3}}}\left[\begin{array}{ccc}\sin \left(\omega t\right)& \sin (\omega t-\frac{2}{3}\pi )& \sin (\omega t+\frac{2}{3}\pi )\\ \\ \cos \left(\omega t\right)& \cos (\omega t-\frac{2}{3}\pi )& \cos (\omega t+\frac{2}{3}\pi )\end{array}\right]$$

(13)

Therefore

$$\left[\begin{array}{c}{v}_d\\ v_q\end{array}\right]=T_P\left[\begin{array}{c}{V}_{an}\\ V_{bn}\\ V_{cn}\end{array}\right]$$

(14)

$$\left[\begin{array}{c}{i}_d\\ i_q\end{array}\right]=T_P\left[\begin{array}{c}{i}_a\\ i_b\\ i_c\end{array}\right]$$

(15)

Considering a balanced three-phase voltage, $v_q$ will be zero as $\overrightarrow{V}$g is aligned with the d-axis. Applying the d-q transformation, the three-phase active and reactive power can be expressed by (16) and (17), respectively, as follows:

$$P={\displaystyle \frac{3}{2}}\left[\left(v_d{i}_d\right)+\left(v_q{i}_q\right)\right]$$

(16)

$$Q={\displaystyle \frac{3}{2}}\left[\left(v_q{i}_d\right)-\left(v_d{i}_q\right)\right]$$

(17)

which shows that by controlling $i_d$ and $i_q$ independently, the control of active/reactive power will be achieved. The current commands $i_d^{*}$ and $i_q^{*}$ of their respective axes are expressed by (18) and (19) as follows:

$$i_d^{*}=\frac{p^{*}}{v_d}$$

(18)

$$i_q^{*}=\frac{q^{*}}{v_q}=0$$

(19)

where $p^{*}$ and $q^{*}$ are the active and reactive power commands, respectively. Here, a strictly unity power factor is considered. $q^{*}$ = 0 guarantees the system operation at a unity power factor. The controlled reference signal is achieved by the inverse d-q transformation, as expressed in (20).

$$\begin{array}{c}\hfill \left[\begin{array}{c}{v}_d^{*}\\ v_q^{*}\end{array}\right]=\left[\begin{array}{c}{v}_d\\ 0\end{array}\right]+\left[\begin{array}{cc}0& -\omega L\\ \omega L& 0\end{array}\right]\left[\begin{array}{c}{i}_d\\ i_q\end{array}\right]+K_1\left[\begin{array}{c}{i}_d^{*}-i_d\\ i_q^{*}-i_q\end{array}\right]\\ \hfill +\frac{K_1}{T_1}\int \left[\begin{array}{c}{i}_d^{*}-i_d\\ i_q^{*}-i_q\end{array}\right]dt\end{array}$$

(20)

Applying the d-q to abc transformation gives the decoupled current controlled signals $V_{ai}^{*}$, $V_{bi}^{*}$, and $V_{ci}^{*}$ shown in Figure 8, which are applied to the cascaded converter modules shown in Figure 7.

The current control loop bandwidth relies on the PWM’s frequency in order to lessen the effect of distortion in the current resulting from abrupt voltage dips or swells in the grid. Equation (21) describes how the PWM is changed in the DC voltage feed-forward control loop to lessen the influence of DC-link voltage ripples:

$$\begin{array}{c}\hfill d=(a_1{\displaystyle \frac{|V_{out}|}{V_{c1}}}+a_2{\displaystyle \frac{|V_{out}|}{V_{c2}}}+a_3{\displaystyle \frac{|V_{out}|-V_{c1}}{V_{c2}}}\\ \hfill +a_4{\displaystyle \frac{|V_{out}|-V_{c2}}{V_{c1}}})\times Sign\left(V_{out}\right)\end{array}$$

(21)

where the duty ratio for the cascaded module output voltage levels is denoted by d and, $a_1$, $a_2$, $a_3$, and $a_4$ are the PWM output conditions given in

Table 3. PWM Operating Conditions.

Operating Condition	${\mathit{a}}_1$	${\mathit{a}}_2$	${\mathit{a}}_3$	${\mathit{a}}_4$
$V_{\mathrm{c}1}$ is a lower capacitor
$\mid V_{\mathrm{out}}\mid \le V_{\mathrm{c}1}$	1	0	0	0
$V_{\mathrm{c}1}<\mid V_{\mathrm{out}}\mid <(V_{\mathrm{c}1}+V_{\mathrm{c}2})$	0	0	1	0
$V_{\mathrm{c}2}$ is a lower capacitor
$\mid V_{\mathrm{out}}\mid \le V_{\mathrm{c}2}$	0	1	0	0
$V_{\mathrm{c}2}<\mid V_{\mathrm{out}}\mid <(V_{\mathrm{c}1}+V_{\mathrm{c}2})$	0	0	0	1

. The output direction of the PWM is determined by $Sign\left(V_{out}\right)$ in (22):

$$Sign\left(V_{out}\right)=\left\{\begin{array}{cc}1\hfill & \mathrm{if}{V}_{out}\ge 0\hfill \\ -1\hfill & \mathrm{if}{V}_{out}<0\hfill \end{array}\right.$$

(22)

4.2. Decoupled Voltage Control Loop

The imbalance of voltage in the DC-link capacitors in the per-phase cascaded module arises mainly due to the inaccuracy of the PWM gating signal over a cycle and the real component produced by the non-linearity of the semiconductor devices. To mitigate this balancing issue, a decoupled voltage balancing control is employed with the control objectives that are classified and discussed below.

4.2.1. Average Voltage Control

The sum of the charge across the average-mode DC-link capacitor ($V_{c1}\mathrm{and}{V}_{c2}$) in each phase of the cascaded module is finite. An energy exchange is required between the three-phase leg/inverter or grid to compensate for the total energy. The total sum of all the charges across these cascaded modules will decide the amount of energy that is required to be absorbed from the AC main or three-phase converter. As the fundamental component of the voltage is a positive sequence and the current is sinusoidal, the sign of the positive-sequence voltage will decide the direction of the energy exchange between the cascaded modules and the grid or three-phase converter. If the sum of the capacitors’ energies in the cascaded modules is less than the reference value, the energy will be absorbed from the three-phase converter or grid. If the energy is higher, it will transfer to the three-phase converter or grid. Therefore, average DC-link capacitor voltage balancing is attained through positive-sequence voltage. Figure 9a shows the average-mode DC-link capacitor voltage control loop. The reference signal for controlling the average-mode DC-link capacitor voltages per phase is given in (23):

$$\left[\begin{array}{c}△V_a\\ △V_b\\ △V_c\end{array}\right]=△V\left[\begin{array}{c}sin\left(\omega t\right)\\ \\ sin(\omega t-{\displaystyle \frac{2}{3}}\pi )\\ \\ sin(\omega t+{\displaystyle \frac{2}{3}}\pi )\end{array}\right]$$

(23)

To keep the sum of the capacitors’ energies in the cascaded modules balanced at the required value, the average sum of all the DC-link voltages of the cascaded modules is compared with the reference DC value. The error signal is given to a PI controller to attain a compensated $△V$ reference signal, which is deduced in (24)–(26):

$$E_c={\displaystyle \frac{1}{2}}C{\left({\displaystyle \frac{dV{c}_{avg}}{dt}}\right)}^2$$

(24)

$$V{c}_{avg}={\displaystyle \frac{1}{3}}\sum _{h=a,b,c}\sum _{l=1,2}V{c}_{hl}$$

(25)

$$△V={\left(Vre{f}_{\left(avg\right)\left(dc\right)}-V{c}_{avg}\right)}^{*}\left(K_2+{\displaystyle \frac{K_2}{s{T}_2}}\right)$$

(26)

4.2.2. Inter-Module Power Balancing

In practice, after transferring the average power, the AHMMC cannot be naturally balanced because of component parametric variances or different control signal delays, which inevitably cause unbalanced power among the cascaded modules. Redistributing the power among the cascaded module converters is carried out to address the uneven energy distribution. A corrective voltage control, i.e., difference-mode voltage control, is realized, which is dependent on injecting zero-sequence voltage. By implementing the difference-mode DC-link capacitor voltage control, power among the cascaded modules is exchanged by zero-sequence voltage injection, ensuring that the power will not appear at the output of the cascaded converter modules. Hence, the power is exchanged equally among the cascaded modules. The analysis of the difference-mode DC-link capacitor voltage control is shown in Figure 9b. The average active power due to the zero-sequence voltage can be calculated by (27) and (28):

$$P_{a0}+P_{b0}+P_{c0}=0$$

(27)

where

$$P_{a0}=V_0{e}^{j0}I{e}^{j0}$$

(28)

Similarly, the change in the power commands for the a-phase, b-phase, and c-phase can be expressed by (29):

$$\left[\begin{array}{c}△P_a^{*}\\ △P_b^{*}\\ △P_c^{*}\end{array}\right]=V_0{e}^{j0}I\left[\begin{array}{c}sin\left(\omega t\right)\\ \\ sin(\omega t-{\displaystyle \frac{2}{3}}\pi )\\ \\ sin(\omega t+{\displaystyle \frac{2}{3}}\pi )\end{array}\right]$$

(29)

The controlled converter currents, which are in phase with the grid voltage, are assumed to contain positive-sequence currents, and the power command in phasor form by the zero-sequence voltage is given by (30) and (31):

$$△P_a^{*}=Re\left[(V_a-j{V}_m)I_a\right]$$

(30)

$$△P_b^{*}=Re\left[(V_a-j{V}_m)I_b\right]$$

(31)

The zero-sequence voltage is calculated by comparing (30) and (31) and is given as follows:

$$V_0=\left(V_a-j{V}_m\right)$$

(32)

4.2.3. Individual Capacitor Voltage Balancing

Once the power is distributed equally among the cascaded modules, it is essential to balance each DC-link capacitor’s voltage to the desired reference, which is accomplished by the voltage swapping approach, which utilizes the redundant switching states shown in Table 1. Based on the relationship, redundant switching states are used for charge swapping:

• When $(i_{\left(hdc\right)}\times V_{Ch1})<0$, if $V_{Ch1}<V_{Ch2}$, Table 1 (b) will subsequently be chosen.
• When $(i_{\left(hdc\right)}\times V_{Ch2})>0$, if $V_{Ch1}>V_{Ch2}$, Table 1 (a) will subsequently be chosen.

where $i_{\left(hdc\right)}$ is the DC reference current direction (subscript h is either a, b, or c). The voltage balancing of the capacitors is accomplished using the relation of the selected tables mentioned above.

5. Simulation Results

A simulation of the AHMMC configuration shown in Figure 1 is performed in MATLAB/Simulink. Using the specifications mentioned in

Table 4. Proposed system’s parameters.

Parameter	Symbol	Value
Inductance	L	$0.7$ mH
DC-link Capacitor	C	20 mF
Cascaded Converter	PWM${}_{freq}$	$3.2$ kHz
Three-phase Converter	SW${}_{freq}$	150 Hz
Capacitor Voltage	Vc	110 $V_{dc}$
Grid Voltage (rms)	Vg${}_0$	110 V
Grid Current (rms)	I${}_s$	15 A
DC-bus Voltage	E	300 V

, the simulated findings from the research were scaled to the experimental results.

Extensive simulations were conducted to choose the components. Capacitors were chosen based on a peak–peak voltage ripple of 2%, whereas inductors were chosen for a peak–peak current ripple of 0.5% at the maximum rated current. A switching frequency of 3.2 kHz was chosen because the outer-leg switches on the cascaded converter module were under minimal voltage stress (1.6 kHz effective switching frequency). By operating the outer-leg switches of the cascaded converter modules $S_a$ and $S_c$ at a switching frequency of 3.2 kHz, the current ripple, inductor size, and overall system costs were minimized.

Figure 10 demonstrates the simulation waveforms of the single-leg phase-output voltage of the AHMMC topology. The output voltage V${}_{an}$ was obtained by adding the a-phase output voltage of the fundamental converter to the output voltage of the cascaded converter module. It is clear that the fundamental converter with high-voltage stress on the semiconductor devices was switched at a low frequency, whereas the cascaded converter module was switched at a high frequency to compensate for the harmonics produced by the fundamental converter.

Figure 11 shows the simulation results of the three-phase phase voltages. At the maximum modulation index M${}_f$ = 1 of the fundamental converter, the AHMMC topology generated an output voltage of seven levels. When the modulation index value was reduced to M${}_f$ = 0.9, the converter fundamental component was in phase with the grid voltage and only the sampling time changed, which varied with the modulation depth, as shown in Figure 12. Figure 13 shows the simulation results of the three-phase line voltages. The output line voltage of the AHMMC topology was $\sqrt{3}$V${}_{an}$, and at M${}_f$ = 1, it generated an output voltage of nine levels. Figure 14 shows the output line voltages when the modulation index value was reduced to M${}_f$ = 0.9.

Figure 15 shows the waveform of the proposed converter current. It is clear that the converter tracked its reference current, which was realized in the $dq$ reference coordinates. The current tracked the reference value I${}_{ref}$, even when it changed direction (180${}^{\circ }$ out of phase with the grid voltage) to ensure a bidirectional active power flow. Figure 16 shows the simulation results of the converter phase voltage and current with variations in the power transfer (when the amplitude of the reference current was changed from a 50% to a 100% converter rating).

A decoupled voltage control technique was applied to maintain the balance of the summated DC-link capacitor voltage in the cascaded module to its reference value. However, the DC-link capacitor voltage of the cascaded modules was not naturally balanced and was affected when the output terminal is connected through one of the DC-link capacitor terminals. The DC-link capacitor voltage in each cascaded converter module, V${}_{cn1}$ and V${}_{cn2}$ (subscript n is either a, b, or c), diverged from its reference value and entered into an over-charging/under-charging state, respectively. The individual DC-link capacitor voltage balancing in the cascaded converter modules was realized by the charge-swapping technique using the redundant switching-state selection, which converged the capacitor voltages to their respective reference values. Figure 17 depicts the simulation results of the balanced DC-link capacitor voltages of the cascaded converter modules. The balancing of the summated DC-link capacitor voltage, which was achieved by redistributing the power among the cascaded converter modules, is shown in Figure 17a. Initially, swapping was enabled that converged the DC-link capacitor voltage to its reference value. When the swapping of the cascaded converter module was disabled, the DC-link capacitor voltage deviated from its reference value, as shown in Figure 17b.

6. Experimental Results

Using a low-voltage laboratory prototype, as illustrated in Figure 18, the proposed converter and its modular control strategy were experimentally validated. A customized control board was built, which utilized a micro-controller unit (TMS320C28346 Delfino^TM), complex programmable logic device (EPM570 ALTERA^®), and AD conversion to realize the control in practice. It can be observed that all the experimental results are in good agreement with the results achieved in the simulation.

Figure 19 demonstrates the experimental results of the single-leg phase-output voltage of the AHMMC topology. The converter output voltage V${}_{an}$ was obtained by adding the a-phase output voltage of the fundamental converter to the output voltage of the cascaded converter module. Figure 20 shows the experimental results of the three-phase phase voltages. At the maximum modulation index M${}_f$ = 1 of the fundamental converter, the proposed AHMMC topology generated an output voltage of seven levels. Figure 21 depicts the experimental waveform of the output phase voltages at M${}_f$ = 0.9 in which the fundamental component of the converter was in phase with the grid voltage, and due to the variation in the sampling time, the modulation depth changed.

Figure 22 shows the experimental results of the three-phase line voltages. The output line voltage of the AHMMC topology was $\sqrt{3}$V${}_{an}$; therefore, at M${}_f$ = 1, it generated an output voltage of nine levels.

Figure 23 shows the experimental waveform of the proposed converter current. It can be seen that the converter tracked its reference value I${}_{ref}$, even when it changed direction (180${}^{\circ }$ out of phase with the grid voltage) to ensure the bidirectional active power flow.

Figure 24 depicts the experimental waveforms of the DC-link capacitor voltages of the CCMs connected to the a- and b-phase legs of the three-phase converter. Initially, the swapping in the a-phase cascaded converter module was disabled, which resulted in the deviation of the DC-link capacitor voltage from its reference value. When the swapping was enabled, the DC-link capacitor voltage converged to its reference value.

Figure 25 shows the experimental results of the converter phase voltage and current with variations in the power transfer (when the amplitude of the reference current was changed to a 100% converter rating).

Table 5. Converter current THD.

Current THD	Power Rating
Simulation	25%	50%	100%
	5.31	2.83	1.38
Experimental	7.2	5.33	4.21

presents the simulated and experimental current total harmonic distortion (THD) at various power ratings.

The proposed converter was compared with similar works in [44,45] in terms of the output voltage levels, required number of components, and THD percentage of harmonic content. The comparison is provided in

Table 6. Comparative analysis of converter topologies.

Converter System	Parameters
	V-Level	Switch	Diode	DC Source	Capacitor	Current THD
AHMMC	9	8	0	1	2	4.21%
MLI [44]	8	6	4	2	6	1.25%
MLI [45]	19	12	1	2	2	4.30%

.

It is evident from Table 6 that the performance of the proposed AHMMC is better than that in [45] in terms of the THD and those in [44,45] in terms of the component count.

7. Conclusions

A new topology for a three-phase AHMMC for a medium-voltage high-power front-end converter is proposed, which is a per-phase series arrangement of a high-voltage three-phase half-bridge converter with a low-voltage cascaded converter module. The proposed modular control scheme, which is a combination of control techniques, i.e., SV-PWM, POD-PWM, inter-module energy balancing through zero-sequence voltage, and active swapping, is employed to decrease the voltage stress on the converter, keep the DC-link voltage balanced, and track the current to its reference value. Furthermore, the active switches’ categorization of the proposed topology is performed according to the voltage stress: (i) high-voltage low-frequency switching, and (ii) low-voltage high-frequency switching. The features of the AHMMC topology include the minimization of the harmonic contents injected into the AC mains, a wider modulation range for the unity power factor, reduced conduction and switching losses, low DC-link capacitor voltage requirements for harmonic compensation, and the elimination of a bulky transformer. The detailed topology design and effectiveness of the modular control scheme are thoroughly examined. The efficiency and usefulness of the proposed topology are verified through simulation results, and experimental results via a customized laboratory prototype based on control and power boards are presented to validate the system in practice.