Analysis of Ruggedness of 4H-SiC Power MOSFETs with Various Doping Parameters

Abstract

This work investigates the effect of the doping concentration of SiC power metal-oxide–semiconductor field-effect transistors (MOSFETs) under an unclamped inductive switching (UIS) condition. Switching circuits such as inverters and motor-drive circuits often face unexpected operating conditions; therefore, a UIS test is performed to assess the avalanche ruggedness of the device, and design parameters such as the doping concentration should be considered to improve the UIS characteristics. Technology computer-aided design circuit simulation results, such as the current flows during failure and electrical changes, were obtained by changing the doping concentration of each region in the SiC power MOSFET.

1. Introduction

SiC power metal-oxide–semiconductor field-effect transistors (MOSFETs), which have the advantages of a higher thermal conductivity, smaller device size, lower power dissipation, and faster switching speed than Si devices, are widely used in power applications. However, switching circuits such as traction inverters may lead to device instability and an abnormal operation when a circuit operates in the high-power condition for a long time. Additionally, device structural parameters such as the p-base, N+ source, and P+ source doping can influence the device robustness under unexpected operating conditions such as with unclamped inductive switching (UIS). It is, therefore, necessary to evaluate their ruggedness and to understand their failure mechanisms under abnormal operating conditions. In this work, their characteristics are analyzed through technology computer-aided design (TCAD) circuit simulations. By varying the doping concentration of the p-base, N+ source, and P+ source regions, the ruggedness of the device under the avalanche mode can be improved [1,2,3,4,5,6,7,8,9].

2. Materials and Methods

2.1. Unclamped Inductive Switching (UIS) Circuit Test

Figure 1 illustrates the unclamped inductive switching (UIS) test circuit. This circuit was used to assess the avalanche ruggedness of the device. As shown in Figure 2a, when the device under test (DUT) was turned on by a single gate pulse ($t_{on}$), the inductor current gradually increased, and the device temperature rose by joule-heating during a $t_{on}$, as shown in Figure 2b. When the DUT turned off, the power MOSFET entered the avalanche mode in which the $V_{DS}$ increased to a value close to the breakdown voltage, and the current flowed to the load devices to eliminate the inductor current. However, there was no load device in the UIS circuit and the inductor current was entirely terminated in the DUT. The electrons remaining in the p-base and the holes, which were the majority of carriers in the p-base region, underwent a recombination, and the current was gradually decreased. The blocking voltage increased until the recombination was completed, as shown in Figure 2c [10].

2.2. Device Failure Mechanisms

The Si power MOSFET failed when the parasitic bipolar junction transistor (BJT) was activated. The body diode and the parasitic BJT are shown in Figure 3. The voltage drop between the base-emitter ($V_{BE}$) for the parasitic Si NPN BJT was approximately 0.7 V. When the temperature increased, the $V_{BE}$ decreased gradually until the parasitic BJT was activated [11]; however, the $V_{BE}$ for the parasitic SiC NPN BJT was approximately 2–3 V, and the BJT activation due to the temperature increasing was not a main reason for the device failure. As discussed in Section 2.1, when the DUT was turned-off, the blocking voltage increased until the recombination was completed; however, if the DUT had been turned on for a longer time, too many electrons could have remained in the p-base region. Then, the avalanche breakdown that caused the failure of the DUT may have occurred before the electrons remaining in the p-base region were completely recombinated with the holes. As shown in Figure 4a, the inductor current increased when the DUT failed, and the $V_{DS}$ went to zero. Additionally, the temperature of the device increased, as shown in Figure 4b [12,13].

2.3. Device Description

Figure 3 illustrates the structure of a 1.7 kV 4H-SiC MOSFET. The MOSFET was designed using the Sentaurus TCAD simulation tool. The drift-layer doping concentration ($N_{\mathrm{Drift}}$) and drift thickness ($t_{\mathrm{Drift}}$) for a breakdown voltage of 1.7 kV were $0.97\times {10}^{16}{\mathrm{cm}}^{-3}$ and $13.4\mathsf{\mu }\mathrm{m}$, respectively. To decrease the junction field-effect transistor (JFET) resistance and threshold voltage, the JFET and channel region were implanted [14]. The doping concentrations of the JFET, p-base ($N_{Pbase}$), $N^{+}$ source ($N_{N+}$), and ${\mathrm{P}}^{+}$ source ($N_{P+})$were $8\times {10}^{17}$, 6$\times {10}^{18}$, $1\times {10}^{20}$, and $1\times {10}^{20}{\mathrm{cm}}^{-3}$, respectively. The depths of the p-base, $N^{+}$ source, and ${\mathrm{P}}^{+}$ source were $1.0$, $0.2,$ and $0.4\mathsf{\mu }\mathrm{m}$, respectively. The ranges of the $N_{Pbase}$, $N_{Nsource}$, and $N_{Psource}$ values were from $3\times {10}^{18}$ to $9\times {10}^{18}$, $3\times {10}^{19}$ to $1\times {10}^{20}$, and $3\times {10}^{19}$ to $1\times {10}^{20}{\mathrm{cm}}^{-3}$, respectively. These values were used to analyze the failure of the 4H-SiC power MOSFET.

3. TCAD Simulation Results

In the thermal dynamic simulation, the temperature affected the device. When the current flowed to the device, the temperature increased owing to Joule heating. It was essential to consider the heat capacity for more accurate circuit simulations, although increasing the temperature was not a main reason for the device failure. Research was conducted on the thermal dynamic physics, with the heat capacity C given by:

$$C=a+bT+c{T}^2+d{T}^3,$$

(1)

where a, b, c, and d are the fitting parameters. The experimental data for the heat capacity are listed in

Table 1. Experimental Data of Thermal Dynamic Parameter.

Heat Capacity
a	$1.5778\left[\mathrm{J}/\left(\mathrm{K}·{\mathrm{cm}}^3\right)\right]$
b	$3.5332\times {10}^{-3}\left[\mathrm{J}/\left({\mathrm{K}}^2·{\mathrm{cm}}^3\right)\right]$
c	$-1.5447\times {10}^{-6}\left[\mathrm{J}/\left({\mathrm{K}}^3·{\mathrm{cm}}^3\right)\right]$
d	$2.6052\times {10}^{-10} \left[\mathrm{J}/\left({\mathrm{K}}^4·{\mathrm{cm}}^3\right)\right]$

[15].

3.1. UIS Circuit Simulation for 4H-SiC Power MOSFET

The UIS circuit was designed using MixedMode TCAD simulations. The inductance was $1\mathrm{mH}$, the DC power supply voltage ($V_{DD}$) was $400\mathrm{V},$ and the maximum voltage of the gate pulse was $15\mathrm{V}$. Figure 5a illustrates the $V_{DS}$ for various $t_{\mathrm{on}}$ to search for the failure point. When the DUT was completely turned off, the $V_{\mathrm{DS}}$ went to $V_{DD}$ and the $I_{DS}$ decreased gradually before finally approaching zero before failure. When the $t_{on}$ was $151\mathsf{\mu }\mathrm{s}$, the device failed, as shown in Figure 5b [16].

3.2. UIS Circuit Simulation for Various Doping Concentrations

3.2.1. P-Base Region

Figure 6a shows the $V_{\mathrm{DS}}$ for the various p-base doping concentrations ranging from $3\times {10}^{18}$ to $9\times {10}^{18}{\mathrm{cm}}^{-3}$. As the $N_{pbase}$ increased, the inductor current was completely removed, as shown in Figure 6b. This can explain why the holes in the p-base region underwent a complete recombination with the electrons remaining in the p-base region; however, in the case of the $N_{pbase}$ of less than $6\times {10}^{18}{\mathrm{cm}}^{-3}$, the holes were not sufficient for a full recombination. After the recombination was completed, the electrons remained in the p-base. Finally, the parasitic BJT was turned on and the current flowed across the p-base region, as shown in Figure 7 [17].

3.2.2. P⁺ Source Region

Figure 8a shows the $V_{\mathrm{DS}}$ for the various p-base doping concentrations ranging from $3\times {10}^{19}$ to $1\times {10}^{20}{\mathrm{cm}}^{-3}$. As the $N_{P+}$ decreased, the DUT failed more rapidly, as shown in Figure 8b. The $P^{+}$ source region also recombined with the electrons remaining in the p-base region; however, the holes in the p-base and $P^{+}$ source regions were not sufficient for a full recombination with the electrons, owing to the decreased $N_{P+}$. The parasitic BJT was turned on and the current that flowed across the p-base region increased gradually, as shown in Figure 9.

3.2.3. N⁺ Source Region

Figure 10a shows the $V_{DS}$ for the various p-base doping concentrations ranging from $3\times {10}^{19}$ to $1\times {10}^{20}{\mathrm{cm}}^{-3}$. As the $N_{N+}$ increased, the failure of the DUT occurred more rapidly, as shown in Figure 10b. This can explain why the depletion region between the $N^{+}$ source region and p-base region spread more widely to the p-base region. In addition, the holes in the p-base region diffused to the depletion region. This indicates that the holes in the p-base were not sufficient for a full recombination with the electrons. The parasitic BJT turned on and the current that flowed across the p-base region increased gradually, as shown in Figure 11.

4. Conclusions

The UIS TCAD circuit simulation was performed for various doping concentrations of each region of a SiC MOSFET device. The higher doping concentration of the p-base and $P^{+}$ source regions, were lower than that of the $N^{+}$ source region, making the device more stable under the UIS condition. It should be noted that, for the design of the power MOSFET, not only the static characteristics could be considered but also the dynamic characteristics of the device which are used in power applications, such as in a traction inverter. Additionally, the avalanche ruggedness of the device could be expected before the UIS test. Additionally, the circuit design should be investigated by connecting extra free-wheeling diodes to improve the dynamic characterization of SiC power MOSFETs and future device technologies.