A 300-mV ΔΣ Modulator Using a Gain-Enhanced, Inverter-Based Amplifier for Medical Implant Devices

Abstract

An ultra-low-voltage low-power switched-capacitor (SC) delta-sigma (ΔΣ) modulator running at a supply voltage as low as 300 mV is presented for biomedical implant devices, e.g., cardiac pacemakers. To reduce the supply voltage, an inverter-based amplifier is used in the integrators, whose DC gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full input-feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. To demonstrate the concept, a second-order loop topology was chosen. The entire modulator operates reliably against process, voltage and temperature (PVT) variations from a 300 mV ± 10% supply voltage only, while the switches are driven by a charge pump clock boosting scheme. Designed in a 65 nm CMOS technology and clocked at 256 kHz, the simulation results show that the modulator can achieve a 64.4 dB signal-to-noise ratio (SNR) and a 60.7 dB signal-to-noise and distortion ratio (SNDR) over a 1.0 kHz signal bandwidth while consuming 0.85 μW of power.

1. Introduction

Supply voltage reduction, as a direct consequence of the process technologies’ scaling, is further enforced by battery-operated biomedical implant devices, such as pacemakers, cardiac defibrillators and neural recording integrated circuits, to make their operating supply compatible with human body potentials [1,2], in the range of few hundreds of mVs. Therefore, designing analogue-to-digital converters (ADCs) operating at a very low supply voltage is inevitable for the measurement of various electrophysiological signals (e.g., ECGs, EEGs, etc.).

Pacemakers need to sense the cardiac signals, which mainly are situated in very low frequencies from nearly DC to several hundred hertz [3,4,5,6,7]. The cardiac signals are sensed by the low-noise amplifier, amplified by a gain stage; the undesired interferences are filtered out, and then, the detected analog signal is digitized by a back-end ADC. The ADC architecture and circuit design play a key role in maintaining ultra-low-power efficiency while providing a high conversion accuracy (or resolution). ADC resolutions from eight bit to 13 bit have been reported previously [5,6,7]. The low frequency noise, including flicker noise, needs to be treated properly in the circuit implementation.

There are two critical factors that can determine the lowest operating power supply of the traditional sigma-delta (ΔΣ) modulators: operational transconductance amplifiers (OTAs) in the integrators and the adequate driving voltage of the switching transistors [8,9,10,11,12,13,14]. The conventional analog circuit topologies are no longer practical in ultra-low-voltage operations (below 0.6 V), and also, stacking more than two transistors is impossible due to the limited overdrive and voltage headroom. The inverter is the simplest amplifier, which can sustain a supply voltage of less than the sum of the absolute threshold voltages of the NMOS and PMOS transistors [12], also known as a Class-C inverter. The DC gain and gain-bandwidth product (GBW) of the CMOS inverter degrade significantly at supplies far below the nominal V_TN + |V_TP| = 0.62 V and need to be enhanced for a robust and high-performance modulator design. Chae and Han [12] proposed an inverter-based ΔΣ modulator using a cascode inverter for boosting the DC gain. In this paper, we present a fully-differential second-order feedforward ΔΣ modulator for ultra-low-voltage low-power biomedical applications, which uses a novel gain-enhanced inverter-based, current mirror amplifier to replace the OTA in the integrators. Moreover, a clock boosting scheme is used to sufficiently drive the switching transistors. While all transistors operate at gate voltage less than 300 mV, the effective gate voltage of the switches is 600 mV with the aid of a charge pump clock doubler [13]. The single-bit quantizer, including the preamplifier, dynamic comparator and latch, was designed in a deep sub-threshold regime, providing very high power efficiency.

The rest of the paper is organized as follows: Section 2 describes the proposed gain-enhanced inverter-based amplifier and its advantages and drawbacks. Section 3 discusses the modulator architecture and its low-voltage and low-power design considerations. Section 4 presents the modulator circuit design. Section 5 discusses the simulation results. In Section 6, the proposed modulator is compared to the reported state-of-the-art ultra-low-voltage modulators. Conclusions are drawn in Section 7.

2. Proposed Gain-Enhanced Inverter-Based OTA

A novel inverter-based amplifier is proposed for ultra-low-voltage applications, which is composed of a Class-C inverter and a current mirror output stage. Figure 1 shows the schematics of the basic CMOS inverter, the cascode inverter and the proposed inverter-based, current mirror OTA (Figure 1c).

A switched-capacitor (SC) biasing scheme using floating capacitors C_bp and C_bn (Figure 1c) is used to define the operating point of the inverter M₁–M₂. These capacitors are periodically refreshed by the bias voltages Vbn and Vbp during the sampling phase Ф_Sam (Ф_Sam = Ф_1d in the first integrator; Ф_Sam = Ф_2d in the second integrator) and work as floating batteries between the input and the gates of the transistors. It is worth mentioning that the pre-charging Vbn and Vbp occurs simultaneously with sampling the signal onto C_S1 (C_S2) and the inverter offset onto C_C1 (C_C2) in phase Ф_Sam (Figure 4). The sampling clock speed is low (i.e., 256 kHz), so initially, the C_bp = C_bn = 0.5 pF are charged in the early phase of Ф_Sam (C_bp = C_bn << C_Ci), and then, the amplifier is placed in the unity feedback configuration for offset sampling when its biasing was set appropriately. The Vbp and Vbn are generated using a constant-g_m biasing circuit followed by a level shifter to eliminate the V_sat problem as in [15], which provides wider overdrive voltage and, in turn, a smaller transistor width. At the output stage, an energy-efficient SC common-mode feedback (CMFB) circuit is employed [8], which derives the gate of PMOS transistor M₅, in order to set the output CM level at the middle of the supply voltage for the maximum output swing.

The DC gain and GBW of the CMOS inverter degrade significantly at supplies far below the nominal V_TN + |V_TP|, which need to be enhanced for a robust and high-performance modulator design. The aim of the proposed technique is to boost the gain and GBW simultaneously by mirroring a small fraction (~10%) of the bias current of the inverter M₁–M₂ through transistor M₃ to the output. The factor k is the current ratio of the current mirror M₃–M₄ and is defined as (W/L)_M4/(W/L)_M3. The approximate gain and GBW of the proposed amplifier shown in Figure 1c can be determined from its small-signal model using sub-threshold current as:

$$A_{en}=\frac{g_{m1}+g_{m2}}{g_{m3}+g_{ds1}+g_{ds2}+g_{ds3}}.\frac{g_{m4}}{g_{ds4}+g_{ds5}}$$

$$\cong (g_{m1}+g_{m2})\times k\times R_{out}$$

(1)

$$GBW=\frac{k\times (g_{m1}+g_{m2})}{2\mathit{\pi }{C}_L}=\frac{k(2-\mathit{\alpha })I_{D2}}{2\mathit{\pi }{C}_{L}n{V}_T}$$

(2)

where g_mi and g_dsi represent the transconductance and output conductance of the i-th transistor, respectively. R_out is the total output resistance, which is equal to (g_ds4 + g_ds5)⁻¹. C_L is the total load capacitor for the frequency compensation. n and V_T are the sub-threshold parameters. We consider α = I_D3/I_D2 as the ratio of the currents of M₃ and M₂. In addition, it can be shown that the term g_m4/(g_{m3 +} g_ds1 + g_ds2 + g_ds3) is approximately equal to k. A large device size of M₁–M₂ has to be prevented, as it creates large parasitic capacitors, which can limit the amplifier speed.

To explain the gain-enhancement technique, the DC gain of the basic inverter (Figure 1a) and the proposed amplifier (Figure 1c) given by Equation (1) can be written in the following forms in Equations (3) and (6):

$$A_0=(g_{m1}+g_{m2})R_{out}=\frac{2I_D}{n{V}_T}\times \frac{1}{\mathit{\lambda }{I}_D}=\frac{2}{n\mathit{\lambda }{V}_T}$$

(3)

V_T is the thermal voltage; n is the non-ideality factor; and λ is the channel length modulation coefficient. A₀ is the intrinsic gain achieved by an inverter in the sub-threshold regime. In deep submicron technologies, by shrinking the transistor length, the effect of channel length modulation becomes more important. As a consequence, the output resistance and, thus, the DC gain of the inverter are normally low.

In Figure 1c, the bias current of the diode-connected device (i.e., I_D3) is equal to α I_D2, where α in this design is approximately 0.1. The M₁ transistor then shunts the rest of the current to the ground. Assuming M₁ carries (1 − α) × I_D2, from Equation (1), the gain of the proposed OTA can be expressed as:

$$A_{en}=(g_{m1}+g_{m2})\times k\times R_{out}=\left[\frac{(1-\mathit{\alpha })I_{D2}}{n{V}_T}+\frac{I_{D2}}{n{V}_T}\right]\times k\times \frac{1}{{\mathit{\lambda }}_4{I}_{D4}}$$

(4)

Now, the biasing current of M₄ is:

$$I_{D4}=k\times I_{D3}=k\times \mathit{\alpha }{I}_{D2}$$

(5)

Finally, the enhanced gain of the OTA is given by:

$$A_{en}=\frac{2-\mathit{\alpha }}{2\mathit{\alpha }}\times \frac{2}{n\mathit{\lambda }{V}_T}=(\frac{1}{\mathit{\alpha }}-0.5)A_0$$

(6)

From Equation (6), it can be seen that the gain is enhanced (1/α − 0.5)-times. The gain increase can be adjusted by the α factor during the design. With α = 0.1 in this design, the gain can be enhanced 9.5-times directly from Equation (6). With α = I_D3/I_D2 as the ratio of the currents in M₃ and M₂, the current mismatch can affect the gain enhancement (Section 2.2). In typical corner simulation from a 0.3 V supply, the α factor is about 0.12, which corresponds to a gain enhancement of eight-times, whereas in the worst-case corner, it is approximately 0.13, corresponding to a gain enhancement of seven-times.

Figure 2a shows the variations of the DC gain with respect to the supply voltage (V_DD) for the basic inverter shown in Figure 1a and the gain-enhanced inverter shown in Figure 1c. Figure 2b,c also shows the variations of the GBW as a function of the V_DD for both the basic inverter and the gain-enhanced inverter. For PMOS transistor M₂, the overdrive voltage (i.e., V_DD − Vbp − |V_TP|) depends on V_DD and increases by increasing V_DD. Similarly, for NMOS device M₁, the overdrive voltage (i.e., Vbn − V_TN) is enhanced linearly with V_DD to accommodate a wider input linear range in this analysis.

For V_DDs far below V_TN + |V_TP|, the DC gain and GBW degrade significantly. A large device size in M₁–M₂ has to be avoided, as this creates large parasitic capacitances, which can limit the OTA performance. The aim of this work is to enhance the gain and GBW simultaneously by mirroring a small fraction of the bias current of the inverter M₁–M₂ to the output stage (with α ~ 10% and k = 8).

Shown in Figure 2, with the current mirror gain-enhancement technique, the simulated DC gain and GBW increase to 40 dB and 1.9 MHz from 22 dB and 0.38 MHz, respectively, from a 0.3 V supply and a 3 pF load capacitance in a typical (TT) process corner, at 27 °C. The phase margin is 66 °C. The transistors sizes of the developed inverter-based current mirror amplifier are summarized in

Table 1. Transistor aspect ratios and bias setting for the gain-enhanced current mirror inverter amplifier in a 65 nm CMOS.

Transistor	W/L (µm/µm)
M1	1/0.8
M2	9/0.8
M3	2/0.2
M4	16/0.2
M5	5/0.25
Capacitor	Value (pF)
Cbn = Cbp	0.5
CLoad	3.0

. The DC gain gets worse in FS (fast NMOS, slow PMOS) and SF (slow NMOS, fast PMOS) process corners (i.e., 37 dB at V_DD = 0.3 V), whereas its deviation is trivial for FF and SS corners (i.e., 39 dB at V_DD = 0.3 V).

In practice, the gain enhancement can be restricted by several factors: phase margin, matching of bias currents between the M₁ and M₃ transistors and thermal noise. These factors are discussed below.

2.1. Frequency Response and Internal Parasitic Pole

Using the gain-enhancement technique increases the impedance of the internal node at the gate of the diode-connected M₃. The total parasitic capacitance at this node is represented by C_P in Figure 1d. The parasitic non-dominant pole due to the impedance 1/g_m3 of the transistor M₃ operating in the sub-threshold regime and the parasitic capacitor C_P can be expressed as:

$$P_{nd}=\frac{g_{m3}}{2\mathit{\pi }{C}_P}=\frac{\mathit{\alpha }{I}_{D2}}{2\mathit{\pi }{C}_{P}n{V}_T}$$

(7)

where C_P is approximately C_gs3 + C_gs4. To maintain a reasonably safe phase margin, the P_nd has to be placed more than three-times the unity GBW given by Equation (2). Thus, the following criteria for α can be derived with respect to C_P/C_L and k:

$$\frac{1}{\mathit{\alpha }}-0.5\le \frac{1}{6k}\frac{C_L}{C_P}$$

(8)

Recalling (1/α − 0.5) in Equation (6) as the gain-enhancement factor, Equation (8) represents the maximum gain-enhancement that can be achieved by the proposed technique. The larger the C_L/C_P, the greater is the gain enhancement and the phase margin, but this costs more power. The dominant pole in this design is set by C_L, which can be expressed by:

$$P_1=\frac{1}{2\mathit{\pi }{R}_{out}{C}_L}=\frac{g_{ds4}+g_{ds5}}{2\mathit{\pi }{C}_L}$$

(9)

2.2. Bias Current Matching

As described earlier, the ratio of the bias currents of transistors M₃ and M₂, defined as α = I_D3/I_D2, plays an important role for enhancing the amplifier gain given by Equation (6). Practically, the matching between I_D3 = α I_D2 and I_D1 = (1 − α) I_D2 determines the real α factor and, thus, the gain enhancement. To ensure good matching between those currents, the gate bias voltages of M₁–M₂ both are generated from the same reference current source using current mirrors. For good matching, transistors should be sized properly.

2.3. Thermal Noise

A drawback of the gain-enhanced, inverter-based amplifier, as compared to the basic CMOS inverter, is that it exhibits more input-referred thermal noise, related to the g_m3 of the device M₃. Since the correlated double-sampling (CDS) technique, as an auto-zeroing technique, is used in the corresponding integrator, the low frequency flicker noise is attenuated at the cost of an increased white noise floor due to the noise folding accompanied by the sampling [16]. The foldover thermal noise of the integrator is the dominant source of the noise, in which the thermal noise is amplified by a factor GBW/f_S, with sampling frequency f_S [16]. As a result, the input-referred noise power of the Class-C inverter and the gain-enhanced inverter shown in Figure 1c, denoted by GE-inv, can be expressed, respectively, as:

$$\overline{V_{n-fold,inv}^2}=\frac{GBW}{f_s}.\frac{4kT\gamma }{g_{m1}+g_{m2}}\left[v^2/Hz\right]$$

(10)

$$\overline{V_{n-fold,GE-inv}^2}=\frac{GBW}{f_s}.\frac{4kT\gamma }{g_{m1}+g_{m2}}(1+\frac{g_{m3}}{g_{m1}+g_{m2}})\left[v^2/Hz\right]$$

(11)

where the noise of the gain-enhanced amplifier has an additional term corresponding to g_m3. Therefore, M₃ has to be sized carefully, such that the thermal noise is minimized and the non-dominant pole, i.e., g_m3/2πC_P with C_P the parasitic capacitance at the gate of M₃ and M₄, is placed more than 3× the GBW for a reasonably safe phase margin.

3. Modulator Architecture

Output swing is of great importance in ultra-low-voltage low-power designs, which directly determines the modulator dynamic range (DR) and, ultimately, the power consumption. The minimum swing V_swing that the amplifier shown in Figure 1c can still operate with imposes a hard limit equal to 2V_sat + V_swing for the supply voltage scaling, with saturation voltage V_sat. The limited voltage swing is therefore translated into the demanding requirement of a low-swing loop topology. Compared to the traditional feedback topology, the full input-feedforward architecture suggests the integrators to process only the quantization error, thereby reducing the integrators’ swing considerably [17]. This is beneficial for the amplifiers’ relaxed requirements for slew-rate. Figure 3a shows the input-feedforward loop architecture for a second-order modulator. Half-cycle delay integrators are adopted in this structure to realize the CDS scheme for the inverter’s offset cancellation. The loop coefficients were optimized with behavioral simulations as (a₁ a₂ c₁ c₂ c₃) = (0.1 0.6 1 7 1). The coefficients are determined from the loop stability constraint, the maximum linear swing of the integrators and the required SNR. Figure 3b depicts the magnitude of the signal transfer function (STF) and the noise transfer function (NTF) of the target modulator. As expected, the STF is unity, and the NTF has a 40 dB/dec noise suppression in the baseband.

The single-bit quantizer is inherently linear. A multi-bit quantizer is not preferable for the low power and moderate resolution in this application, because the internal DAC becomes nonlinear, requiring dynamic element matching (DEM) or other complementary techniques for DAC linearization, which increase the hardware complexity and, thus, the total power consumption.

4. Modulator Circuit Design and Building Blocks

In this section, the details of modulator circuit design and its building blocks are discussed.

4.1. Modulator Circuit

Figure 4 shows the schematic of the designed second-order SC ΔΣ modulator using the proposed pseudo-differential integrators. The SC CMFB circuit is not shown and is omitted for simplicity. The proposed inverter-based amplifier in feedback configuration does not provide a virtual ground at the integrator input, because it has only one input terminal (Figure 1c). Combined with the CDS technique to cancel out the input offset and to attenuate the 1/f noise [16], two instances of the designed inverter-based amplifier are used to realize a pseudo-differential integrator with a virtual ground. There is a half-cycle delay between the integrators, i.e., when the first integrator samples the input onto C_S1 and the offset of the inverter onto C_C1, the second integrator is in charge transfer phase and vice versa. Since all feedforward paths have to create full delay paths according to Figure 3a, a half-cycle delay element is inserted in the internal feedforward path using SC implementation.

The summation of the feedforward paths is realized by the parallel capacitor branches at the quantizer input by using an SC passive network. The feedforward architecture is preferable due to its relaxed OTA’s performance requirements and low internal swings.

4.2. Low-Voltage Clocking and Clock-Boosting Circuitries

Figure 5 shows the non-overlapping clock generation circuitry used to provide the clock timing required by the modulator. The entire circuit employs low-V_TH low-power (LVTLP) devices enabling operation at 300 mV. The transistor aspect ratios of the CMOS inverters and the output buffers are specified in µm/µm in the figure. The aspect ratios of the CMOS NAND gate for PMOS and NMOS devices are 0.24 µm/1.5 µm and 0.135 µm/1.5 µm, respectively. In order to open and close the switches properly, they are implemented as transmission gates with low-V_TH transistors, driven by an ultra-low-voltage charge-pump clock doubler [13].

Figure 6 shows the schematic of the clock boosting circuit, which is composed of a charge-pump voltage doubler with two cross-coupled NMOS devices, two capacitors as large as 5 pF and two inverters as the buffer and level shifter. Low-V_TH devices were employed in the charge-pump circuit and level shifters for low voltage operation at 300 mV. The Ф1L and Ф2L are two non-overlapping clocks generated by the circuit in Figure 5 with a voltage level equal to 0.3 V, whereas Ф1H and Ф2H are level shifted up to 0.6 V. Hereafter, for simplicity, we denote Ф1H and Ф2H as Ф1 and Ф2, as in Figure 4. In a similar way, the Ф1d and Ф2d are generated and level shifted.

4.3. Ultra-Low-Voltage Sub-Threshold Quantizer

The single-bit quantizer is implemented using a dynamic comparator preceded by a single-stage preamplifier, as shown in Figure 7.

Table 2. Transistor aspect ratios of the clocked comparator and latch designed in the sub-threshold regime.

Transistors in Comparator	W/L (µm/µm)
M1a/M1b	8/0.18
M2a/M2b	4/0.18
M3a/M3b	3/0.18
M4a/M4b	25/0.18
M5a/M5b	30/0.18
Transistors in Latch	W/L (µm/µm)
M6	1/0.18
M7	0.5/0.18
M8	1/0.18
M9	1/0.18

summarizes the transistors dimension in µm. At a 0.3 V supply, the regular preamplifier and comparator circuits do not function properly in the strong inversion.

The input signals have a common-mode level equal to 0.15 V (i.e., V_DD/2), which is not adequate to turn on the input transistors. The threshold voltage of the used low-V_TH transistors in this technology itself is more than 0.15 V. On the other hand, stacking more than three transistors is impractical. Therefore, the single-bit quantizer (including the preamplifier circuit and the dynamic comparator and latch) is designed in the deep sub-threshold regime, providing very high power efficiency. The entire circuit dissipates only 6 nW, while clocked at 256 kHz. The quantizer operating at 0.3 V ± 10% was simulated against process, voltage and temperature (PVT) variations. It is capable of detecting an input signal as low as 200 µV, whereas the modulator’s least significant bit (LSB) is 300 µV for a full-scale reference voltage of 300 mV and 10 bit resolution.

The gain of the preamplifier degrades to 5 dB at a 0.3 V supply. Thus, it employs a gain-enhanced positive feedback in order to boost the low-frequency gain [2]. The preamplifier exploits low-V_TH transistors, providing more headroom for ultra-low voltage operation. For robust function against PVT variations, the effect of mismatch and process variations over DC gain was simulated using Monte Carlo analysis. Figure 8a shows the histogram of the DC gain for 5000 runs, which demonstrates the mean value of 10.55 dB. The frequency response was also simulated for 1000 runs, as depicted in Figure 8b. The worst-case DC gain in this plot is more than 9 dB.

5. Simulation Results

The proposed 0.3 V delta-sigma modulator was designed and simulated in a 65 nm CMOS process. Figure 9 shows the output power spectrum for a −2 dB full-scale (dBFS), 226 Hz sine-wave input. Figure 10 shows the power spectrum for a 960 Hz input, near the signal bandwidth edge, with a full scale input amplitude (i.e., 0 dBFS). The differential input signal range is 500 mV_pp. The modulator performance is simulated against process corners and 10% supply voltage variations, the achieved worst-case peak SNR and SNDR are 64.4 dB and 60.7 dB, respectively, within a 1.0 kHz signal bandwidth with a 256 kHz sampling clock frequency. The total power consumption from a 0.3 V power supply is 0.85 μW, in which the digital power is only 9%, including clock generation and clock boosting circuitries. Figure 11 presents the modulator SNDR versus the input differential amplitude in dBFS. The performance metrics are summarized in

Table 3. Simulated performance results.

Metrics	Simulated Value
Supply voltage	0.3 V
Technology	65 nm CMOS
Clock frequency	256 kHz
Signal bandwidth	1 kHz
Differential input range	0.5 Vpeak-to-peak
Temperature range	0 to 100 °C
Peak SNR	slow corner 64.4 dB
	typical corner 65.5 dB
	fast corner 67 dB
Peak SNDR	slow corner 60.7 dB
	typical corner 62 dB
	fast corner 63.2 dB
Dynamic range	65 dB
Power consumption	0.85 µW

. The resulting figure of merit (FOM) is 0.46 pJ/conversion-step, by calculating FOM = power/(2^ENOB × 2 × bandwidth) with ENOB as the effective number of bits. The modulator can work up to a 0.5 V power supply.

6. Comparison of the Power Efficiency

The performance of the presented modulator in Section 4 and Section 5 is compared to previous state-of-the-art low-voltage modulators in

Table 4. Performance comparison with previously-reported low-voltage low-power delta-sigma modulators. FOM, figure of merit.

Parameters	[15]	[18]	[19]	[9] †	[20]	This Work †
VDD (V)	0.25	0.2	0.3	0.4	0.4	0.3
Bandwidth (Hz)	10 k	20 k	20 k	10 k	20 k	1 k
Power consumption (µW)	7.5	7.5	79.3	0.41	140	0.85
Sampling frequency (Hz)	1.4 M	12 M	2.56 M	2 M	3.2 M	256 k
SNDR (dB)	61	60.3	74	58	68	60.7
DR (dB)	64	68.9	77	64	74	65
Technology (nm)	130	90	130	130	130	65
FOM1 (pJ/step)	0.477	0.222	0.481	0.032	1.7	0.464
FOM2 (dB)	155	163	161	168	155.5	156
FOM3 (pJ.V/step)	0.119	0.044	0.144	0.013	0.68	0.139

^† Results from simulation. Other references provide experimental results.

. Two commonly-used FOMs are employed, which are defined below:

$$FO{M}_1=\frac{Power}{2^{(SNDR-1.76)/6.02}\times 2\times BW}$$

(12)

$$FO{M}_2=D{R}_{dB}+10\log (\frac{BW}{Power})$$

(13)

The FOM₁ favors high-resolution ADCs, whereas the FOM₂ favors high-DR ADCs. These FOM definitions disregard V_DD, the threshold voltage of the corresponding technology, and the available swing. According to the FOM definitions given above, the designed inverter-based, second-order modulator achieves 0.46 pJ/conversion-step and 156 dB, respectively, which are comparable to the other state-of-the-art modulators operating with supply voltages below 0.4 V. Among others, the passive modulator in [2] operating at a 0.5 V supply consumes the lowest power (only 250 nW) while gaining moderate resolution (65 dB SNDR) and 72 dB DR. It looks attractive when using both FOM definitions given by Equations (12) and (13).

The modulator design in the ultra-low voltage domain (below 0.5 V) is becoming more and more challenging due to the limited available signal swing and switch overdrive voltage. The output swing of an OTA directly determines the integrators’ swing, which indeed defines the modulator reference voltage. As a consequence, the maximum input signal, V_in.max, that determines the DR of the ADC at a given input-referred noise floor P_n is limited by the reference voltage or the integrators’ swing. The DR can be derived as:

$$DR=10\log \frac{V_{in.\max }^2/2}{P_n+P_D}$$

(14)

where P_D is the input-referred distortion. To maintain the same DR in lower supply voltages, the noise floor and distortion power have to be decreased, requiring higher power consumption [21]. Generally speaking, for a better power efficiency, it is not desirable to reduce the supply voltage, because the analog power increases. However, specific applications, such as body implants (e.g., cardiac pacemakers, cochlear implants, etc.), demand ultra-low-voltage operation in the order of human body potentials.

It should be noted that the threshold voltage does not scale at the same proportion as the supply voltage, which limits the available overdrive voltage of the operating switches in SC designs. For fair comparisons of the modulators listed in Table 4, in addition to the commonly-used FOM₁ and FOM₂, the proposed FOM₃ takes into account the V_DD, as well.

$$FO{M}_3=\frac{Power\times V_{DD}}{2^{(SNDR-1.76)/6.02}\times 2\times BW}$$

(15)

In fact, the most effective comparison among different modulators is when we consider the threshold voltage in addition to the supply voltage, V_DD, because the available voltage headroom for analog blocks and the overdrive voltage for the switching transistors (i.e., V_GS − V_TH) depend directly on V_TH. Therefore, for a fair comparison, we need to consider the term V_DD − V_TH in the numerator of the FOM₃ given by Equation (15), rather than merely V_DD. For simplicity, we assume all technologies used in Table 4 have the same V_TH. According to FOM₃ and considering operating V_DD, the proposed modulator achieves a competitive figure of merit of 0.139 pJ.V/conversion-step.

7. Conclusions

An ultra-low-voltage, energy-efficient ΔΣ modulator is introduced in this paper for medical implant devices. In the absence of cascoding, a new gain-enhanced inverter-based amplifier was proposed to compensate for the reduced inverter’s DC gain and GBW. To overcome the switches’ overdrive limitation, the charge pump clock doublers were used to boost the clock signals’ level. The single-bit quantizer, including the preamplifier, dynamic comparator and latch, was designed in the deep sub-threshold regime, providing very high power efficiency. The entire modulator operates reliably against PVT variations from a 300 mV ± 10% supply voltage. The modulator design is compatible with human body potentials, as well as the energy efficiency intended for the target applications.