1. Introduction
Kinetic energy harvesting has been drawing significant attention in recent years since it can potentially extend battery lifetime or even facilitate energy autonomy for battery-operated IoT systems or portable/wearable electronics [
1,
2,
3]. For kinetic energy harvesting, energy harvesters with periodic excitations, such as cantilever-based piezoelectric energy harvesters, are widely studied since they generate regular periodic energy input, which allows the optimization of the harvesting interface circuit at the resonant frequency. Many state-of-the-art kinetic energy harvesting interfaces [
4,
5,
6] have been proposed for energy harvesters with such periodic inputs at relatively low (<5 V) harvester output voltages (
VHRV).
Recently, high voltage kinetic energy harvesters, such as triboelectric generators (TEG) [
7,
8] and high-voltage piezoelectric generators (HV-PEG) [
9,
10], have been actively investigated by the material science research community. These energy harvesters offer high energy density but at a relatively high
VHRV (>5 V). High energy density can be helpful in reducing the system form factor if the high
VHRV can be handled efficiently. In addition, if energy harvesting is realized for energy harvesters that generate irregular output, unlike the cantilever-based energy generators, kinetic energy can be harvested from a wider range of motions, e.g., computer key strokes and knee joint motion, and from new types of generators. For example, a TEG generates asymmetric pulsed output with different positive and negative peak voltages and delay between successive pulses even under periodic excitation [
7,
8]. Therefore, to achieve efficient energy harvesting from various types of motions and harvesting sources, a harvesting interface that can handle energy inputs with a wide range of voltages and various types of excitation modes is desired.
In recent years, a few harvesting interface designs [
11,
12,
13,
14] have been published that can deal with discontinuous energy input with high voltages. However, these designs suffer from a number of limitations:
- (1)
In high-voltage harvesting interfaces [
11,
12,
13], the power stage consists of a combination of HV PMOS and NMOS. HV NMOS can be driven by output/battery voltage (
VBAT) referenced drivers. Because
VBAT is stable, NMOS inherits a simple driving scheme. On the other hand, HV PMOS requires a high-voltage (
VHRV) referenced driving scheme. Under random input harvesting, stable
VHRV cannot be maintained without additional architecture and power overhead. Thus, unstable high-voltage
VHRV complicates the driving requirements for HV PMOS, which results in significant driving power overhead and also increases the system cost as HV PMOS driving interface consists of HV devices.
- (2)
Moreover, the standby powers of the prior harvesting interfaces [
12,
13,
14] are 10 s to 100 s of nW, limiting their application for harvesting under excitations with long idle periods.
- (3)
Furthermore, for the harvesting interfaces implementing voltage peaking event detection, sample and hold comparators are employed [
14]. Periodic charging/discharging of a sampling capacitor incurs power overhead, which may lead to inefficient harvesting at low-energy input.
These factors suggest the potential for improvement in discontinuous harvesting interface efficiency by adopting an HV NMOS power stage, lowering standby power by an ultra-low quiescent current wake-up controller (WUC) and reducing harvesting interface active mode controller power overhead by the use of an efficient voltage peak detection scheme.
In this work, a new harvesting interface is proposed to efficiently charge low-voltage batteries (2.4–4 V) with high voltage (5–200 V) PEG/TEG output in continuous as well as discontinuous form. The proposed harvesting interface architecture primarily consists of two blocks: the power stage and the controller. Unlike prior architectures that use high voltage NMOS and PMOS in the power stage, the proposed harvesting interface power stage uses only high voltage NMOS as shown in
Figure 1. NMOS with the source terminal at ground (
VSS) potential (M
1, M
2) can be directly driven by the
VBAT swing driving signal, but
VBAT source-connected NMOS (M
3) cannot be driven by the
VBAT swing signal. To drive M
3, an output (
VBAT) referenced, low-voltage device driving scheme is introduced in this work. NMOS-only power stage implementation eliminates high-voltage (
VHRV) referenced gate drivers. Thus, all drivers can be designed with low voltage devices; which simplifies the driving scheme and reduces the switching loss. Moreover, the high mobility of NMOS charge carriers also improves efficiency by offering a better tradeoff between switching and conduction loss.
To minimize controller power overhead, an event-based controller is implemented. The event-based controller limits controller power overhead by activating most sub-circuits only when energy input is detected; during standby mode, most of the sub-circuits are disabled/power gated.
During standby mode, the event-based controller activates only the wake-up controller (WUC); thus, for efficient harvesting under random excitation, an ultra-low quiescent current WUC is a key building block. Discontinuous excitation may result in long idle periods between successive
VHRV pulses; thus, for efficient harvesting under discontinuous input, the WUC must consume low quiescent current. The standby power consumption (WUC quiescent power) of prior harvesting interfaces [
12,
13,
14] is in the nano-Watts range. To improve harvesting interface standby performance, a new WUC is introduced that consumes only a few pico-Watts quiescent power. Thus, the proposed topology results in a significant reduction in standby power as compared to the prior arts. Moreover, a low voltage rejection filter is also introduced in the proposed WUC to inhibit harvesting from low voltage/energy input, which may result in negative efficiency.
Furthermore, to reduce controller active mode current consumption, a new inverter-based voltage peak detector (VPD) is introduced. The proposed VPD determines the voltage peak by evaluating the slope of VHRV. The proposed harvesting interface consumes only a few nJ per harvesting cycle, and standby power consumption is in the pW range. Thus, the proposed circuit can efficiently harvest form excitation that results in as low as 10 s of nJ energy per pulse even under discontinuous excitation. To limit the power overhead, all active devices in the controller and drivers are standard low-voltage devices, whereas high-voltage (HV) devices are used only for the power stage and for coupling HV at the low voltage controller.
The remainder of this paper is organized as follows:
Section 2 briefly describes the harvester’s maximum energy extraction condition and illustrates the top level architecture of the proposed harvesting interface and its operation cycle. Then implementation details of the proposed interface controller sub-circuits and drivers are presented in
Section 3. In
Section 4, the results are shown to verify the effectiveness of the proposed approach, and
Section 5 concludes the paper.
4. Simulation Results
The proposed random input harvesting interface is designed in 350 nm HV/LV (40 V/5 V) BCD process and evaluated with post-layout simulation with Hspice and Spectre. The BCD process used for circuit design provides high and low drain-source voltage devices. High-voltage devices offer ratings up to 40 V (break-down rating ≈ 48 V), and low-voltage devices have a rating of 5 V (break down rating ≈ 8 V). By utilizing both types of devices, two versions of the proposed harvesting interface are designed. In the first version, all high-voltage switches in the power stages are implemented with 40 V-rated integrated devices.
Figure 13a shows the layout of the proposed harvesting interface with all power switches integrated. The power stage occupies an active area of 1500 µm × 660 µm, whereas the controller and drivers occupy 712 µm × 280 µm. For the second version, 200 V-rated discrete devices are assumed to be used as power switches, and only the controller and drivers are implemented on-chip with low-voltage devices as shown in
Figure 13b. Due to the low voltage rating of the integrated capacitor (5 V) provided by the selected technology, discrete capacitors are used for all high-voltage capacitors. For simulating both versions, a 220 µH inductor with internal resistance (R
DC) of 0.022 Ω (Model = SRR7032) is used.
To verify operation of the proposed harvesting interface, two different piezoelectric generator (PEG) models are examined. The first model is a custom-made flexible PEG with low internal capacitance used in [
19] whose internal capacitance (C
P) is 500 pF and internal resistance (R
P) is 2 GΩ. The second model is a commercial PEG “MIDE V22B” with an internal capacitance of 19.5 nF.
For simulations, a PEG is often modeled with a variable current source, an internal capacitance and a resistance as shown in
Figure S3a [
4,
5,
6,
11,
12,
13,
14]. A variable current source is used to model various input conditions; it is assumed that the current source generates triangular current pulse with fixed duration (100 ms) and varying amplitude to model varying forces applied to the PEG. Such variation in physical input conditions results in variation in the generated energy (
EHRV_IN) and the resulting peak open circuit voltage (
VHRV(OC)_PEAK).
VHRV(OC)_PEAK is the voltage at the end of physical deformation of the harvesting material when no additional load is attached to it (
Figure S3b). As the amplitude of the current source (
IP) varies,
VHRV(OC)_PEAK also varies from 10 V to 195 V, as shown in
Figure S3c. For the rest of measurement, the input condition is represented with this
VHRV(OC)_PEAK since the actual peak voltage during harvesting operation varies with the input capacitance of the attached load circuits—the harvesting interface or a full bridge rectifier (FBR).
Figure 14 compares the harvesting performance of the integrated version of the proposed harvesting interface and an FBR. Post-layout simulation is conducted to measure the efficiency (left Y-axis) and harvested output energy (
EOUT) (right Y-axis) for charging a 3.3 V battery.
Figure 14a shows them as functions of
VHRV(OC)_PEAK (abbreviated as
VHRV(OC) in figures), and
Figure 14b shows them as functions of
EHRV_IN. As
VHRV(OC)_PEAK is increased with stronger input excitation, more energy is generated by the PEG. When the proposed harvesting interface is utilized, the harvesting operation is not activated until the output voltage reaches its peak, i.e., excitation is finished, allowing voltage accumulation at the output of the PEG. The final voltage when the harvesting interface is connected,
VHRV(INT)_PEAK, is smaller than
VHRV(OC)_PEAK due to larger load capacitor seen by the harvesting source since the input capacitance of the harvesting interface is added. Assuming the total charge generated by the PZT harvester is fixed with identical excitation, the relation between
VHRV(OC)_PEAK and
VHRV(INT)_PEAK can be expressed as:
where C
P is the parasitic capacitance of the PEG, and
CIN is the input capacitance of the proposed harvesting interface. Since the amount of energy generated by the PEG can be calculated as:
The PEG-generated energy (
EHRV_IN) is proportional to
and also to
. Therefore, the overall energy harvested by the harvesting interface (
EOUT) is also approximately proportional to
, as shown in
Figure 14a, and approximately proportional to
EHRV_IN, as shown in
Figure 14b. On the other hand, when an FBR is used for harvesting, the output voltage of the PEG is limited to
VFBR_HARV =
Vth_FBR + VBAT, where
Vth_FBR is the FBR threshold voltage (
Figure S3d,e). Therefore the amount of energy generated by the PEG is proportional to the amount of charge generated by the PEG, making the amount of harvested energy with an FBR (
EOUT) also approximately proportional to
, as shown in
Figure 14a.
In this measurement, the efficiency of the proposed harvesting interface or FBR is defined as follows:
With a weak excitation on the PEG, i.e., low
VHRV(OC)_PEAK or
EHRV_IN, the efficiency of the proposed harvesting interface drops due to the circuit operation overhead, resulting in worse efficiency than that achieved with an FBR. But as
VHRV(OC)_PEAK exceeds 11.5 V (or
EHRV_IN exceeds 33 nJ), the efficiency of the harvesting interface exceeds that of the FBR, with a maximum energy extraction improvement of up to 607% at
EHRV_IN = 506 nJ
(VHRV(OC)_PEAK = 45 V). Detailed simulated waveforms of the proposed harvesting interface at this point are provided in
supplementary Figure S4.
Figure 14c shows the percentage improvement in energy extraction of the proposed interface as compared to an FBR. It can be clearly seen that a significantly larger amount of energy can be harvested with the proposed harvesting interface than with an FBR.
As mentioned earlier, the 350-nm BCD process utilized for performing post-layout simulation provides 40 V high-voltage devices whose break down rating is 48 V. Therefore, to harvest energy with input peak voltage
VHRV(INT)_PEAK higher than 48 V, integrated power switches cannot be used as is. A version of the proposed harvesting interface is designed to operate with discrete high voltage transistors with 200 V rating (HV NMOS = PHC2300, FBR = DF02M, Diode = BAS21).
Figure 15 shows the simulation results for efficiency and
EOUT with the discrete power switches and with an FBR. Similar to the earlier case, a flexible PEG model is used, and the proposed harvesting interface is compared with a discrete FBR for charging a 3.3 V battery. Spice simulation models from vendors of discrete devices are utilized for analysis. Discrete high-voltage devices inherit higher parasitic loading, leakage loss, and driving overhead as compared to integrated versions; thus, in general, the efficiency is lower than that of the integrated version. FBR performance is better than that of the discrete version of the proposed interface up to
VHRV(OC)_PEAK = 40 V. But, as stronger excitation is applied to the PEG and
VHRV(OC)_PEAK exceeds 40 V (
EHRV_IN > 400 nJ), the efficiency of the discrete HV device harvesting interface exceeds that of the FBR.
Figure 15c shows that the proposed topology provides up to 1365% efficiency improvement as compared to the FBR when
EHRV_IN = 9.8 µJ
(VHRV(OC)_PEAK = 195 V). The overall trends of efficiency and
EOUT are similar to the results obtained with the integrated version.
Unlike the custom-built flexible PEG [
19], typical commercially available PEGs have internal capacitances on the order of ten nF
. To evaluate the compatibility of the proposed interface with commercial PEGs, the proposed harvesting interface was simulated with a PEG model whose internal capacitance is similar to “MIDE V22B,” whose
CP is 19.5 nF.
Figure 16a,b show the post-layout simulation results for efficiency and
EOUT with the integrated version of the proposed harvesting interface and an FBR.
The simulations are performed with varying levels of sinusoidal excitations, and the frequency of the excitation is assumed to be 174 Hz, which is the resonance frequency of MIDE V22B. The overall trends of efficiency and
EOUT are similar to the earlier analysis. However, due to the high energy-generation capacity and resulting capacitance of the harvester source, harvestable energy even at the low voltage limit (
VHRV(OC)_PEAK = 5 V) is significantly higher than that of the control and driving overhead, making the proposed harvesting interface superior than the FBR for all input ranges.
Figure 16c shows that the proposed topology provides up to 562% efficiency improvement as compared to the FBR when
VHRV(OC)_PEAK = 45 V (
EHRV_IN = 19.7 µJ) (for energy to power conversion multiply energy results with double of the periodic excitation frequency (348), because a positive and negative pulse is generated during each excitation). The detailed waveforms obtained under this condition are provided in
supplementary Figure S5. As the high capacitance PEG MIDE V22B can provide a maximum
VHRV(OC)_PEAK of ~40 V in real measurement, the discrete version of the proposed interface has not been simulated with the high capacitance PEG model.
A performance comparison of the proposed harvesting interface with other prior arts [
11,
12,
13,
14] is shown in
Table 1. The proposed harvesting interface is designed to handle a wide range of input voltages for maximum energy extraction. The maximum input voltage can be easily extended to 200 V with the use of discrete devices since the all-NMOS power stage design only requires control signals as high as 2 ×
VBAT or 3 ×
VBAT for handling high voltage inputs. The proposed harvesting interface can handle irregular pulsed inputs as well as periodic inputs with a load isolation scheme. Low operation overhead is achieved with event-based activation of an all-NMOS power stage and energy efficient WUC, VPD implementations, resulting in a large energy extraction improvement up to 1365%. Event-based activation with a low quiescent power WUC allows extremely low standby power consumption of 53 pW, enabling efficient energy harvesting from sporadic energy inputs with long intervals.
5. Conclusions
A novel harvesting interface has been introduced in this work for harvesting kinetic energy under irregular as well as periodic excitation. The proposed harvesting interface operates with a load isolation scheme to maximize energy extraction, which allows efficient harvesting independent of the nature of the harvester source or the type of excitation. Thus, the proposed interface operates efficiently over a wide voltage range and can be attached to a variety of harvester sources, from a PEG to a TEG, and under irregular as well as periodic excitation. A new WUC with ~13 pA quiescent current has been presented in this work, significantly reducing standby power and making the proposed harvesting interface suitable for energy harvesting from sporadic inputs. With an all-MOS power stage and an energy efficient VPD, efficient harvesting operation is enabled to significantly improve energy extraction.
The post layout analysis verifies that the integrated version of the proposed harvesting interface provides higher efficiency compared with that of an FBR over the VHRV(OC) range of 11.5 V to 45 V, with a peak efficiency improvement of 607% at 45 V when a PEG with a small CP of 500 pF is used as the source. When harvesting from the PEG with a higher CP, such as the commercially available PEG “MIDE V22B,” whose CP is 19.5 nF, the proposed interface efficiency is always higher than that of the FBR, with a peak improvement of 562% at 45 V. The proposed harvesting interface can also operate with discrete power switches, and our analysis with discrete NMOS with a voltage rating of 200 V provides high efficiency as compared to an FBR over a VHRV range of 40 V to 195 V with peak efficiency improvement of 1365% at 195 V when a PEG with CP of 500 pF is used as the harvester source.
We believe that the proposed harvesting interface can be used for efficient harvesting under random excitation, enabling efficient energy harvesting in numerous new applications, such as charging portable electronics with energy generated from random human body motion and charging wireless sensor nodes attached to animals for tracking by harvesting energy from random animal motions.