A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique
Abstract
:1. Introduction
2. Image Sensor Architecture
3. Proposed Techniques
3.1. Nonlinear Ramp Generation Technique Based on Dummy Pixel Array
3.2. Fully Differential Pipeline Sampling Quantization Based on Double Auto-Zeroing Technique
4. Analysis of Proposed Techniques
4.1. Linearity Analysis of CMOS Image Sensor with Linear Ramp
4.2. Linearity Analysis of CMOS Image Sensor with Adaptive Nonlinear Ramp
5. Results
5.1. Simulation Results of Nonlinear Ramp Generation Circuit Based on Dummy Pixel
5.2. Simulation Results of Fully Differential Pipeline Sampling Quantization with Double Auto-Zeroing Technique
5.3. Experimental Result
6. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Reference | This Work | [2] | [3] | [3] | [8] |
---|---|---|---|---|---|
Process (nm) | 180 | 180 | 180 | 180 | 40 |
Linearity improvement techniques | Adaptive nonlinear ramp based on dummy pixel | Pixel optimization and calibration | Analog buffer | Off-chip digital calibration | Linear ramp and source follower buffer |
Array size | 2560 × 3072 | 128 × 160 | 128 × 128 | 128 × 128 | NA |
Global/Rolling shutter | GS/RS | RS | RS | RS | RS |
ADC Architecture | 12/14 bit SS-ADC | 12 bit SS-ADC | 10 bit SS-ADC | 10 bit SS-ADC | 12 bit SS-ADC |
Frame rate (fps) | 86 (400 MHz clock) | NA | 60 (12.5 MHz clock) | 60 | NA |
Digital CDS | Y | Y | Y | Y | Y |
Pixel size | 6.5 µm × 6.5 µm | 12 μm × 10 μm | 10 μm × 10 μm | 10 μm × 10 μm | NA |
Fill factor | 100% (BSI) | 40% (FSI) | 47% (FSI) | 47% (FSI) | 100% (3D BSI) |
Pixel type | 5T | CTIA | 4T | 4T | NA |
Conversion gain | 17.4 μV/e− | 40 μV/e- | 56.8 μV/e- | 45.3 μV/e- | NA |
Read noise | 7.9 e− | 16.4 (gain = 8) | 4.12 (gain = 8) | 4.17 (gain = 8) | 261.5 μVrms |
Full well capacity | 91.7 ke− | 30.613 ke− | 17.27 ke− | 20.96 ke− | NA |
Dynamic range(dB) | 81.3 | 65 | 72.4 | 74 | 71.8 |
Column FPN (%) | 0.019 | NA | NA | NA | 0.028 |
SNR (dB) | 49.4 | 44.2 | 42.1 | 42.9 | NA |
Nonlinearity (%) | 0.047 | 0.095 | 0.058 | 0.06 | NA |
Dark current | 8.3 pA/cm2@23 °C | NA | 5.6pA/cm2 | NA | NA |
Per column Power | 96.3 μW | NA | NA | NA | 66.8 μW |
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Li, C.; Han, B.; He, J.; Guo, Z.; Wu, L. A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique. Sensors 2020, 20, 1046. https://doi.org/10.3390/s20041046
Li C, Han B, He J, Guo Z, Wu L. A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique. Sensors. 2020; 20(4):1046. https://doi.org/10.3390/s20041046
Chicago/Turabian StyleLi, Chuangze, Benguang Han, Jie He, Zhongjie Guo, and Longsheng Wu. 2020. "A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique" Sensors 20, no. 4: 1046. https://doi.org/10.3390/s20041046