Robust Pixel Design Methodologies for a Vertical Avalanche Photodiode (VAPD)-Based CMOS Image Sensor
Abstract
:1. Introduction
2. Robust Pixel Design of “Guard-Ring-Free” VAPD-CIS
2.1. Device Architecture of a VAPD Pixel Compared to a Conventional SPAD Pixel
2.2. Specifications and Chip Designs for VAPD-CISs
2.3. Potential and Layout Designs for Electric Field Relaxation and Pixel Isolation
3. Verification of the Robustness of VAPD-CIS
3.1. Verification of Potential Design against Process Variation
3.2. Characteristics of Robustness to Applied Voltage and Temperature
4. Robust Operation of VAPD-CIS in High-Temperature and Intense-Light-Exposure Conditions
4.1. Stable Operation during Direct Imaging of the Sun (DIS)
4.2. Stable Operation with No Degradation during High-Temperature/Intensity-Light-Illumination Operation Tests (HTs/ILOTs)
5. Discussion
5.1. Mechanism of Voltage Stabilizing by GFBR for Robust Operation
5.2. Temperature-Independent ATP: The Stabilizing Effect of GFBR
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
List of Selected Acronyms
AM | (voltage) Amplitude of Multiplication |
ATP | Avalanche Triggering Probability |
DIS | Direct Imaging of the Sun |
GFBR | Global Feedback Resistor |
HT/ILOT | High-Temperature/Intensity-Light-illumination Operation Test |
MR | (avalanche) Multiplication Region |
OFT | Overflow Transistor |
SRS-TOF | Subrange Synthesis Time-of-Flight |
VAPD | Vertical Avalanche Photodiode |
Appendix A
Appendix A.1. Calculation Formulas for Main Characteristics
References
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Items | Specifications | Typical Experimental Results |
---|---|---|
CMOS technology | 65 nm 1P4M1MIM | |
Pixel pitch | 6 μm | |
Array size | 1200 × 900 | |
Frame rate | 30 fps | |
Fill factor | 30.6% (including circuit area) 57.3% (excluding circuit area) | |
|VBD| | <32 V | 29.8 V @−25 °C 27.5 V @RT |
Isolation potential | <0 V | −1.3 V @RT |
PDE @940 nm | >1% >1.2%@RT | 1.2% @−25 °C 1.6% @RT |
DCR | <100 cps/pix @RT <54,000 cps/pix @105 °C | 21 cps/pix @RT 10,000 cps/pix @105 °C |
Voltage swings | >1 V | 1.5 V |
Item | Before | After | Variation | Test Spec. |
---|---|---|---|---|
Q.E. (%) | 4.38% | 4.20% | −4.0% | 3.5% max. |
|VBD| (V) | 28.15 V | 28.15 V | 0% | 27 V~29 V |
DCR (cps) | 21.5 cps | 20.4 cps | −5.0% | 50 cps max. |
PDE (%) | 1.46% | 1.46% | 0% | 1% min. |
AM (V) | 1.50 V | 1.50 V | 0% | 1 V min. |
σAM (V) | 0.083 V | 0.084 V | 1.4% | 0.17 V max. |
Temperature | 125 °C |
Illumination power | 827 μW/cm2 |
Wavelength | 940 nm |
Exposure Time | 1000 h. |
Optical Filters Condition | w. BPF and Lens |
Driving mode | Time-of-Flight (45,000 exposures/s) |
Read-out speed | 450 fps |
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Inoue, A.; Torazawa, N.; Yamada, S.; Sugiura, Y.; Ishii, M.; Sakata, Y.; Kunikyo, T.; Tamaru, M.; Kasuga, S.; Yuasa, Y.; et al. Robust Pixel Design Methodologies for a Vertical Avalanche Photodiode (VAPD)-Based CMOS Image Sensor. Sensors 2024, 24, 5414. https://doi.org/10.3390/s24165414
Inoue A, Torazawa N, Yamada S, Sugiura Y, Ishii M, Sakata Y, Kunikyo T, Tamaru M, Kasuga S, Yuasa Y, et al. Robust Pixel Design Methodologies for a Vertical Avalanche Photodiode (VAPD)-Based CMOS Image Sensor. Sensors. 2024; 24(16):5414. https://doi.org/10.3390/s24165414
Chicago/Turabian StyleInoue, Akito, Naoki Torazawa, Shota Yamada, Yuki Sugiura, Motonori Ishii, Yusuke Sakata, Taiki Kunikyo, Masaki Tamaru, Shigetaka Kasuga, Yusuke Yuasa, and et al. 2024. "Robust Pixel Design Methodologies for a Vertical Avalanche Photodiode (VAPD)-Based CMOS Image Sensor" Sensors 24, no. 16: 5414. https://doi.org/10.3390/s24165414