Comprehensive Analysis of LCL Filter Interfaced Cascaded H-Bridge Multilevel Inverter-Based DSTATCOM

Abstract

Three-phase two-level voltage source converters are used for distribution static compensator (DSTATCOM) applications and can be replaced by a multilevel inverter. In this paper, an LCL filter interfaced cascaded H-bridge multilevel inverter-based (CHBMLI) DSTATCOM is simulated and its performance is analyzed considering the system parameters. The analysis considers factors including the switching frequency, modulation index, and filter parameters of a DSTATCOM system. The LCL filter design and analysis for the low switching frequency operation of CHBMLI is proposed in this paper. Phase shift pulse-width modulation is used for the generation of switching signals. The reference current is generated using synchronous reference frame theory (SRFT) for reactive power and harmonic compensations. The simulation model of the CHBMLI-based DSTATCOM system is developed in MATLAB Simulink. The results are demonstrated for a linear/non-linear load under unbalanced conditions, considering the voltage sag and swell in the system due to a disturbance in the load.

1. Introduction

It is essential to recognize power quality issues in power systems. Power quality refers to a system’s ability to maintain a sinusoidal power distribution voltage and current at a rated magnitude and frequency. Therefore, any disturbance in a distribution system is referred to as a power quality issue. Power transmission may have an effect on power quality, but it only has a minor effect because modern transmission systems have lower resistance-to-reactance ratios, and consequently, have lower damping ratios [1,2,3]. Also, the generating system is not usually the primary cause of any existing non-ideal behavior, and thus, it is not often a major concern in terms of power quality. The roots of power quality issues are categorized in two ways: natural causes and manmade causes, which may be due to the load or a feeder. The second category plays a major role in contributing to the rise in power quality issues. Some of the manmade causes that affect power quality include transformers, the charging and discharging of capacitors, nonlinear loads such as power electronic loads (e.g., an uninterrupted power supply), speed drive converters, and the time-variant switching of large loads.

Power grids that are connected to various types of loads suffer from dynamic and transient changes due to power quality issues; to monitor the functioning of the grid, online real-time monitoring systems are therefore required. Real-time power quality monitoring requires a system set-up that enables corrective actions to be taken. A real-time power quality monitoring system is thus necessary to provide the required information, both locally and more widely throughout the system [4,5]. Therefore, the monitoring system must be aware of the effects of poor power quality on the safety, reliability, and efficiency of the many types of equipment connected to the grid. The various aspects of power quality to be considered include voltage fluctuations, voltage sag-swell, voltage imbalance, and higher-order harmonics in the grid current [6].

The cumulative use of power electronic loads by both industry and local consumers results in a considerable amount of harmonic injection, and a poor power factor. Conventionally, passive filters have been used to eliminate the current harmonics and improve the power factor. However, the use of passive filters has many disadvantages, including a high value inductance, damping effects, and the large size of the capacitor bus. Recently, with the rapid progress being made in modern power electronics technology, filter applications are oriented towards the use of active filters, rather than passive filters. The basic difference between passive and active filters is that the active filters have the ability to compensate for randomly varying currents [7].

Recent developments in power systems and emerging power device technologies include the flexible AC transmission system (FACTS) and custom power devices, where deregulated power systems with flexible new control capabilities fall under the category of custom power devices. Custom power devices are classified into network configuration-type and compensation-type devices; the former type actually alters the properties of the power system network, enhancing the power quality [8].

In any distribution system, the presence of an unbalanced load or nonlinear loads can inject higher order harmonics or cause an imbalance in the system. The custom power devices are used to prevent such unbalanced and distorted currents from being drawn into the grid of the distribution line, either connected in series or shunt configurations. One such shunt-connected custom power device is the distribution static compensator (DSTATCOM) that can dynamically inject a compensating current with the desired amplitude, frequency, and phase. For reactive power compensation and harmonic elimination applications, the DSTATCOM is one of the fastest and most reliable modular custom power devices. DSTATCOM can be used to ensure that the current drawn from the grid is nearly sinusoidal and distortion-free. A voltage source converter (VSC) is commonly used to realize a DSTATCOM. The VSC structure determines the level or extent of compensation that the device can provide in the grid. If a three-phase four-wire system is connected to a balanced load, then a balanced compensating current is required to maintain the smooth operation of the system. However, in the above scenario, if the source current or load is unbalanced or distorted, the required compensation current must be unbalanced and distorted to mitigate the lack of balance or distortion in the system [9,10]. DSTATCOM behaves like a controlled voltage or current source in the grid. DSTATCOM can supply the required reactive power to the problem load from the circulating energy that is present between the phases of the AC system.

DSTATCOM requires a VSC for its functionality and one of the preferred converter topologies is the multilevel VSC. An alternating voltage source in phase with the grid voltage can be generated through the application of a suitable control scheme to a multilevel inverter-based DSTATCOM [11,12]. Multilevel inverters (MLIs) are capable of producing a synthesized output voltage from several input DC voltage levels. As per the MLI topology, a voltage waveform with a near-sinusoidal shape can be obtained by using a sufficient number of DC sources. Therefore, MLIs have been gaining attention in recent years, for their application in medium and high voltage systems [13].

Cascaded H-bridge MLI (CHBMLI) have the advantages of lower operating switching frequencies, a reduced electromagnetic interference, and a modular structure. However, it requires separate DC sources/capacitors for each bridge. The modularity of topology and the ease of lower to higher level expansion are some of the application-based advantages of the CHBMLI-based DSTATCOM [14]. Several applications of cascaded MLIs have been attempted, including the STATCOM, motor drive applications, and the integration of renewable energy sources. CHBMLI has certain advantages over the diode-clamped MLI and the capacitor-clamped MLI, as they require additional clamping diodes and clamping capacitors [15,16]. In such inverter topologies, the switching of power electronic devices injects higher level harmonics into the grid.

A proper current control is required for the generation of pulse width modulation (PWM) signals, to mitigate the harmonics. The different PWM techniques can be adopted to optimize the switching frequency of each of the power electronic devices. There are two main types of carrier-based modulation techniques that have been developed by extending conventional PWM: phase shift PWM (PSPWM) and level shift PWM. However, other modulation techniques have been proposed in the literature [17]. Sinusoidal PWM (SPWM) offers a nearly constant switching frequency and reduced complexity for MLIs when compared to other modulation techniques, including hysteresis current control and space vector modulation (SVM), which have contrasting disadvantages. The modulation techniques that are used for MLIs can be classified into three types, comprising SVM, SPWM, and selective harmonics elimination PWM. In recent years, several authors have attempted to generalize the available PWM techniques for various multilevel inverter topologies [18,19]. Based on previous efforts, it was observed that the generation of PWM signals for CHBMLI, using phase shift and level shift PWM, have been found to be reliable, supported by a reduced complexity [20].

The computation of reference quantity using a proper control algorithm is responsible for the generation of PWM signals to improve the power quality. In general, these control algorithms can be classified, based upon the reference generation in the stationary/rotating axis frame. Synchronous reference frame theory (SRFT) is based on a set of instantaneous power equations defined in the time domain. In an SRFT-based system, it has been acknowledged that the d-component and q component of the load current are responsible for the active power and reactive power, respectively [21,22,23,24].

In this paper, a five-level CHBMLI-based DSTATCOM is implemented and a phase-shift PWM technique is adopted for the generation of switching signals, because of the uniform distribution of power stress on each switching device. An LCL filter interfaced MLI system is proposed, due to its inherent advantage over L and LC filter-based systems. An LCL filter is designed with a reduced inductor size to avoid resonance issues, using an appropriate damping technique [25,26,27]. This paper involves the operation in a switching frequency range of 1–5 kHz, and the LCL filter design is thus performed with passive damping for a better attenuation bandwidth. The reference signal is generated using SRFT for the indirect current control of the LCL filter interfaced DSTATCOM system. The performance of the MLI inverter system is validated under different load conditions, such as balanced and unbalanced linear/non-linear loads, considering power quality issues. The proposed system is also investigated considering the effect of change in the dc voltage capacitance and switching frequency on the dc bus voltage under transient conditions.

2. System Description and Design

2.1. Basic Structure

The CHBMLI topology utilized for DSTATCOM offers both modularity and flexibility, corresponding to a change in the voltage level and switching frequency. The basic circuit of the three-phase CHBMLI is shown in Figure 1, considering generalized m-levels. The circuit consists of (m − 1)/2 cascaded cells in each phase. Each CHBMLI cell requires an isolated DC source/capacitor for the generation of a synthesized output ac voltage. The generalized system equations, as in Equations (1)–(4), are for the DC voltage and output ac voltage of CHBMLI. For the DSTATCOM application, the CHBMLI bandwidth must be decided upon, based on the highest level of harmonics which need to be compensated. In the case of CHBMLI, the increased level of inverters has a linear relation with the number of H-bridge cells and dc sources/capacitors required for the implementation of the system. However, the improvement in the output voltage performance does not follow the linear relation and there will not be a considerable improvement in the performance corresponding to increased levels. Therefore, five and seven level inverters are predominantly used for system implementation at a medium voltage (415–1100 V). Each of the H-bridges that are connected in cascade can generate three output levels: +V_dc, 0, and −V_dc.

The peak value of the output voltage per phase can be written as:

V_a = V_aH1 + V_aH2 + … + V_{aH[(m−1)/2−1]} + V_a[(m−1)/2]

(1)

by assuming that each of the H-bridges has an equal DC bus voltage, i.e., V_aH1 = V_aH2 = … = V_{aH[(m−1)/2−1]} = V_a[(m−1)/2] = V_dc.

The output voltage of the CHBMLI is also written as:

$$V_A\left(\mathsf{\omega }t\right)={\displaystyle \sum }_{n=1}^{n=\infty }f\left(x,n\right)(\sin n\mathsf{\omega }t)$$

(2)

where:

$$f\left(x,n\right)=\frac{4V_{\mathrm{dc}}}{n\mathsf{\pi }}{\displaystyle \sum }_{k=1}^{\left(m-1\right)/2}\left(a_n\cos n{\mathsf{\alpha }}_k\right)$$

(3)

It is necessary for the switching angles to be restricted such that:

$$\frac{\mathsf{\pi }}{2}>{\mathsf{\alpha }}_m>\dots \dots {\mathsf{\alpha }}_2>{\mathsf{\alpha }}_1$$

(4)

2.2. Implemented System

A five-level CHBMLI-based DSTATCOM is analyzed and investigated, and connected to the grid via an LCL filter. The CHBMLI (acting as the VSC) for the DSTATCOM application offers control capabilities similar to those of the traditional three-leg inverter. The only difference between these inverters is that more gate signals are required by the earlier invertor, but one of the advantages of the proposed system is that a reduced total harmonics distortion (THD) can be achieved in the converter voltage. The application of an appropriate control scheme with an optimum inverter level produces a voltage source inverter that can generate an alternating voltage in phase with the source voltage. The analysis of the DSTATCOM is also conducted, based on the filter that is applied between the system and the STATCOM. Similarly, the five inverter voltage levels are −2V_dc, −V_dc, 0, V_dc, and 2V_dc; these voltage levels are added to provide the synthesized output of the MLI. The voltage waveform in each phase of the five-level cascaded inverter consists of five leveled outputs, with two H-bridges connected in the cascade. Each phase of this voltage is fed to the distribution line through a coupling inductance, to form a shunt-connected DSTATCOM, as shown in Figure 2, where V_sa, V_sb, and V_sc are the source phase voltages that are connected to a nonlinear load or reactive load. L_s is the per phase line inductance, and I_La, I_Lb, and I_Lc represent the per phase load currents. As shown in Figure 2, the CHBMLI is connected in shunt configuration to the load, and thus, at the point of common coupling (PCC), Kirchhoff’s law can very easily be applied. Generalized phasor diagrams of the leading and lagging power factor (PF) load compensation are shown in Figure 3, where cos θ is a PF.

The focus of this paper is on the analysis and effects of different parameters on the design of a DSTATCOM for reactive power and harmonics compensation. As shown in Figure 2, the system configuration used is the CHBMLI-based DSTATCOM. Linear, nonlinear, and unbalanced loads are connected to the system, and draw lagging or leading, distorted and unbalanced load currents from the source, respectively. The shunt-connected device allows for the compensation of the reactive power and harmonics to be performed, and the avoidable component of the current is supplied by the DSTATCOM.

After the connection of the shunt device, the current equation will be as expressed in Equation (5). The nature of the compensation current generated by the shunt device is entirely dependent on the purpose of the required power quality improvement. At the PCC, the resulting source current should be sinusoidal.

$$\left[\begin{array}{c}{I}_{\mathrm{La}}\\ I_{\mathrm{Lb}}\\ I_{\mathrm{Lc}}\end{array}\right]=\left[\begin{array}{c}{I}_{\mathrm{Ca}}\\ I_{\mathrm{Cb}}\\ I_{\mathrm{Cc}}\end{array}\right]+\left[\begin{array}{c}{I}_{\mathrm{sa}}\\ I_{\mathrm{sb}}\\ I_{\mathrm{sc}}\end{array}\right]$$

(5)

2.3. DC Link System

Here, the selection of the topology used for the DSTATCOM application is based on the symmetrical structure of the CHBMLI. If all the parameters and all the switching pulses for all of the H-bridge units are symmetrical, then the actual power of each unit will be identical. However, because of the dispersion of the capacitors and the switching losses of the IGBTs, the active power of each of the H-bridge units is different. A five-level MLI topology has been adopted for the analytical study, meaning that there are two H-bridges in each phase, and therefore, there are two capacitors per phase and a total of six capacitors in the five-level cascaded H-bridge inverter-based DSTATCOM. The voltages across each of the capacitors should be balanced throughout the operation. Many techniques are available to balance the voltages across the DC link capacitors. Many advanced and intelligent techniques have also been proposed for the balancing of the capacitor voltage, because it is a prominent part of the overall system design and operation.

In reference [28], a mathematical formulation for the cascaded H-bridge capacitance is derived as:

$$C_{\text{dc-cascaded}}=\frac{I_{\mathrm{rms}}\times 100}{\sqrt{2}\mathsf{\pi }{f}_{\mathrm{g}}\%V_{\mathrm{r}}{V}_{\mathrm{dc}}}[1-\sin \left(\mathrm{arcos}\right(\frac{M\mathsf{\pi }}{4}\left)\right)]$$

(6)

where I_rms is the root mean square (RMS) load current (rated), f_g is the frequency of the system’s supply, V_r is the peak-to-peak ripple voltage, $V_{\mathrm{dc}}$ is the DC bus voltage, and M is a modulation index. The voltage balancing can be performed in a phase-wise manner, i.e., the voltages across each of the phases should be equal, and if not, this can be achieved by using an individual voltage balancing technique. In this paper, an individual voltage balancing technique is used for voltage balancing of each capacitor. To distribute the total active power between all of the H-bridges and to make the capacitor voltage equal to the reference voltage, one extra loop must be added to the control system. The proportional integral (PI) controller is one of the most commonly applied linear feedback controllers, and has been used here because of its simplicity, applicability, and ease of control. The current responsible for power loss due to charging and discharging of capacitors (i_dloss) is calculated and function of this controller can be elaborated simply, using the following mathematical equation:

$$i_{\mathrm{dloss}}=K_{\mathrm{p}}\left(V_{\mathrm{dcref}}-V_{\mathrm{dc}}\right)+K_{\mathrm{i}}{{\displaystyle \int }}^{\text{}}\left(V_{\mathrm{dcref}}-V_{\mathrm{dc}}\right)$$

(7)

This equation shows only one PI controller, which drives the system to make the capacitor voltage equal to the reference value of the DC link voltage ($V_{\mathrm{dcref}})$ however there are six PI controllers in the proposed feedback control loop across each bridge. All of the controllers have the same proportional gain (K_p) and Integral gain (K_i) values. The trial-and-error method is used to determine values of the proportional and integral gains.

2.4. Reference Current Generation for CHBMLI

Various voltage and current control techniques are available for the control of the STATCOM, and because of its reduced complexity and ease of implementation, an indirect current control technique is used for reactive power and harmonics compensation. A basic block diagram that depicts the reference current generation for indirect current control, is shown in Figure 4, and is responsible for reactive power and harmonic compensation.

According to the current control technique implemented using the d-q component, the direct and quadrature axis current is responsible for the active power and reactive power, respectively. The load current passes through the low pass filter (LPF) to obtain the fundamental components of the current. Therefore, only the active component of the power should be required from the source, or only the average DC component ($I_{\mathrm{d}}^{*}$) is required to be fed from the grid. A certain amount of the active power is also consumed by the DSTATCOM, due of the charging and discharging of the capacitors, and this component of the current is responsible for some losses in the grid. The current that is responsible for maintaining the capacitor voltage is added to the active power component of the current, to regulate the capacitor dc voltage by compensating for inverter losses. The mathematical equation involved in the transformation of cuurent from abc to dq0 axis, and in the dq0 to abc axis transformation, is as follows:

$$\left[\begin{array}{c}{I}_{\mathrm{d}}\\ I_{\mathrm{q}}\\ I_0\end{array}\right]=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}\cos \mathsf{\omega }t& \cos \left(\mathsf{\omega }t-\frac{2\mathsf{\pi }}{3}\right)& \cos \left(\mathsf{\omega }t+\frac{2\mathsf{\pi }}{3}\right)\\ -\sin \mathsf{\omega }t& -\sin (\mathsf{\omega }t-\frac{2\mathsf{\pi }}{3})& -\sin \left(\mathsf{\omega }t+\frac{2\mathsf{\pi }}{3}\right)\\ \frac{1}{\sqrt{2}}& \frac{1}{\sqrt{2}}& \frac{1}{\sqrt{2}}\end{array}\right]\left[\begin{array}{c}{I}_{\mathrm{La}}\\ I_{\mathrm{Lb}}\\ I_{\mathrm{Lc}}\end{array}\right]$$

(8)

The inverse transformation from the dq0 to abc phases can then be written as:

$$\left[\begin{array}{c}{I}_{\mathrm{a}}^{*}\\ I_{\mathrm{b}}^{*}\\ I_{\mathrm{c}}^{*}\end{array}\right]=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}\cos \mathsf{\omega }t& -\sin \mathsf{\omega }t& \frac{1}{\surd 2}\\ \cos (\mathsf{\omega }t-\frac{2\mathsf{\pi }}{3})& -\sin (\mathsf{\omega }t-\frac{2\mathsf{\pi }}{3})& \frac{1}{\surd 2}\\ \cos (\mathsf{\omega }t+\frac{2\mathsf{\pi }}{3})& -\sin (\mathsf{\omega }t+\frac{2\mathsf{\pi }}{3})& \frac{1}{\surd 2}\end{array}\right]\left[\begin{array}{c}{I}_{\mathrm{d}}^{*}\\ I_{\mathrm{q}}^{*}\\ I_0^{*}\end{array}\right]$$

(9)

The generalized reference current for indirect control is calculated using the following equations:

$$V_{\mathrm{t}}=\sqrt{\frac{2}{3}\left(v_{\mathrm{sa}}^2+v_{\mathrm{sb}}^2+v_{\mathrm{sc}}^2\right)}$$

(10)

$$I_{\mathrm{qt}}=K_{\mathrm{p}}\left(V_{\mathrm{tref}}-V_{\mathrm{t}}\right)+K_{\mathrm{i}}{{\displaystyle \int }}^{\text{}}\left(V_{\mathrm{tref}}-V_{\mathrm{t}}\right)$$

(11)

$$I_{\mathrm{d}}^{*}=I_{\mathrm{df}}+I_{\mathrm{d},\mathrm{loss}}$$

(12)

$$I_{\mathrm{q}}^{*}=I_{\mathrm{qf}}+I_{\mathrm{q},\mathrm{t}}$$

(13)

V_t is termed as the terminal voltage of the PCC that is regulated through the PI controller to maintain the power quality of the system, considering the voltage sag and swell caused by disturbance.

3. SPWM for CHBMLI

Many modulation techniques have been developed by researchers for MLIs; however, for the DSTATCOM application, SPWM techniques are modular and avoid any complexity in the system. Other commonly used modulation techniques for MLIs include SVM and the selective harmonics elimination technique, and some nonlinear modulation techniques have also been developed for the CHBMLI. Two types of SPWM techniques have been utilized for CHBMLISs: level shift SPWM and phase shift SPWM. Both modulation techniques have advantages, such as the ease of implementation, a constant switching frequency, and the linear nature of control. For m-level CHBMLI, (m − 1) carrier signals (triangular) are compared to the one modulating signal (sinusoidal) in order to generate the PWM signals.

3.1. Level Shift Modulation-Based System

A level shift modulation technique requires that all carrier signals have the same frequency and phase, but their amplitudes are reduced by the average value and shifted along the vertical axis as shown in Figure 5. An implemented five-level inverter that required four triangular signals is compared to the sinusoidal signal, in order to generate the PWM signal for the switches. The modulation index can be varied by changing the magnitude of the sinusoidal wave. Further classifications of the level shift modulation have been conducted, but for simplicity, all of the carrier waves can be taken in the same phase.

3.2. Phase Shift Modulation-Based System

Similar to level shift PWM, phase shift PWM uses (m − 1) carrier signals; however, the carrier signals are phase shifted, while their amplitudes and frequencies are identical as shown in Figure 6. The phase shifts of 360/(m − 1) degrees between each sequential carrier signal are required. In this paper, a five-level inverter is used, and thus four carrier signals with 90° phase shifts are compared with the reference signal, in order to generate the PWM signal for CHBMLI. Phase shift modulation also has one important advantage in that it eases the modulation index change process. Phase shift modulation produces an equal power stress on each switching device, and thus, the modularity and switching losses are distributed across the entire MLI structure. In this paper, the phase shift modulation technique is implemented on a five-level CHBMLI and the satisfactory results demonstrate its applicability and modularity for MLI applications.

4. LCL Filter Design

Another function of the proposed distribution system is to suppress the additional higher order harmonics that are present in the output voltage generated by power electronic converters, because these harmonics affect the PCC voltage and current. To suppress the harmonics generated by the power electronic devices, the LCL filter is used because it offers advantages such as a small inductor size and cost effectiveness. The minimum filter inductor required to limit the current ripple, considering the single inductor filter system, is given by:

$$L_{\mathrm{fmin}}=\frac{V_{\mathrm{m}}}{v_{\mathrm{s}}{f}_{\mathrm{s}}}$$

(14)

where f_s is the switching frequency, V_m is the amplitude of the source voltage, and v_s is the peak amplitude of the triangular carrier signal.

Several researchers [28,29,30,31] have used an LCL filter for two-level VSC and a better performance is obtained when compared to L/LC filters, as an LCL filter is capable of providing an attenuation of 40 dB/decade beyond the switching frequency, for a large frequency range. The main objective of using the CHBMLI is to provide low switching losses because the output voltage contains fewer switching ripples compared to the conventional two-level VSC . However, a CHBMLI operates at a low switching frequency compared to the conventional two-level inverter. So, the parameter design of an LCL filter is needs to be modified, according to the operating condition of the MLI system, by following fundamental design constraints. In this study, an LCL filter is designed for an MLI system operating at a lower switching frequency, to avoid the use of a large-sized bulky inductor.

The LCL filter design is required to follow the constraint of the resonance frequency of the filter, switching frequency of the inverter, and fundamental frequency of the grid system, given the inequality (15). The grid impedance may vary substantially, along with its stiffness, so the filter resonance frequency may also vary, and thus specific care must be taken when designing the filter. Current filter design practices dictate that the inductor should be small in size, while the capacitor size may vary or can be large. However, the capacitor design deals with the power factor constraint. The filter design constraint in Equation (16) limits the size of the capacitor.

10f_g << f_res << 0.5f_s

(15)

$$C_{\mathrm{f}}<0.05C_{\mathrm{b}}$$

(16)

$$C_{\mathrm{b}}=\frac{1}{{\mathsf{\omega }}_{\mathrm{g}}{Z}_{\mathrm{b}}}$$

(17)

$$Z_{\mathrm{b}}=\frac{V_{\mathrm{source}-\mathrm{LL}}^2}{P_{\mathrm{inv}}}$$

(18)

The filter design includes two inductors that are termed as grid side and inverter side inductances, and both inductors should have an optimum value so that they work correctly for the given operation.

$$L_{\mathrm{g}}=\frac{V_{\mathrm{s}-\mathrm{phase}}}{2\sqrt{6}{f}_{\mathrm{s}}{i}_{\mathrm{ripple}.\mathrm{peak}}}$$

(19)

where a = 1 and L_i can be defined as:

$$L_{\mathrm{g}}=a{L}_{\mathrm{i}}$$

(20)

where C_b is the base capacitance, Z_b is the base impedance, ${\mathsf{\omega }}_{\mathrm{g}}$ is the angular frequency of the grid, V_source-LL is the source voltage, P_inv is the inverter’s rated power, V_s-phase is the RMS value of the source phase voltage, and I_ripple.peak is taken to be 20% of the rated current. f_g, f_res, and f_s are the grid, resonance, and switching frequencies, respectively. The Bode diagram shown in Figure 7 illustrates the performance of the LCL filter with and without damping resistances of various values (passive damping). Passive damping of the LCL filter allows the resonance to be avoided. The attenuation capability of the LCL filter is reduced over the high frequency range for high values of damping resistance, and thus, an optimum resistance value of 0.5 Ω is selected. The filter capacitance value is determined, based on the assumption that C_f = 0.015 C_b. The value of the capacitor in the LCL filter can be chosen very easily and should satisfy the above relationship for the lower order harmonics.

The LCL filter design procedure in the proposed work has been performed, based on the consideration that the operating switching frequency ranges from 1 kHz to 5 kHz, while the resonance frequency of the designed LCL is 629 Hz, to satisfy the consideration of Equation (15); the converter side inductance of the filter should be selected with particular care, because the current ripples vary substantially within a single switching period. L_g is designed first, and the values of L_i are subsequently chosen, accordingly. Therefore, the LCL filter offers an outstanding option for the proposed system considering various constraints. The passive/active damping methods can be used to avoid resonance issues. The passively damped system is adopted by using a damping resistance for ease of system control implementation. In this paper, the two inductors are taken to have equal values.

5. Results and Discussion

The DSTATCOM system shown in Figure 2 is implemented and simulated under the unity power factor (UPF) mode, to force the grid to supply the fundamental active components of the power through the proper generation of the reference current. The CHBMLI-based DSTATCOM developed in MATLAB Simulink (2014b, MathWorks, Natick, MA, USA) was analyzed for linear and non-linear loads under UPF operation.

Table 1. Simulation data used illustrating the STATCOM performance.

S. No.	Simulation Parameter	Values
1.	Source voltage	1100 V
2.	Frequency	60 Hz.
3.	Sources reactance	0.01 Ω and 1.6 mH
4.	LCL Filter Parameter	Lg = 1.6 mH, Ls = 1.6 mH, Cf = 80 µF, Rd = 0.5 Ω
5.	DC link voltage per cell	450 V
6.	Kp, Ki	1.2 × 10−3, 7 × 10−4
7.	Capacitor	800 µF
8.	Switching Frequency	1000–5000 Hz
9.	Linear Load	65 KVA 0.8 PF lagging
10.	Non Linear Load	Rectifier load R = 50 Ω, L = 500 mH
11.	Unbalanced load	In phase C 10 KVA

shows the values of all parameters of the proposed system. Each of these values is taken for a 1100 V line-to-line voltage system, under the condition that there are two bridges in each phase that produce the same voltage level, where a value of 450 V should be maintained across each bridge. The point of this analysis is to assess the performance of this system when using phase shift SPWM.

5.1. System Performance

5.1.1. Linear Load Condition

The performance of the DSTATCOM system is analyzed considering the linear type R-L load connected to the system. The generated reference current forces the DSTATCOM to compensate for the reactive power required by the load. Therefore, the grid can operate under UPF up to the capacity of the DSTATCOM system, compensating for the reactive power. The PCC voltage corresponding to the DSTATCOM output is demonstrated in Figure 8, Figure 9, Figure 10 and Figure 11. For the DSTATCOM performance evaluation load, the source and DSTATCOM current is shown in Figure 12, Figure 13 and Figure 14 for a linear, unbalanced, and non-linear load, for a time duration of 0–15 s, 0.15–0.30 s, and 0.30–0.45 s, respectively. The load source current and DSTATCOM current under a balanced load condition from time t = 0–0.15 s, are demonstrated in Figure 12a–c, respectively. The linear load connected to the system switched to the unbalanced condition at time t = 0.15–0.30 s, by disturbing phase “c” of the load. The source current was maintained in the balanced condition during unbalance in the system as the unbalanced compensating current provided by the DSTATCOM. The compensating current enables the source current to supply balanced active power to the load, as shown in Figure 13a–c, during an unbalanced condition.

5.1.2. Non-Linear Load Condition

The DSTATCOM system was investigated considering the non-linear load condition needed to validate the system performance. The diode bridge rectifier with a R-L load was considered to be a non-linear type load, and was connected to the system at t = 0.3 s. The PCC voltage of the system, as shown in Figure 8, is maintained under a non-linear load condition. The harmonic compensating current provided by the DSTATCOM, as shown in Figure 14a–c, forced the source current, supplying the active power component. The power supplied by the source, the DSTATCOM, and the power required by the load, are demonstrated in Figure 15, Figure 16 and Figure 17 for linear and non-linear load conditions. The grid is only supplying active power, as the reactive power required by the load is compensated for by the DSTATCOM.

5.2. Power Quality Analysis

5.2.1. Voltage Disturbance

The change in load creates a disturbance in the PCC voltage of the system, resulting in voltage sag/swell. The DSATCOM system is capable of maintaining the PCC voltage under the normal condition, by supplying a compensating current. The PCC voltage shown in Figure 18a is balanced under the disturbance, caused by the unbalanced load condition and change in load. The terminal voltage at the PCC (V_t), computed using Equation (10), is examined to investigate the performance of the DSTATCOM and is used as a validation of its effectiveness. The reference V_t can be computed as in Equation (21):

$$V_{\mathrm{t}}=\sqrt{\frac{2}{3}\left(v_{\mathrm{sa}}^2+v_{\mathrm{sb}}^2+v_{\mathrm{sc}}^2\right)}=\sqrt{\frac{2}{3}\left(3{\left(\frac{1100}{\sqrt{3}}\right)}^2\right)}=898\mathrm{V}$$

(21)

The PCC voltage of the system shown in the figure demonstrates the condition of the DSTATCOM when it is connected and unconnected to the system. The system without DSTATCOM is unable to maintain the V_t under a linear load condition and changes when there is perturbation, due to the connection of a non-linear load in the system. Thereore, the effectiveness of the CHBMLI-based DSTATCOM is investigated for V_t, considering the voltage disturbance due to perturbation in the load.

5.2.2. Fast Fourier Transform Analysis of Source Current under Various Load Conditions

As the switching frequency changes (i.e., increases in this case), the other important system parameter that is affected is the source current, and the THD in the source current decreases under linear load conditions, as shown in

Table 2. Source current THD (total harmonics distortion) under different switching frequencies.

S. No.	Switching Frequency (Hz)	Source Current (THD %)
1.	1000	0.62
2.	2000	0.58
3.	3000	0.53
4.	4000	0.48
5.	5000	0.43

. Therefore, for a better application of the proposed system, the frequency should be high, while for a multilevel operation, the frequency should be kept within optimal limits to ensure that the switching losses do not exceed acceptable limits, as shown in Figure 19, Figure 20 and Figure 21.

A current THD of less than 5% is acceptable, as per IEEE Standard 519-1992 (IEEE Recommended Practices and Requirements for Harmonic Control in Electric Power Systems). The reduction in the source current distortion illustrates the effectiveness of components such as the MLI, the LCL filter, and the DC link capacitor, and that of the switching technique at different frequencies. To provide a complete DSTATCOM design with an appropriate control algorithm to prevent losses, avoid system complexity, and maintain operational stability, the control algorithm and all of the parameters must be selected correctly.

5.3. Effect of System Parameters

5.3.1. DC Link Capacitor

In this analysis of the DSTATCOM, the two important components that have been analyzed are the DC link capacitor and the coupling filter. The DC link capacitor is a prominent part of the proposed DSTATCOM system, in that each H-bridge cell contains an isolated DC link capacitor. In custom power device applications, it is desirable for the DC link capacitor to be small in size when compared with the AC capacitor bank, to compensate for the same amount of reactive power. The modulation index is kept constant by the insertion of a proportional controller into the system. The proportional controller maintains the amplitude of the error signal that is obtained by comparing the reference current with the source current. These parameters affect the capacitor value and vice versa, as depicted in Equation (6); this is verified by various results that were obtained by correct modelling of the system. The DC link capacitance affects the ripple in the DC bus voltage, irrespective of the applied filter.

While the system operation is quite complex, it is often found that the value of the DC link capacitor is also a very important factor in the current system, so further analysis is conducted based on different capacitor values and the performance is illustrated in the results. As the results show, different capacitor values produce different overshoot values, which can be easily understood using the results presented here. The voltage ripple in the DC link is inversely proportional to the capacitance value. This means that to produce a lower ripple in the DC link, it is necessary to choose the optimum capacitor value. The relationship between the voltage ripple and the capacitance is illustrated by the results shown in Figure 22a–c, which were obtained using capacitor values of 650, 950, and 1200 µF during linear load operation of the DSTATCOM. The simulation results obtained verify the relationship expressed in Equation (9) and we see that as the capacitor value increases, the ripples in the DC voltage decrease. Similarly, the transient response of the DC link voltage can be obtained for different capacitor values of 650, 800, and 950 µF, as shown in Figure 23. In this case, the switching frequency is kept constant at 1000 Hz and the load is changed at 0.5 s.

5.3.2. Switching Frequency

In this paper, the LCL filter is proposed for a lower switching frequency range and the differences in the system performance under these conditions are also analyzed. The analysis is also conducted on the basis of the switching frequency, as it varies from 1 kHz to 5 kHz. As we see, the switching frequency does not affect the DC voltage ripples in this case, and subsequent results confirmed that a variation of the switching frequency does not affect the DC voltage ripples, as shown in Figure 24. The magnitude of the ripples is almost identical for the three different switching frequencies.

6. Conclusions

An LCL filter interfaced cascaded H-bridge multilevel inverter-based (five-level) DSTATCOM is comprehensively analyzed and investigated considering load conditions, the power quality performance, and the effect of system parameters. The DC-link voltage is maintained using a PI controller for each H-bridge. The LCL filter is designed considering the constraints for a lower operating switching frequency (1–5 kHz) of CHBMLI. The performance of the CHBMLI-based DSTATCOM is evaluated for reactive power compensation, harmonic compensation, and load balancing under a linear load, Non-linear load, and unbalanced load condition. The power quality issues are investigated for a disturbance in the PCC voltage (voltage sag and swell) under an unbalanced load and load change condition. The source current THD under different load conditions (0.51% linear load, 0.79% unbalanced load, 4.59% nonlinear load) is achieved and is well within the IEEE-519 standards of 5%. The effect of switching frequency and the DC link capacitor on the DC link voltage ripples is investigated, to provide the optimum selection of system parameters.