An Isolated Three-Port Bidirectional DC-DC Converter with Enlarged ZVS Region for HESS Applications in DC Microgrids

Abstract

In this paper, a two-stage three-port isolated bidirectional DC-DC converter (BDC) for hybrid energy storage system (HESS) applications in DC microgrids is proposed. It has an enlarged zero-voltage-switching (ZVS) region and reduced power circulation loss. A front-end three-phase interleaved BDC is introduced to the supercapacitor (SC) channel to compensate voltage variations of SC. Consequently, wide ZVS range and reduced circulation power loss for SC and DC bus ports are achieved under large-scale fluctuating SC voltage. Furthermore, a novel modified pulse-width-modulation (PWM) and phase-shift (PHS) hybrid control method with two phase-shift angles is proposed for BA port. And it contributes to an increasing number of switches operating in ZVS mode with varying battery (BA) voltage. Phase shift control with fixed driving frequency is applied to manage power flow. The ZVS range as well as the current stress of resonant tanks under varying port voltages is analyzed in detail. Finally, a 1 kW prototype with peak efficiency of 94.9% is built, and the theoretical analysis and control method are verified by experiments.

1. Introduction

The development and utilization of renewable energy have turned out to be new solutions for the worldwide energy depletion and environmental pollution problems [1]. In order to achieve efficient utilization of distributed energy generations, DC microgrid has become a research focus in recent years [2,3,4]. However, the output of several renewable energy sources is intermittent and time-varying, and the load demand is uncertain [5]. Therefore, storage units are usually used to balance the power supplies and loads in DC microgrids. Several studies use hybrid energy storage systems (HESSs), which are composed of SC and BA, to improve stability and reliability of DC microgrid [6,7,8]. Numerous literatures have researched on energy management and power sharing strategy of HESS in DC microgrid [9,10,11,12,13,14,15,16]. While, the design of interface converters between HESS and DC microgirds is still considered as an emerging area of research.

Three-port BDC, which integrates SC and BA converters into one dual-input converter, will assist to improve the efficiency, power density and control coordination of HESS converters. Many three-port BDCs have been reported in literatures. According to the connection methods, three-port BDCs can be categorized into three types: non-isolated, partly-isolated and isolated converters. Typical structures of three-port BDCs are shown in Figure 1 [17].

Figure 1a shows the diagram of non-isolated three-port converter [18,19], and Figure 1b presents the topology of partly-isolated converter [20,21,22]. The common shortcomings of non-isolated and partly-isolated three-port converters are the lack of complete electrical isolation among three ports, and being unable to cope with wide operating voltage ratio. For the HESS application, security is of great importance, and thus, electrical isolation is essential. In consequence, the isolated structure shown in Figure 1c is adopted in this article [23,24].

Numerous isolated three-port DC-DC converters have been proposed to integrate two energy sources into one dual-input converter. The three-port triple-active-bridge (TAB) converter shown in Figure 2, as the most widely disseminated isolated three-port topology, attracts a lot of attentions from researchers [23,24,25,26,27,28,29]. In [26], a TAB converter is used to deal with a hybrid energy source consisting of full cell and super capacitor. It appears that TAB converter has attractive features of galvanic isolation, bidirectional power flow, ZVS operation and phase shift control with fixed switching frequency. However, power transfer among three ports in TAB is coupled, therefore, decoupling control algorithm is required. What’s more, the power transmission of TAB topology is inversely proportional to the impedance of inductance. While, the inductance of TAB is inherent greater than the leakage inductor of transformer. In case of high power levels, switching frequency has to be reduced to get realizable inductance value. In [26,27,28,29] the driving frequency are all 20 kHz, and this will be detrimental for realizing high power density.

In order to solve problems of TAB mentioned above, a series-resonant (SR) based converter is proposed in [30]. The impedance of SR tank is determined by value of inductor and capacitor together with the switching frequency. Therefore, it can operate at higher frequency under high power level. In [31,32], renewable source, battery and load are integrated to a three-port SR BDC. The driving frequency is 100 kHz, which is apparently higher than 20 kHz of TAB as shown in [26,27,28,29]. What’s more, power flow among three ports can be controlled independently since there are only two SR tanks. Nevertheless, the three-port SR BDC still suffers disadvantages including losing ZVS operation and increased current stress under wide voltage variations. However, previously published works mainly concentrated on the operating characteristics of SR BDC with fixed port voltages. The methods, which can enlarge ZVS region and reduce circulation power loss under varying port voltages, are still considered as emerging area of research.

Two methods for enlarging ZVS range and decreasing power circulation loss under DAB and TAB topologies are reported in [33,34,35,36]. One method is to adopt improved control algorithm. Literature [34] has presented an improved modulation control approach, where two phase-shift angles are employed to minimize the switching losses for DAB under light load. Another alternative method is to use a front-end converter to keep input voltage of bridge constant, as suggested in [36]. These two methods effectively improve the characteristics of TAB converters with wide voltage variations. Unfortunately, few of literatures have ever investigated the validity of these two methods in three-port SR BDC under varying port voltages.

Based on the SR BDC, this article proposes a two-stage three-port BDC to integrate HESS and DC microgrid. The subject of this paper is to enlarge the ZVS operating range and to reduce the circulation power loss of the proposed three-port SR BDC. Then, by comprehensively considering the large SC’s and small BA’s voltage fluctuation ranges, two different methods are adopted in SC and BA channels respectively. For the SC channel, a three-phase interleaved BDC is introduced to convert the widely fluctuating V_SC to a fixed voltage V_dc-link. This method guarantees the unity voltage gain between SC and DC bus ports. The BDC adopts the interleaved structure to improve the power level of the BDC, and to reduce the SC current ripple as well as the inductor size [37,38]. Additionally, a PWM and PHS (PWM-PHS) control method is developed to enlarge ZVS operating range when the voltage gain between DC bus and BA ports is greater than 1. The control objectives of three-port SR BDC and there-phase interleaved BDC are to maintain the DC bus voltage and dc-link voltage stable respectively. Finally, a prototype platform is built to verify the feasibility of the proposed topology. The structure of this article is organized as followings: the topology of proposed converter is given in Section 2. Operating principles are introduced in Section 3. Section 4 explains the variation of ZVS region and the peak value of resonant current under varying voltage gain. Principles of the proposed PWM-PHS control method are also introduced in Section 4. Finally, the experimental results are presented in Section 5, while the conclusion is drawn in Section 6. The main contributions of this paper are summarized below:

(1)

A new two-stage three-port isolated BDC topology is proposed to integrate SC and BA.

(2)

Methods to enlarge ZVS region and to reduce power circulation loss for three-port SR BDC under varying port voltages are first investigated.

(3)

A front-end converter in SC channel is introduced to keep input of full bridge constant. For BA channel, PWM-PHS control method is developed to improve the characteristics of the proposed three-port BDC.

(4)

By adopting the two-stage structure, all switches of SC and DC bus ports have realized ZVS with variable V_SC. By applying the proposed PWM-PHS control method, two more switches of BA port realize ZVS even under the worst input voltage condition of M_BA = 1.15.

2. Proposed System

The overall structure of the proposed two-stage three-port BDC is shown in Figure 3. It contains two parts: a three-port SR BDC and a three-phase interleaved BDC. Three-port SR BDC is presented to maintain DC bus voltage stable and to control power transmission among three ports. The function of three-phase interleaved BDC is converting the widely fluctuating super capacitor voltage V_sc to a constant voltage V_dc-link.

2.1. Three-Port SR BDC

The three-port SR BDC is composed of a three-winding transformer, three full bridges and two SR tanks formed by C_r1, L_r1 and C_r2, L_r2 respectively. The three-winding transformer provides electrical isolation among three ports. What’s more it has inherent bidirectional power flow characteristic, since all power switches of three full bridges are MOSFETs. The converter works at a constant switching frequency f_s, which is above the resonant frequency of SR tanks. As a consequence, it works only in continuous current mode. Phase shift control method is implemented, the amount and direction of transmitted power are controlled by the phase shift angles. All the switches of the three full bridges work with 50% duty cycle.

Through theoretical analysis, the three-port SR BDC is shown to have the best operating characteristics such as maximum ZVS operating region, reduced current stress and cutoff current only under unity voltage gain among three ports. Whereas, the voltage of SC has a large fluctuation range with the change of residual energy. To solve the contradictions of the varying V_SC and the best operating voltage gain restraint of SR BDC, a three-phase interleaved BDC is applied in the system. The interleaved BDC is used to convert the widely fluctuating SC voltage to a fixed voltage V_dc-link. However, the fluctuation range of battery voltage is relatively small, the method of converting the battery voltage to a fixed voltage by increasing a BDC converter is not the best solution. In addition, a new PWM-PHS hybrid control strategy which has two phase-shift angles is proposed to improve the operation characteristics of battery channel under a variation range of voltage gain. The proposed control method can increase the number of MOSFETs operating in ZVS.

The features of the three-port SR BDC are:

(1)

Three-port structure with transformer coupling reduces amount of power switches, increases power density.

(2)

Power flow between BA port and DC bus port, SC port and DC bus port are bidirectional.

(3)

Centralized control method of power flow by changing the direction and magnitude of the phase shift angles between three ports is applied.

(4)

Three-phase interleaved BDC is introduced in the SC channel to keep voltage gain M_SC = 1, which guarantee best operating characteristics of SC channel of SR BDC.

(5)

PWM-PHS hybrid control strategy is proposed for the BA channel to increase the number of switches, which can achieve ZVS, under a variation voltage V_BA.

2.2. Three-Phase Interleaved BDC

A three-phase interleaved BDC is introduced to the SC channel of SR BDC to convert the widely fluctuating SC voltage V_SC to a fixed voltage V_dc-link. The SC is connected to the low-voltage side, and the SR BDC is placed on the high-voltage side. When energy flows from SC to the SR BDC, it works at boost mode, and conversely, it works under buck mode.

A non-isolated bidirectional buck/boost converter topology is adopted in this paper. In order to achieve high efficiency and high power density, the converter is designed to operate in discontinuous conducting mode (DCM), such that all the switches realize ZVS, and the buck/boost inductors are minimized. However, the DCM also has the drawback of large current ripple. To reduce current ripple, the interleaved multi-phase structure is introduced to reduce current ripple. All of the interleaved channels adopt the same control strategy, while hold a phase shift of π/3 in driving signal from each other. As a consequence, the inductor currents of three phases are shifted by π/3. Hence, with interleaved inductor currents, the ripple current of SC is minimized. The features of the three-phase interleaved BDC are:

(1)

The structure is simple, and it combines a boost converter together with a buck converter connected in antiparallel.

(2)

Three-phase interleaved structure is adopted to reduce current ripple, improve power level and reduce current stress of the converter.

(3)

It works under DCM, which can reduce the inductance value.

(4)

Two MOSFETs of one phase-leg conduct complementarily, and the inductor operates under DCM condition, and thus ZVS of MOSFETs is achieved.

3. Operating Analysis

In this section, operating principles of three-port SR BDC and three-phase interleaved BDC are introduced respectively. For the three-port SR BDC, relationship between phase shift angle and power transmission is deduced. What’s more, ZVS soft-switching realizing region and current stress of the resonant tank are analyzed in detail. For three-phase interleaved BDC, the operating principle as well as the inductance designing method is introduced.

3.1. Operating Principle of Three-Port SR BDC

The proposed three-port SR BDC is shown in Figure 4. It is composed of three full bridges, a three-winding transformer, two SR tanks formed by C_r1 and L_r1, C_r2 and L_r2, and filter capacitors C_f1–C_f3. Port 1 is connected to SC through a three-phase interleaved BDC, port 2 is and port 3 are BA port and DC bus respectively. Phase shift method is applied among three ports to control the direction and magnitude of the power transmission, all the switches of the converter are driven at 50% duty cycle. Since the voltage of three ports are constant dc, V_T1, V_T2 and V_T3 are square-waves with amplitudes of ±V_dc-link, ±V_BA and ±V_bus respectively. In the subsequent analysis, phase shift angles of SC and BA ports are defined as φ₁ and φ₂, which are shown in Figure 4. They control the phase shift between the square-wave outputs of the active bridges. The phase shifts φ₁ and φ₂ are considered positive if V_T1 and V_T2 lead V_T3, and conversely, φ₁ and φ₂ are considered negative.

3.1.1. Operating Mode Analysis

The operating principles when both SC and BA ports are providing energy to DC bus port are analyzed. In this condition both φ₁ and φ₂ are positive. The theoretical waveforms, when φ₁ > φ₂ > 0, are shown in Figure 5.

There are 18 different intervals in one switching cycle. Dead time is considered in the analysis, however, the charging and discharging intervals of snubber capacitors are very small, and they can be neglected.

Interval 1 (t₀–t₁): S₁ and S₄, S₅ and S₈ are on. This interval is dead time of port 3 and all the switches of port 3 are off. Since i₃ is positive, i₃ flows through the anti-parallel diodes of S₉ and S₁₂. i₁ flows through S₁ and S₄, and i₂ flows through S₅ and S₈. This interval ends at t₁, when S₉ and S₁₂ are turned on.

Interval 2 (t₁–t₂): S₁ and S₄, S₅ and S₈, S₉ and S₁₂ are on. This interval ends when i₂ increases to zero. The anti-parallel diodes of S₉ and S₁₂ conduct prior to the main switches, thus, S₉ and S₁₂ are turned on with ZVS. The operating characteristics of port 1 and 2 are exactly same with interval 1.

Interval 3 (t₂–t₃): This interval begins at t₂ when i₂ increases to zero, and it ends when switches S₁ and S₄ are turned off. During this interval, S₁ and S₄ of port 1, S₅ and S₈ of port 2 and S₉ as well as S₁₂ of port 3 are on. i₁, i₂ and i₃ are positive and flow through S₁ and S₄, S₅ and S₈, and S₉ and S₁₂ respectively.

Interval 4 (t₃–t₄): This interval is dead time of port 1 and all the switches of port 1 are off. i₁ is positive, so i₁ flows through the anti-parallel diodes of S₂ and S₃. During this interval, i₂ and i₃ flow through S₅ and S₈, and S₉ and S₁₂ respectively. This interval ends when S₂ and S₃ are turned on.

Interval 5 (t₄–t₅): At t₄, S₂ and S₃ are turned on, and this interval ends when S₅ and S₈ are turned off. Since the anti-parallel diodes conduct before main switches of S₂ and S₃, S₂ and S₃ are turned on with ZVS. The operating characteristics of port 2 and 3 are identical with interval 4.

Interval 6 (t₅–t₆): At t₅, switches S₅ and S₈ are turned off, this interval ends when i₁ decreases to zero. This interval is dead time of port 2 and all the switches of port 2 are off. i₂ is positive, hence i₂ flows through the anti-parallel diodes of S₆ and S₇. i₁ and i₃ flow through S₂ and S₃, and S₉ and S₁₂ respectively.

Interval 7 (t₆–t₇): This interval begins at t₆ when i₁ decreases to zero, and it ends when S₆ and S₇ are turned on. The difference between interval 7 and 6 is that the direction of i₁ changes. i₂ still flows through the anti-parallel diodes of S₆ and S₇.

Interval 8 (t₇–t₈): At t₇, S₆ and S₇ are turned on, and this interval ends when i₃ decreases to zero. The anti-parallel diodes conduct ahead the main switches of S₆ and S₇, therefore, S₆ and S₇ are turned on with ZVS. The operating characteristics of port 1 and 3 are exactly same with interval 7.

Interval 9 (t₈–t₉): This interval begins at t₈ when i₃ decreases to zero, and it ends when S₉ and S₁₂ are turned off. The difference between interval 9 and 8 is that the direction of i₃ changes. The operating characteristics of port 1 and 2 are exactly the same with interval 8.

Interval 10 (t₉–t₁₀): This interval is dead time of port 3. Because i₃ is negative, so i₃ flows through the anti-parallel diodes of S₁₀ and S₁₁. During this interval, i₁ and i₂ flow through S₂ and S₃, and S₆ and S₇ respectively. This interval ends when S₁₀ and S₁₁ are turned on.

Interval 11 (t₁₀–t₁₁): At t₁₀, S₁₀ and S₁₁ are turned on, and this interval ends when i₂ decreases to zero. The anti-parallel diodes conduct before main switches of S₁₀ and S₁₁, so that S₁₀ and S₁₁ are turned on with ZVS. The operating characteristics of port 1 and 2 are exactly same with interval 10.

Interval 12 (t₁₁–t₁₂): This interval begins at t₈ when i₂ decreases to zero, and it ends when S₂ and S₃ are turned off. The difference between interval 12 and 11 is that the direction of i₂ changes.

Interval 13 (t₁₂–t₁₃): This interval is dead time of port 1. During this interval, i₁ is negative, so i₁ flows through the anti-parallel diodes of S₁ and S₄. i₂ and i₃ flow through S₆ and S₇, and S₁₀ and S₁₁ respectively. This interval ends when S₁ and S₄ are turned on.

Interval 14 (t₁₃–t₁₄): At t₁₃, S₁ and S₄ are turned on and this interval ends at t₁₄ when S₆ and S₇ are turned off. The anti-parallel diodes conduct prior to the main switches of S₁ and S₄, so S₁ and S₄ are turned on with ZVS. The operating characteristics of port 2 and 3 are exactly same with interval 13.

Interval 15 (t₁₄–t₁₅): This interval is dead time of port 2. During this interval, i₂ is negative, thus i₂ flows through the anti-parallel diodes of S₅ and S₈. i₁ and i₃ flow through S₁ and S₄, and S₁₀ and S₁₁ respectively. This interval ends at t₁₅ when i₁ increases to zero.

Interval 16 (t₁₅–t₁₆): This interval begins at t₁₅ when i₁ increases to zero and ends when S₅ and S₈ are turned on. This interval is still dead time of port 2. The difference between interval 16 and 15 is that the direction of i₁ changes.

Interval 17 (t₁₆–t₁₇): This interval begins at t₁₆ when S₅ and S₈ are turned on, and ends when i₃ increases to zero. Because the anti-parallel diodes conduct prior to the main switches of S₅ and S₈, so S₅ and S₈ are turned on with ZVS. The operating characteristics of port 1 and 3 are exactly same with interval 16.

Interval 18 (t₁₇–t₁₈): This interval begins at t₁₇ when i₃ increases to zero, and ends when S₁₀ and S₁₁ are turned off. The difference between interval 18 and 17 is that the direction of i₃ changes.

3.1.2. Analysis for Voltage Source Load

This section analyzes the relationship between phase shift angle and power transmission, ZVS soft-switching realizing condition and peak current of the resonant tank under a given voltage source load.

The equivalent circuits of the three-port SR BDC are shown in Figure 6. In Figure 6a the output of three active bridges are represented by square waves V_T1, V_T2 and V_T3 respectively, and in Figure 6b V_T3 of port 3 is transferred to port 1 and port 2 according to the transformer ratio.

In the proposed three-port SR BDC, L_r1 = L_r2 = L_r, C_r1 = C_r2 = C_r, and the resonant frequency of SR tanks are f_r. The operating frequency of three ports is f_s, which is greater than f_r, and the corresponding angular velocity is ω_s. Then the impedance value of two resonant tanks can be given by:

$$X={\omega }_s{L}_{\mathrm{r}}-\frac{1}{{\omega }_s{C}_{\mathrm{r}}}$$

(1)

The Fundamental Harmonics Approximation (FHA) method is a commonly used approach for steady-state analysis in resonant-type converters. And the accuracy level of the results obtained from FHA is acceptable for our work. To simplify the analysis procedure, all harmonics except fundamental component of all voltages and currents are neglected. V_T1,1, V_T2,1 and V_T3,1 are the fundamental components of square waves V_T1, V_T2 and V_T3, and phase shift angles between port 1 and port 3, port 2 and port 3 are φ₁ and φ₂ respectively. Using the Fourier series, V_T1,1, V_T2,1 and V_T3,1 are shown as follows:

$$V_{\mathrm{T}1,1}=\frac{4V_{\text{dc-link}}}{\pi }\sin \left({\omega }_{s}t+{\phi }_1\right)$$

(2)

$$V_{\mathrm{T}2,1}=\frac{4V_{\mathrm{BA}}}{\pi }\sin \left({\omega }_{s}t+{\phi }_2\right)$$

(3)

$$V_{\mathrm{T}3,1}=\frac{4V_{\mathrm{bus}}}{\pi }\sin {\omega }_{s}t$$

(4)

The variables M_SC and M_BA are defined as the voltage gain between port 1 and port 3, port 2 and port 3 respectively. They are given by (5) and (6):

$$M_{\mathrm{SC}}=\frac{n_{13}{V}_{\mathrm{bus}}}{V_{\text{dc-link}}}$$

(5)

$$M_{\mathrm{BA}}=\frac{n_{23}{V}_{\mathrm{bus}}}{V_{\mathrm{BA}}}$$

(6)

Resonant currents of three ports can be obtained as follows:

$$i_1\left(t\right)=\frac{V_{\mathrm{T}1,1}-n_{13}{V}_{\mathrm{T}3,1}}{jX}=\frac{4V_{\text{dc-link}}}{\pi X}\left[\sin ({\omega }_{s}t+{\phi }_1-{90}^{°})-M_{\mathrm{SC}}\sin ({\omega }_{s}t-{90}^{°})\right]$$

(7)

$$i_2\left(t\right)=\frac{V_{\mathrm{T}2,1}-n_{23}{V}_{\mathrm{T}3,1}}{jX}=\frac{4V_{\mathrm{BA}}}{\pi X}\left[\sin ({\omega }_{s}t+{\phi }_2-{90}^{°})-M_{\mathrm{BA}}\sin ({\omega }_{s}t-{90}^{°})\right]$$

(8)

$$i_3\left(t\right)=n_{13}{i}_1\left(t\right)+n_{23}{i}_2\left(t\right)$$

(9)

Switches in port 1 and port 2 can realize ZVS only when the resonant tank currents lag their applied square wave voltages. While for port 3, the defined positive current direction is contrary to port 1 and 2, the condition for ZVS realization is that the resonant current leads its applied square wave voltage. Then the constraint conditions for ZVS of port 1–3 can be given by (10)–(12) respectively:

$$i_1\left(-\frac{{\phi }_1}{t}\right)=\frac{4V_{\text{dc-link}}}{\pi X}(M_{\mathrm{SC}}\cos {\phi }_1-1)<0$$

(10)

$$i_2\left(-\frac{{\phi }_2}{t}\right)=\frac{4V_{\mathrm{BA}}}{\pi X}(M_{\mathrm{BA}}\cos {\phi }_2-1)<0$$

(11)

$$i_3\left(0\right)=n_{13}\frac{4V_{\text{dc-link}}}{\pi X}(M_{\mathrm{SC}}-\cos {\phi }_1)+n_{23}\frac{4V_{\mathrm{BA}}}{\pi X}(M_{\mathrm{BA}}-\cos {\phi }_2)>0$$

(12)

By calculating the maximum value of i₁(t) and i₂(t), the peak current of two resonant tanks can be derived as:

$$i_{1\max }=\frac{4V_{\text{dc-link}}}{\pi X}\sqrt{1+{M_{\mathrm{SC}}}^2-2M_{\mathrm{SC}}\cos {\phi }_1}$$

(13)

$$i_{2\max }=\frac{4V_{\mathrm{BA}}}{\pi X}\sqrt{1+{M_{\mathrm{BA}}}^2-2M_{\mathrm{BA}}\cos {\phi }_2}$$

(14)

The transferred power from SC and BA ports to the bus port can be calculated as follows:

$$P_1=\frac{1}{2\pi }{\displaystyle {\int }_0^{2\pi }{V}_{\mathrm{T}1}(t)\cdot }{i}_1(t)d({\omega }_{s}t)=\frac{8{V_{\text{dc-link}}}^2{M}_{\mathrm{SC}}}{{\pi }^{2}X}\sin {\phi }_1$$

(15)

$$P_2=\frac{1}{2\pi }{\displaystyle {\int }_0^{2\pi }{V}_{\mathrm{T}2}(t)\cdot }{i}_2(t)d({\omega }_{s}t)=\frac{8{V_{\mathrm{BA}}}^2{M}_{\mathrm{BA}}}{{\pi }^{2}X}\sin {\phi }_2$$

(16)

Equations (15) and (16) indicate that the power transferred from SC and BA ports to the DC bus port are proportional to the sinusoidal values of φ₁ and φ₂ respectively. It is obviously that the power transmission is positive when φ₁ and φ₂ values are positive, and conversely the power flow is negative.

3.1.3. Analysis for Resistive Load

This section explains the relationship of voltage gain, power transmission and phase shift angles under a resistive load. If the DC bus port is connected to a pure resistive load, the output voltage V_bus needs to be derived. According to superposition theorem, in the three-port SR BDC with linear resistive load, the output voltage V_bus can be divided into two parts: V_busSC and V_busBA. V_busSC and V_busBA are output voltage values when only one of the two inputs works alone. M_busSC and M_busBA are the corresponding voltage gain, and are given by:

$$M_{\mathrm{busSC}}=\frac{n_{13}{V}_{\mathrm{busSC}}}{V_{\text{dc-link}}}$$

(17)

$$M_{\mathrm{busBA}}=\frac{n_{23}{V}_{\mathrm{busBA}}}{V_{\mathrm{BA}}}$$

(18)

Under specific output voltage value and phase shift angles conditions, the transferred power is given in (15) and (16), no matter what kind of load is connected to the DC bus port. If the load resistance is defined as R_L. Combing (15) and (16), the output power P₁ and P₂, when V_dc-link and V_BA work alone, can be given by:

$$P_1=\frac{{V_{\mathrm{busSC}}}^2}{R_{\mathrm{L}}}=\frac{8{V_{\text{dc-link}}}^2{M}_{\mathrm{busSC}}}{{\pi }^{2}X}\sin {\phi }_1$$

(19)

$$P_2=\frac{{V_{\mathrm{busBA}}}^2}{R_{\mathrm{L}}}=\frac{8{V_{\mathrm{BA}}}^2{M}_{\mathrm{busBA}}}{{\pi }^{2}X}\sin {\phi }_2$$

(20)

By combing (17)–(20), the voltage gain M_busSC and M_busBA can be given as follows:

$$M_{\mathrm{busSC}}=\frac{8{n_{13}}^2{R}_{\mathrm{L}}}{{\pi }^{2}X}\sin {\phi }_1$$

(21)

$$M_{\mathrm{busBA}}=\frac{8{n_{23}}^2{R}_{\mathrm{L}}}{{\pi }^{2}X}\sin {\phi }_2$$

(22)

According to the superposition theorem, the output voltage V_bus with resistive R_L can be given by:

$$V_{\mathrm{bus}}=\frac{8n_{13}{R}_{\mathrm{L}}}{{\pi }^{2}X}\sin {\phi }_1{V}_{\text{dc-link}}+\frac{8n_{23}{R}_{\mathrm{L}}}{{\pi }^{2}X}\sin {\phi }_2{V}_{\mathrm{BA}}$$

(23)

3.2. Operating Principle of Three-Phase Interleaved BDC

The operating principles of the three-phase interleaved BDC are analyzed in this section. The proposed three-phase interleaved BDC is shown in Figure 7. When power transfers from SC to the dc-link, it works under boost mode and switches Q_D1–Q_D3 are main switches. If direction of power transfer is reversed, the BDC works under buck mode and switches Q_U1–Q_U3 are main switches. L₁–L₃ are buck/boost inductors, C₁ and C_f1 are filter capacitors. By adopting three-phase interleaving structure, current ripple of SC port can be minimized and thus the required filter capacitance can be reduced.

For the proposed three-phase interleaved BDC, switches of one phase leg conduct complementarily, and the inductor current can go through from positive to negative and then raise to positive. This will ensure all the switches realize ZVS turn on.

The three-phase interleaved channels adopt the same control strategy, but hold a phase shift of π/3 in driving signal. In order to simplify the analysis, the operating characteristics of single phase are introduced. Circuit diagram of single phase is shown in Figure 8, and theoretical waveforms under boost mode are shown in Figure 9.

The parameters are defined as follows: V_SC and V_dc-link are the voltage of SC and dc-link; i_L and v_L are voltage and current of the buck/boost inductor L; i_max and i_min are the maximum and minimum value of i_L respectively; Δi is the variation of i_L during one switching cycle; i_SC is the current of SC. t_db is dead band time; T_s is switching period; t_D and t_U are the conducting time of Q_U and Q_D separately.

For single-phase BDC, there are four different intervals in one switching cycle. Same as the above analysis of three-port SR BDC, dead time is considered, while charging and discharging intervals of snubber capacitors are neglected.

Interval 1 (t₀–t₁): This interval is dead band time, both Q_U and Q_D are off, and it ends when Q_D is turned on. During this interval, i_L < 0 and it flows through the anti-parallel diode of Q_D. If the conduction voltage drop of anti-parallel diode is neglected, v_L = V_SC and i_L increases linearly.

Interval 2 (t₁–t₂): During this interval, Q_D is on and Q_U is off, i_L flows through Q_D. Since the anti-parallel diodes conduct prior to the main switches of Q_D, thus it is turned on with ZVS. Same as interval 1, i_L increases linearly.

Interval 3 (t₂–t₃): This interval is also dead band time, both Q_U and Q_D are off, and it ends when Q_U is turned on. Different from interval 1, during this interval i_L > 0, so it flows through the anti-parallel diode of Q_U. v_L = V_SC − V_dc-link and this value is less than zero, so i_L decreases linearly.

Interval 4 (t₃–t₄): During this interval, Q_U is on and Q_D is off. i_L flows through Q_U. Same as interval 3, i_L decreases linearly. Since the anti-parallel diodes conduct before main switches of Q_U, it is turned on with ZVS.

Compared to t_D and t_U, t_db can be ignored, so Δi can be derived as follows:

$$\Delta i=\frac{V_{\mathrm{SC}}}{L}\cdot \frac{V_{\text{dc-link}}-V_{\mathrm{SC}}}{V_{\text{dc-link}}}\cdot T_{\mathrm{S}}$$

(24)

To maintain ZVS switching of Q_U and Q_D, it must be ensured that i_max > 0 and i_min < 0.

4. ZVS Region Analysis and Proposed Method for Expanding ZVS Realization Range

Since the transformer voltage of port 3 is clamped by the output voltage V_bus, so there is no direct energy interaction between port 1 and port 2. Thus, the three-port SR BDC can be decomposed into two single input SR BDCs. The ZVS realization and current stress of single channel SR BDC can provide reference for the three-port SR BDC. To simplify the analysis, the ZVS realization region and current stress of single channel SR BDC are analyzed in this section.

4.1. ZVS Region and Current Stress Analysis of Single Channel SR BDC

Through (10)–(12), the ZVS constraint conditions for primary-side and secondary-side can be simplified as follows:

$$\text{Primary-side}:M\cos \phi -1<0$$

(25)

$$\text{Secondary-side}:M-\cos \phi >0$$

(26)

The ZVS regions of primary and secondary sides of single channel SR BDC are shown in Figure 10a,b, respectively. Figure 10a shows that when M < 1 all switches of primary side can realize ZVS, while as shown in Figure 10b, switches of secondary side can only realize ZVS when φ is greater than a certain value. When M > 1 situations are just contrary to situations when M < 1. It can be obtained that, the ZVS realization regions of primary and secondary sides change reversely under varying M. So during the design process, M should be as close to 1 as possible, and M = 1 is the best choice to achieve ZVS for all the switches of primary and secondary sides.

Before analyzing the peak value of resonant current under varying M, it must be noticed that phase shift angles to transfer same power under different M are varying. If we suppose that the phase shift angle under unity voltage gain (M = 1) is φ, and the phase shift angel to transfer same power under varying M is α. The relationship between φ and α is shown in (27) and (28). It is shown in (13) and (14) that with certain input voltage, resonant parameters and switching frequency, the peak value of resonant current is directly proportional to N which is shown in (29). The diagrams of N under M < 1 and M > 1 are shown in Figure 11a,b, respectively:

$$\frac{8{V_{\text{dc-link}}}^2}{{\pi }^{2}X}\sin \phi =\frac{8{V_{\text{dc-link}}}^{2}M}{{\pi }^{2}X}\sin \alpha$$

(27)

$$\alpha =\arcsin \frac{\sin \phi }{M}$$

(28)

$$\begin{array}{l}{i}_{\max }=\frac{4V_{\text{dc-link}}}{\pi X}\times N\\ N=\sqrt{1+M^2-2M\cos \alpha }\end{array}$$

(29)

Figure 11 shows that, when M < 1, the peak current of resonant tanks increases with the decreases of M in a large range. While when M > 1, the peak current increases with the increases of M in a certain range. In the design process, the phase shift must be limited in a relatively small range to restrict cut off current of switches. So, from the point of limiting peak value of resonant current, M should be designed as close to 1 as possible. And M = 1 is the best choice to achieve minimize peak value of resonant current. Through the analysis above, both M_SC and M_BA should be designed to be 1 to achieve best operating characteristics. While the voltages of SC and BA are all not fixed value. To solve this problem, different methods for two channels are proposed.

(1)

For the SC channel, the voltage has a large variation range, and can’t get an ideal operating state only by reasonable parameters design. Therefore, a three-phase interleaved BDC is introduced between SC and port 1 of the three-phase SR BDC. The interleaved BDC is used to convert the widely fluctuating V_SC to a fixed V_dc-link, and thus ensuring M_SC = 1.

(2)

Since voltage variation scale is relatively small for the BA channel, it is not essential to add BDC converter as SC channel does. A new PWM-PHS control strategy is proposed for the BA channel. The newly proposed control method has two phase shift angles for modulation, and can increase number of MOSFETs which can realize ZVS.

4.2. Proposed PWM and Phase Shift Hybrid Control Strategy

The difference of the newly proposed PWM-PHS control strategy and the traditional phase shift control method is that there are two phase-shift angles to modulate for the BA channel. This can provide more control flexibility, and can increase the number of ZVS switches under a wide variation of V_BA. In this method, two switches in each phase leg also work complementary with 50% duty cycle. The two phase legs of BA port are defined as phase leg A and phase leg B, and corresponding phase shift angles are represented as φ_2A and φ_2B respectively. The phase shift angles between two legs is δ, φ_2B = φ_2A − δ. While, when S5 and S7, or S6 and S8 conduct together, the instantaneous value of V_T2 is zero, so the pulse width of is not 180° any more. The pulse width of the newly proposed control method is (180 − δ)°, so it can be regarded as the combination of PWM and PHS control. The theoretical waveforms for the BA channel under PWM-PHS control strategy is shown in Figure 12.

The fundamental components of square waves V_T2 under PWM-PHS control method can be shown as (30). Referring to the analysis above, the resonant current and power transmission value of port 2 under PWM-PHS control method can be shown as (31) and (32) respectively:

$$V_{\mathrm{T}2,1}=\frac{2V_{\mathrm{BA}}}{\pi }\left[\sin \left({\omega }_{s}t+{\phi }_{2\mathrm{A}}\right)+\sin \left({\omega }_{s}t+{\phi }_{2\mathrm{B}}\right)\right]$$

(30)

$$i_2\left(t\right)=\frac{2V_{\mathrm{BA}}}{\pi X}\left[\sin ({\omega }_{s}t+{\phi }_{2\mathrm{A}}-{90}^{°})+\sin ({\omega }_{s}t+{\phi }_{2\mathrm{B}}-{90}^{°})-2M_{\mathrm{BA}}\sin ({\omega }_{s}t-{90}^{°})\right]$$

(31)

$$P_2=\frac{4{V_{\mathrm{BA}}}^2{M}_{\mathrm{busBA}}}{{\pi }^{2}X}(\sin {\phi }_{2\mathrm{A}}+\sin {\phi }_{2\mathrm{B}})=\frac{4{V_{\mathrm{BA}}}^2{M}_{\mathrm{busBA}}}{{\pi }^{2}X}[\sin {\phi }_{2\mathrm{A}}+\sin ({\phi }_{2\mathrm{A}}-\delta )]$$

(32)

The ZVS constraint conditions for phase leg A and B of primary side and secondary side can be shown as follows:

$$\begin{array}{cc}\text{Primary-side leg A}:& i_2\left(-\frac{{\phi }_{2\mathrm{A}}}{t}\right)=\frac{2V_{\mathrm{BA}}}{\pi X}(2M_{\mathrm{BA}}\cos {\phi }_{2\mathrm{A}}-1-\cos \delta )<0\end{array}$$

(33)

$$\begin{array}{cc}\text{Primary-side leg B}:& i_2\left(-\frac{{\phi }_{2\mathrm{B}}}{t}\right)=\frac{2V_{\mathrm{BA}}}{\pi X}[2M_{\mathrm{BA}}\cos ({\phi }_{2\mathrm{A}}-\delta )-\cos \delta -1]<0\end{array}$$

(34)

$$\begin{array}{cc}\text{Secondary-side}:& i_2\left(0\right)=\frac{2V_{\mathrm{BA}}}{\pi X}(2M_{\mathrm{BA}}-\cos {\phi }_{2\mathrm{A}}-\cos {\phi }_{2\mathrm{B}})>0\end{array}$$

(35)

Equations (26) and (35) show that when M_BA > 1, all switches of secondary side can realize ZVS under traditional control method and the newly proposed PWM-PHS control method. Therefore, only the ZVS realization conditions for the primary side are analyzed. The designed maximum value of M_BA is 1.15, and the following analysis is under condition of M_BA = 1.15.

To transfer same power under traditional phase shift control method and newly proposed PWM-PHS control method, phase shift angles of φ₂, φ_2A and δ should satisfy the constraint condition shown in (36) and (37). The diagram of ZVS operating range of primary side phase leg A and B for the variation of δ under M_BA = 1.15 is given in Figure 13:

$$\frac{8{V_{\mathrm{BA}}}^2{M}_{\mathrm{busBA}}}{{\pi }^{2}X}\sin {\phi }_2=\frac{4{V_{\mathrm{BA}}}^2{M}_{\mathrm{busBA}}}{{\pi }^{2}X}[\sin {\phi }_{2\mathrm{A}}+\sin ({\phi }_{2\mathrm{A}}-\delta )]$$

(36)

$${\phi }_{2\mathrm{A}}=\arcsin [\frac{\sin {\phi }_2}{\cos (0.5\delta )}]+\frac{\delta }{2}$$

(37)

Figure 13a,c shows the ZVS range of phase leg A and B in the primary side, Figure 13b,d is the zoom-in diagrams of Figure 13a,c, respectively. The enlarged ZVS range of phase leg A and B are defined as η and γ respectively. Figure 13 shows that the ZVS range of phase leg A and B can be enlarged with the increase of δ. The enlarged ZVS range of phase leg A and B are represented in Figure 13b,d. During η and γ, the ZVS MOSFETs number of primary side under traditional phase shift control (δ = 0) is 0, while the ZVS MOSFETs number under PWM-PHS control (δ ≠ 0) is 2.

The theoretical analysis results prove that the proposed PWM-PHS control method can increase the number of MOSFETs which can realize ZVS under specific power condition.

4.3. Control Strategy of the Proposed Two-Stage Three-Port BDC

Through the proposed two-stage three-port BDC, HESS is integrated to the DC bus of DC microgrid. The proposed three-port BDC is composed of two parts: three-port SR BDC and three-phase interleaved BDC. The control target of three-port SR BDC is to keep DC bus voltage constant by compensating the mismatch between generation and demand. Meanwhile, the control objective of the three-phase interleaved BDC is converting the widely fluctuating SC voltage V_sc to a constant voltage V_dc-link. The control scheme for the proposed two-stage three-port BDC is shown in Figure 14.

The basic idea of the three-port SR BDC is that the battery supports slow transients, and SC supports fast transients. The control structure has an inner current loop as well as an outer control loop for voltage stabilization. The bus voltage V_bus is compared with the reference voltage V_bus*, and the deviation of voltage is tracked by the voltage PI controller to produce the total current reference i_bus*. By using a low-pass filter (LPF), the total current is divided into a dynamic component i_{bus_SC}* and an average component i_{bus_BA}*. Then, the reference currents of SC and BA are derived as i_P1* and i_P2* respectively. Through the inner current loops, phase shift angles are adjusted to maintain a constant DC bus voltage.

The control objective of the three-phase interleaved BDC is to keep the dc-link voltage constant. Same with the control method of three-port SR BDC, V_dc-link is compared with reference voltage V_dc-link*. The current reference is obtained through the outer voltage loop. Combining the current reference and voltage values, the driving frequency f and duty ratio D are deduced. Through the interleaved PWM generator, driving signals of three-phase interleaved BDC are acquired.

5. Experimental Results

To verify the validity of theoretical analyses, a 1 kW prototype was built in the laboratory. The MOSFETs adopted in the system are C3M0065090D units from CREE (Durham, NC, USA). The control platform is a TMS320F28379D from Texas Instruments (Dallas, TX, USA). Based on the theoretical analysis above, a set of optimized parameters of the proposed system are selected and shown in

Table 1. Parameters of the proposed system.

Converter Parameter	Value
Resonant Inductor Lr1 and Lr2	15 μH
Resonant Capacitors Cr1 and Cr2	141 nF
Transformer turns ratio n13:n23:1	0.425:0.51:1
Port 1 voltage Vdc-link	85 V
Port 2 voltage VBA	90 V–102 V
Port 3 voltage Vbus	200 V
Voltage Gain MSC	1
Voltage Gain MBA	1–1.15
Super Capacitor Voltage VSC	30 V–75 V
Buck/Boost Inductor of BDC L	15 μH

.

5.1. SC and BA Charging Mode

For the SC and BA charging mode, a 200 V voltage source is provided for port 3, port 1 and port 2 are connected to resistive loads of 15 Ω, in this experiment V_T1 and V_T2 lag V_T3. Port 1 and 2 are entirely independent from each other. The concrete data of this experiment are as follows: input voltage V_bus = 200 V, output voltage V_dc-link = 84 V, driving frequency f_s = 130 kHz, φ₁ = −18.5°, φ₂ = −20°; V_BA = 102 V, P₁ = −458.2 W, P₂ = −684.5 W, P₃ = −1204.3 W. The efficiency is 94.9%. M_SC = M_BA = 1, thus all switches of 3 ports can realize ZVS. The required phase shift angles to realize M_SC = M_BA = 1 are compared in

Table 2. Comparison of φ₁ and φ₂ under theoretical calculation and experiment.

Method	φ1	φ2
Theoretical Calculation	−19.1°	−19.1°
Experiment	−18.5°	−20°

. It is proved that the experimental results are consistent with theoretical analysis.

Figure 15 shows the waveforms of resonant currents of the three-port SR BDC.

Figure 16 shows the waveforms of resonant currents and transformer voltages of three ports. Figure 16a,b show the operating waveforms of port 1, such as resonant current i₁, drain-source voltage and driving voltage of S1 v_{DS_S1} and v_{G_S1}. Figure 16b is the zoom-in waveforms of Figure 16a, from it we can see that the MOSFETs of port 1 can realize ZVS. Figure 16c,d show the operating waveforms of port 2, resonant current i₂, drain-source voltage and driving voltage of S₅ v_{DS_S5} and v_{G_S5}. Figure 16e,f show waveforms of port 3. It is shown that MOSFETs of port 2 and 3 can realize ZVS under SC and BA charging mode with M_SC = M_BA = 1.

5.2. SC and BA Discharging Mode

In the SC and BA discharging mode, two voltage sources are connected to SC and BA port respectively, a resistive load of 40 Ω is connected to port 3. Power is transferred from port 1 and 2 to port 3. Both M_busSC and M_busBA are designed as 0.5. The concrete data of this experiment are as follows: input voltage V_SC = 30 V, V_BA = 102 V, V_dc-link = 85 V, output voltage V_bus = 200 V; driving frequency f_s = 130 kHz, φ₁ = 18.2°, φ₂ = 13.4°; P₁ = 521.5 W, P₂ = 533.9 W, P₃ = 993.1 W. The efficiency of two stage three-port BDC is 94.1%. All switches of three ports can realize ZVS.

The required phase shift angles to realize M_busBA = M_busSC = 0.5 are compared in

Table 3. Comparison of φ₁ and φ₂ under theoretical calculation and experiment.

Method	φ1	φ2
Theoretical Calculation	19.8°	13.6°
Experiment	18.2°	13.4°

. It is proved that the experimental results are consistent with theoretical analysis. For the three-phase interleaved BDC, inductor currents i_L1–i_L3 and V_dc-link are shown in Figure 17, and they are completely consistent with the theoretical analysis waveforms.

Figure 18 shows the waveforms of resonant currents of three ports. Figure 19a shows i₁, v_{DS_S1} and v_{G_S1} of port 1. Figure 19c shows i₂, v_{DS_S5} and v_{G_S5} of port 2. Figure 19e shows i₃, v_{DS_S9} and v_{G_S9} of port 3. Figure 19b,d,f is enlarged waveforms of Figure 19a,c,e. The waveforms of three ports are consistent with analysis above, and all MOSFETs of three-ports can realize under conditions when M_SC = M_BA = 1.

5.3. Proposed PWM-PHS Control Method

The effectiveness of proposed PWM-PHS control method is verified based on the BA channel for battery discharging mode. A 80 Ω resistive load is connected to port 3. The operating parameters are defined as follows: V_BA = 45 V, V_bus = 100 V, M_BA = 1.15. Two groups of contrast experiment are done, two groups adapt traditional phase-shift and the newly proposed PWM-PHS control method, respectively.

The operating parameters under traditional phase shift control method are as follows: driving frequency f_s = 130 kHz, φ_2A = φ_2B = 23.4°, P₂ = 138.3 W, P₃ = 124.6 W, the efficiency is 90.1%. Figure 20a,c shows the operating waveforms of port 2 and 3. Resonant current i₂, drain-source voltage and driving voltage of S5 and S9 are given. Figure 20b,d is enlarged waveforms of Figure 20a,c. Experimental results show that MOSFETs of BA port can’t realize ZVS, MOSFETs of DC bus port operate under ZVS when M_BA = 1.15.

As shown in Figure 20a,b, MOSFETs of BA port can’t realize ZVS, drive signal of S5 turns positive before the output capacitor of S5 gets fully discharged. Parasitic ringing, which is due to oscillation between output capacitance of S5 and parasitic inductance present in the converter layout, occurs during turn-on switching transient. In Figure 20c,d, output capacitor is fully discharged before driving signal turns positive. Consequently, ZVS is achieved for MOSFETs of DC bus port, and parasitic ringing is avoided.

The operating parameters under phase shift control method are as follows: driving frequency f_s = 130 kHz, φ_2A =35.8°, φ_2B = 10.8°, P₂ = 134.8 W, P₃ = 125 W, the efficiency is 92.7%. The efficiency is relatively low since the power level is low.

Figure 21a,c shows the operating waveforms of phase leg A and B of port 2 respectively. Figure 21e shows waveforms of port 3. Resonant current i₂, drain-source voltage and driving voltage of S5, S7 and S9 are given. Figure 21b,d,f is enlarged waveforms of Figure 21a,c,e. Experimental results show that MOSFETs of phase A of BA port realize ZVS, MOSFETs of phase B of BA port can’t realize ZVS, MOSFETs of DC bus port achieve ZVS operating when M_BA = 1.15.

Like the conditions shown in Figure 20a,b, MOSFETs of phase B can’t realize ZVS, and parasitic ringing presents during the turn-on switching transients. The experimental results above show that, when using traditional phase shift control method, only four switches can realize ZVS, and the efficiency is 90.1%. While, by adopting the newly proposed, the number of switches which can realize ZVS increases to 6, and the efficiency increases to 92.7%. The experimental results are consistent with theoretical analysis. It is proved that the PWM-PHS control method can improve operating characteristics of SR BDC under the condition of M_BA > 1.

6. Conclusions

In this paper, a two-stage three-port BDC is fabricated to interface SC and BA with the DC microgrid. It is composed of a three-port SR BDC and a three-phase interleaved BDC. The particular two-stage structure makes it possible to handle wide voltage variations at SC port, and will ensure unity voltage gain between SC and DC bus ports. In addition, a PWM-PHS hybrid control method is applied on the BA channel. The proposed control method contributes to an increasing number of switches operating under ZVS under variable voltage gain. Together with the proposed PWM-PHS control strategy, the proposed BDC acquires optimized operation characteristics with both enlarged ZVS range and reduced power circulation loss. Finally, a 1 kW prototype is built, and the efficiency of SC and BA charging and discharging mode are 94.9% and 94.1% respectively. The experimental results validate that all switches of SC and DC bus ports can realize ZVS under varying V_SC. With the proposed topology and PWM-PHS control method, two more switches of BA port achieve ZVS even under the worst input condition of M_BA = 1.15.