Analysis of dc-Link Voltage Switching Ripple in Three-Phase PWM Inverters

Abstract

The three-phase voltage source inverter (VSI) is de facto standard in power conversion systems. To realize high power density systems, one of the items to be correctly addressed is the design and selection of the dc-link capacitor in relation to the voltage switching ripple. In this paper, effective formulas for designing the dc-link capacitor as a function of the switching voltage ripple amplitude are obtained, considering the operating conditions such as the modulation index and the output current amplitude. The calculations are obtained considering the requirements and restrictions referring to the high (switching)-frequency dc-link voltage ripple component. Analyses have been performed considering the dc source impedance (non-ideal dc voltage source at the switching frequency) and a balanced load. Analytical expressions are derived for the dc-link voltage switching ripple amplitude and its maximum value over the fundamental period. Different values of modulation index and output phase angle have been considered and different diagrams are presented. Analytical results were validated both by simulations and comprehensive experimental tests.

1. Introduction

Three-phase inverters are customarily adopted, due to their wide availability, in many different applications, such as variable speed ac drives, uninterruptible power supplies (UPS), stand-alone and grid-connected systems, etc. Intensive research on pulse width modulation (PWM) control strategies has been conducted during the last years. Various modulation techniques have been proposed in order to improve the inverter’s performance [1]. The primary target is the reduction in total harmonic distortion (THD) of output currents but also the dc bus utilization, EMI, and switching losses reduction, etc. Among many, the carrier-based PWM (CB-PWM) and space vector PWM (SV-PWM) techniques are the most popular and commonly used. In general, CB-PWM is more popular than the other technique as it has a well-defined harmonic spectrum, fixed switching frequency, easy implementation, and less computation time [2]. On the other side, SV-PWM offers a maximum transfer ratio with lower THD [3]. It is proven that the CB-PWM can work identically to the SV-PWM if a proper common-mode signal is injected (modulation signal centering). Regarding this, both techniques may lead to the same results.

Considering voltage source inverters (VSIs), inverter output characteristics (voltage and current) have been extensively studied recently. However, not many papers have focused on the inverter input (dc-link) side. The peak-to-peak output current ripple amplitude has been calculated over the funda-mental period and presented together with numerical and experimental verification in the case of two-level and multilevel VSIs in [4,5], respectively. The comparison of the output current ripple in the case of multiphase inverters is presented in [6], considering a different number of phases. In [7], the output current ripple analysis has been carried out and the analytical expressions are developed as the basis for the design and implementation of an optimal variable switching frequency (VSF) PWM scheme for three-phase inverters. The effect of selecting a proper discontinuous PWM method regarding the switching losses in three-phase PWM converters is given in [8].

The analysis of the inverter input side (DC-link) is particularly important for the dc-link capacitor’s selection and design. In general, a relevant challenge in inverter system design is to reduce the size and price of the components while improving the inverter performance and reliability. In the PWM inverters, the dc-link capacitor is required to stabilize and smooth the dc-link voltage, keeping the dc-link voltage almost constant. In fact, it can be achieved by connecting the large electrolytic capacitors. However, the large capacitor makes the inverter less compact and reliable. Because of all mentioned, there is a general inverter design requirement to keep the size of the dc-link capacitor as small as possible so the high power density of the entire system can be achieved.

The dc-link voltage ripple is an important parameter in the design consideration of the dc-link capacitor. In a non-ideal or practical dc voltage supply, such as a battery, photovoltaic module, fuel cell, or even the dc-DC converter or PWM rectifier, due to the presence of a series dc impedance, a voltage ripple appears on the dc-link if a switching current ripple circulates through the capacitor. Comprehensive calculations of the dc-link voltage ripple for single-phase H-bridge PWM inverters were first reported in [9], considering both the high- (~10 kHz) and the low-frequency (100 Hz) components. Further analytical developments and experimental verifications have been presented in [10]. Finally, on the basis of the dc-link voltage ripple requirements, simple and effective guidelines for the dc-link capacitor design are proposed.

In general, input current and voltage characteristics for three-phase inverters are usually estimated by using the Fourier analysis and corresponding root mean square (RMS) calculations. The analysis of the input current and voltage have been investigated through the RMS ripple value in [11]. It has been shown that the waveform of the reference signal does not affect inverter input current ripple and that the voltage ripple RMS depends on the load power factor angle. In [12], the dc-link capacitor current RMS is estimated taking into account different continuous and discontinuous PWM techniques. The analytical expression for the current stress on the dc-link capacitor and the experimental verification has been presented in [13] for a three-phase converter system. Based on the Fourier analysis and considering the three-phase balanced load, the dc-link current ripple characteristics have been investigated in [14,15,16]. Similar analyzes under balanced and unbalanced loads are presented in [17], including an investigation of the second harmonic dc-link voltage ripple component. A generalized approach for determining the harmonic spectrum of the dc-link capacitor currents in different two- and three-level VSI topologies has been developed in [18]. In [19,20,21], different modulation methods aimed at reducing the input current harmonics flowing through the dc-link capacitor of the three-phase VSIs have been proposed.

Theoretical analysis of the dc-link voltage switching ripple in a three-phase PWM voltage source inverter with dc source impedance and balanced load has been presented in [22]. This paper further extends those analytical developments and additionally provides numerical and experimental verification of the proposed calculations. In particular, the peak-to-peak dc voltage ripple envelope is analytically defined as a function of the output current amplitude, its phase angle, and the modulation index over the fundamental period. Centered PWM (CPWM) is considered the most popular and effective modulation, easy to be implemented in industrial microcontroller boards, able to maximize the modulation index and to minimize the output current THD, and equivalent to SV-PWM. Different diagrams are obtained showing a wide excursion of the normalized amplitude. Its maximum value is also determined as a function of the modulation index for different output phase angles. Based on the proposed calculations, simple and practical expressions for the dc-link capacitor design are proposed.

2. Basic Inverter Equations

2.1. System Configuration

Figure 1 shows the system under study, which consists of a three-phase VSI with a balanced load. The inverter is supplied by a dc voltage source (V_dc) via a dc source impedance representing an inductive filter (L) and/or an equivalent series resistance (R). The parallel capacitor (C) is connected to the dc bus to smooth the voltage ripple. The balanced load currents i₁, i₂, and i₃ are supposed to be sinusoidal (switching ripple is now neglected) and the output phase angle φ is treated as a degree of freedom.

For a PWM inverter, by neglecting the dc-link voltage oscillations (v ≈ V) and by considering only a linear modulation range, the inverter output phase voltages averaged over the switching period correspond to the reference phase voltages:

$$\{\begin{array}{l}{v}_1^{\ast }=mV\cos (\vartheta )\\ v_2^{\ast }=mV\cos (\vartheta -\frac{2\pi }{3})\\ v_3^{\ast }=mV\cos (\vartheta -\frac{4\pi }{3})\end{array},$$

(1)

where $\vartheta$ = ωt, ω is the fundamental angular frequency (ω = 2πf), and m is the inverter modulation index representing the amplitude of the fundamental output voltage V₀ normalized by the dc supply voltage V; that is, m = V₀/V.

Considering Equation (1), in the case of a balanced load and neglecting the output current ripple, the corresponding three-phase sinusoidal output currents can be written as:

$$\{\begin{array}{l}{i}_1=I_0\cos (\vartheta -\phi ),\\ i_2=I_0\cos (\vartheta -\frac{2\pi }{3}-\phi )\\ i_3=I_0\cos (\vartheta -\frac{4\pi }{3}-\phi )\end{array},$$

(2)

where I₀ and φ are the output current amplitude and the phase angle between the phase voltage and current, respectively.

2.2. Inverter Input Current Components

Generally speaking, the inverter input current i(t) is composed of three components: the dc (average), the low-frequency, and the high-frequency (switching, in order of kHz) component. When the load is balanced, the low-frequency component is zero. Consequently, the inverter input current only contains the dc (average) I = I_dc, which comes from the dc supply, and the high-frequency component ∆i(t) [15], which is bypassed through the dc-link capacitor. Thus, the instantaneous input current can be expressed as:

$$i(t)=I_{dc}+\Delta i(t).$$

(3)

Neglecting the inverter’s losses and assuming that the inverter is ideal, the input current averaged over the switching period T_sw can be obtained on the basis of the input/output power balance considering Equations (1) and (2), giving:

$$I_{dc}=\frac{3}{2}m{I}_0\cos \phi .$$

(4)

An instantaneous value of the inverter input current i can be calculated as the sum of three bridge leg currents, which are dependent on the inverter switching state. Considering the switching states of each leg through the switching function S_k:

$$S_k=\{\begin{array}{l}1\to upperswitchON,lowerswitchOFF\\ 0\to upperswitchOFF,lowerswitchON\end{array},\dots k=1,2,3,$$

(5)

the input current of each inverter leg can be calculated from switching function and corresponding output current. Consequently, the total inverter input current can be expressed by adding the individual leg currents as:

$$i=S_1{i}_1+S_2{i}_2+S_3{i}_3.$$

(6)

The instantaneous sum of the phase currents according to the Kirchhoff current law (KCL) is null since a three-wire load is considered. Regarding this, there is a direct analogy between the output voltage vector and the value of the input current i(t) (Figure 2).

Finally, the switching frequency input current component can be readily obtained utilizing Equations (3), (4), and (6), as shown in Equation (7):

$$\Delta i(t)=i-I_{dc}=\left(S_1{i}_1+S_2{i}_2+S_3{i}_3\right)-\frac{3}{2}m{I}_0\cos \phi .$$

(7)

Due to the symmetry of the inverter input current, the analysis can be limited to one-sixth of the fundament period (T/6 or 60°), that is, the yellow triangle emphasized in Figure 2.

2.3. Space Vector PWM

For three-phase inverters, space vector modulation, which corresponds to carrier-based PWM with a min/max common-mode signal injection, is considered as a nearly optimal modulation for the output current THD. Therefore, in this paper, the dc-link voltage ripple analysis has been developed for SV modulation and implemented with carrier-based PWM by centering the modulating signals.

In the case of sinusoidal balanced reference voltages and by using the definition of the modulation index, the reference voltage space vector can be defined as ${\overline{V}}_0^{\ast }=mV{e}^{j\vartheta }$. There are eight possible switching combinations for a three-phase VSI corresponding to six active and two zero voltage vectors (Figure 2). The reference voltage vector is generated by synthesizing two active and two zero voltage vectors in every switching period T_sw and the volt-second balance is maintained by choosing an appropriate application time for these vectors. In the case of symmetric SV-PWM, it is enough to determine the sequence in one half of the switching period (T_sw/2) since it will be symmetrically repeated in the next half.

The application times of each voltage vector are determined as:

$$t_1=m\sqrt{3}\frac{T_{sw}}{2}\sin (\pi /3-\vartheta ),$$

(8)

$$t_2=m\sqrt{3}\frac{T_{sw}}{2}\sin \vartheta ,$$

(9)

$$t_0=\frac{T_{sw}}{2}-(t_1+t_2)=\frac{T_{sw}}{2}\left[1-\sqrt{3}m\sin (\pi /3+\vartheta )\right].$$

(10)

The application time t₀ of the null voltage vector is equally shared between the two zero switching states 000 and 111 (centered modulation). The limit of the linear modulation range is m ≤ m_max = 1/$\sqrt{3}$, where m_max is given by the generalized expression for k phases m_max = [2 cos(π/2k)]−1, as stated in [23].

3. dc-Link Voltage Ripple Evaluation

3.1. dc-Link Voltage Components

Similar to the inverter input current, the instantaneous dc-link voltage has the following components: the dc (average) component V, the low-frequency component, and the high-frequency component ∆v. The low-frequency component is zero since it is determined on the basis of the corresponding current component that is zero when the load is balanced. Correspondingly, the instantaneous dc-link voltage is expressed as:

$$v(t)=V+\Delta v(t).$$

(11)

The dc component V is simply determined by the supply voltage V_dc and the voltage drop on the dc source resistance R:

$$V=V_{dc}-R{I}_{dc}.$$

(12)

The peak-to-peak amplitude ∆v_pp of the high-frequency (switching frequency) dc-link voltage ripple component can be defined as the difference between its maximum and minimum value within the switching period:

$$\Delta v_{pp}=\max {\left\{\Delta v\left(t\right)\right\}}_{T_{sw}}-\min {\left\{\Delta v\left(t\right)\right\}}_{T_{sw}}.$$

(13)

3.2. Peak-to-Peak Voltage Ripple Evaluation

To determine Δv_pp, the input current switching frequency component, circulating through the dc-link capacitor C, has to be estimated first. Assuming that the capacitive reactance 1/ω_swC dominates the equivalent dc-link RL impedance (at the switching frequency ω_sw = 2πf_sw = 2π/T_sw), the whole current component Δi circulates through the dc-link capacitor. In this case, the corresponding dc voltage excursion can be determined by integrating Δi over the specific application time interval t_pp, determined by the space vector Equations (8)–(10). An effective simplification is obtained by considering Δi constant (ΔI) within the application time interval, leading to:

$$\Delta v_{pp}=\left|\frac{1}{C}{\displaystyle \underset{0}{\overset{t_{pp}}{\int }}\Delta i(t)dt}\right|\cong \frac{1}{C}\left|\Delta I\right|t_{pp}.$$

(14)

Due to the inverter input current periodicity i(t), the evaluation of the voltage ripple can be reduced to the phase angle range 0 ≤ $\vartheta$ ≤ 60°, that is, the first sector of the space vector diagram (Figure 2). Within the first sector, depending on the value of I_dc, two different cases can be distinguished according to Figure 3. The actual peak-to-peak dc-link voltage ripple amplitude ∆v_pp can be obtained by merging the results corresponding to these two cases.

3.2.1. Case A—Evaluation in the Range i₁ ≥ I_dc

The dc-link voltage ripple ∆v and its peak-to-peak value ∆v_pp are depicted in Figure 3, together with the instantaneous input current i(t). According to Figure 3 (left) and considering the application interval t_pp = t₀ (bold pink trace), the peak-to-peak voltage ripple can be written on the basis of Equation (14) as

$$\Delta v_{pp}^A=\frac{2}{C}\left(I_{dc}\frac{t_0}{2}\right)=\frac{1}{C}{I}_{dc}{t}_0.$$

(15)

Introducing Equations (4) and (10) into Equation (15) leads to

$$\Delta v_{pp}^A=\frac{3}{4}\frac{I_0{T}_{sw}}{C}m\cos \phi \left(1-\sqrt{3}m\sin \left(\pi /3+\vartheta \right)\right).$$

(16)

3.2.2. Case B—Evaluation in the Range i₁ < I_dc

According to Figure 3 (right) and considering the application interval t_pp = t₀/2 + t₁ (bold pink trace), the peak-to-peak voltage ripple can be written on the basis of Equation (14) as:

$$\Delta v_{pp}^B=\frac{2}{C}\left(I_{dc}\frac{t_0}{2}+(I_{dc}-i_1)t_1\right).$$

(17)

Introducing Equations (4), (8), and (10) in Equation (17) leads to

$$\Delta v_{pp}^B=\frac{3}{4}\frac{I_o{T}_{sw}}{C}m\cdot \left|\cos \phi \left(1-\sqrt{3}m\sin \left(\mathsf{\pi }/3+\vartheta \right)\right)+\frac{4}{\sqrt{3}}\sin (\pi /3-\vartheta )\left(\frac{3}{2}m\cos \phi -\cos (\vartheta -\phi )\right)\right|.$$

(18)

3.2.3. Merging Cases A and B

The actual peak-to-peak dc-link voltage ripple amplitude ∆v_pp is obtained by merging the results corresponding to cases A and B:

$$\Delta v_{pp}=\max \left\{\Delta v_{pp}^A,\Delta v_{pp}^B\right\}.$$

(19)

Finally, from Equation (19), one can see that the magnitude of the dc-link voltage ripple is always determined by the maximum value of those two.

The dc-link peak-to-peak voltage ripple amplitude can be normalized according to:

$$\Delta v_{pp}=\frac{I_o{T}_{sw}}{C}{r}_{pp}(m,\vartheta ,\phi ).$$

(20)

Applying Equation (20) to both cases A and B (Equations (16) and (18), respectively), the normalized peak-to-peak voltage ripple amplitude is given by:

$$r_{pp}=\max \left\{r_{pp}^A,r_{pp}^B\right\},$$

(21)

being

$$r_{pp}^A(m,\vartheta ,\phi )=\frac{3}{4}m\cos \phi \left(1-\sqrt{3}m\sin \left(\mathsf{\pi }/3+\vartheta \right)\right),$$

(22)

$$r_{pp}^B(m,\vartheta ,\phi )=\frac{3}{4}m\cdot \left|\cos \phi \left(1-\sqrt{3}m\sin \left(\mathsf{\pi }/3+\vartheta \right)\right)+\frac{4}{\sqrt{3}}\sin (\mathsf{\pi }/3-\vartheta )\left(\frac{3}{2}m\cos \phi -\cos (\vartheta -\phi )\right)\right|.$$

(23)

3.3. Maximum Peak-to-Peak Voltage Ripple

Figure 4 depicts the normalized peak-to-peak voltage switching ripple amplitude calculated by Equation (21) in the phase range $\vartheta$ = [0, 60°]. Four modulation indices (m = 1/4, 1/3, 1/2, and 1/$\sqrt{3}$) and two output phase angles ($\phi$= 0 and $\phi$ = 50°) have been considered. These cases will be considered also with both numerical and experimental tests in Section 5.

It is noteworthy that the normalized voltage ripple amplitude r_pp(ϑ) has a wide excursion, generally ranging between 0 and 0.25, with higher values corresponding to the higher load phase angles. The maximum of the normalized peak-to-peak voltage switching ripple amplitude (Equation (21)) is obtained as a function of the modulation index over the period $\vartheta$ = [0, 60°]. Different traces are depicted in Figure 5 considering different output phase angles.

For both output phase angles $\phi$ = 0 and $\phi$ = 90°, the maximum has been analytically determined on the basis of Equation (23) as:

$$r_{pp}^{\max }(m,\phi =0)={r_{pp}^B|}^{\max }=\frac{3}{4}m-\frac{9}{8}{m}^2,$$

(24)

$$r_{pp}^{\max }(m,\phi ={90}^{\circ })={r_{pp}^B|}^{\max }=\frac{\sqrt{3}}{4}m.$$

(25)

For other values of output phase angles ($\phi$ = 50° and $\phi$ = 30°), the maximum is obtained by properly interpolating data with a reasonable degree of approximation. The following equations are obtained:

$$r_{pp}^{\max }(m,\phi ={50}^{\circ })\cong 0.48m-0.24m^2,$$

(26)

$$r_{pp}^{\max }(m,\phi ={30}^{\circ })\cong 0.55m-0.54m^2.$$

(27)

4. Guidelines for Designing the dc-Link Capacitor

The dc-link voltage switching ripple has been investigated in previous sections. Based on the proposed calculation method of the dc-link voltage ripple envelope, simple analytical expressions for designing the dc-link capacitor can be obtained. Referring to the switching frequency in the order of kilohertz (kHz), the RL dc source impedance is much higher than the capacitive reactance. It means that only the size of the dc-link capacitor determines the amplitude of the voltage switching ripple.

To achieve a good compromise between the capacitor size and the dc-voltage ripple, the following analysis has been carried out. Two cases of output phase angles are examined. The first case ($\phi$ = 0) corresponds to most grid-connected applications (no reactive power). The second case ($\phi$ = 90°) has the highest peak-to-peak voltage ripple and, hence, it requires the biggest dc-link capacitor.

Observing Figure 5 and concerning the case $\phi$ = 0, the following simplification is made:

$$r_{pp}^{\max }\approx 0.125\to \Delta v_{pp}^{\max }=\frac{1}{8}\frac{I_0{T}_{sw}}{C}.$$

(28)

The dc-link capacitance can be easily calculated from Equation (28) as

$$C\ge \frac{1}{8f_{sw}}\frac{I_0}{\Delta v_{pp}^{\max }}.$$

(29)

In the case of $\phi$ = 90°, $r_{pp}^{\max }$ is directly proportional to the value of modulation index m. By observing Figure 5 and by considering the maximum value of modulation index (m_max = 0.577), the following simplification is introduced:

$$r_{pp}^{\max }\approx 0.25\to \Delta v_{pp}^{\max }=\frac{1}{4}\frac{I_0{T}_{sw}}{C}.$$

(30)

Based on Equation (30), the following equation for calculating the dc-link capacitor is proposed:

$$C\ge \frac{1}{4f_{sw}}\frac{I_0}{\Delta v_{pp}^{\max }}.$$

(31)

5. Numerical and Experimental Results

Numerical simulations have been carried out by MATLAB/Simulink (R2016b, MathWorks, Natick, MA, USA) and corresponding experimental tests have been performed in the laboratory by a custom-made inverter prototype.

The three-phase inverter (Figure 1) is controlled by centered PWM (corresponding to SVM) with switching frequency f_sw = 2.5 kHz. The simulation circuit parameters summarized in

Table 1. Simulation circuit and experimental setup parameters.

Label	Description	Parameters
Vdc	dc voltage supply	90 V
R	dc source resistance	5 Ω
L	dc source inductance	10.15 mH
C	dc-link capacitance	100 μF
f	Fundamental frequency	50 Hz
fsw	Switching frequency	2.5 kHz

are set in order to match the corresponding experimental setup parameters. For the experimental verification, two different output phase angles ($\phi$ = 0 and $\phi$ = 50°) have been obtained using two different loads.

Figure 6 shows the electrical circuit schematic of the experimental load. The corresponding load parameters presented in

Table 2. Load parameters.

Load	φ = 0	φ = 50°
RL	3.16 Ω	26.8 Ω
LL	20.1 mH	103 mH
Ro	20 Ω	0
Co	58 μF	0

are estimated by supplying the load by an AC power source/analyzer (50 Hz, three-phase balanced voltage source) and measuring the load currents and voltages.

The whole experimental setup is shown in Figure 7. It consists of a three-phase custom-made VSI using the Mitsubishi PS22A76 intelligent power IGBT module (1200 V, 25 A, Mitsubishi Electric Corporation, Tokyo, Japan), driven by the DSP microcontroller board via an optical interface board. DSP board (TMS320F28379D, Texas Instruments, Dallas, TX, USA) is programmed by Code Composer Studio IDE (CCS) (Texas Instruments, Dallas, TX, USA) with the possibility of real-time adjustment of the modulation parameters by a computer interface.

Simulation results are presented in Figure 8. The peak-to-peak envelopes calculated by Equation (19) as the half of peak-to-peak dc-link voltage ripple amplitude ∆v_pp/2(t) (red traces) are shown together with the instantaneous dc-link voltage switching ripple ∆v(t) (blue trace) over a fundamental period (T = 20 ms). Two values of the output phase angles $\phi$ = 0 and $\phi$ =50° are considered (left and right column, respectively) and four values of the modulation index (m = 0.25, 0.33, 0.5 and 0.577; from top to bottom) to cover the whole modulation range.

Experimental results are shown by Yokogawa DLM 2024 oscilloscope screenshots (Yokogawa Electric Corporation, Tokyo, Japan) collected in Figure 9. Two values of the output phase angles $\phi$ = 0 and $\phi$ =50° have been considered (left and right column, respectively) and four values of the modulation index—m = 0.25, 0.33, 0.5 and 0.577 (from top to bottom)—to cover the whole modulation range, as in the simulations presented in Figure 8. In all screenshots, two upper traces present the load voltage and current (green and red traces, respectively) and the bottom (blue) trace presents the measured dc-link voltage switching ripple ∆v(t). The additional two orange traces present the calculated envelopes of the voltage ripple (∆v_pp/2(t)) provided by the DSP board and displayed using DAC block with a proper voltage scaling.

The switching ripple ∆v(t) has been obtained both numerically and experimentally by properly filtering the instantaneous dc-link voltage, according to Equation (11). In the case of the experimental results, the “ac coupling” built-in function of the oscilloscope has been used together with the built-in low-pass filter in order to better clean the waveforms.

Numerically and experimentally obtained results show good matching between the theoretically calculated envelope and peak-to-peak dc-link voltage ripple for all considered cases of modulation indices and output phase angles, proving the effectiveness of the proposed approach.

6. Conclusions

The detailed calculation and comprehensive experimental investigations of the instantaneous dc-link voltage switching ripple in three-phase PWM VSIs have been carried out. Analyses refer to the case of a non-ideal dc voltage source, representing an input inductive filter or photovoltaic dc supply; however, they are also valid in the case of most dc supplies since the dc source impedance at the inverter switching frequency becomes usually much higher than the dc-link capacitor impedance.

Specifically, the peak-to-peak dc voltage ripple is analytically defined as a function of the output current amplitude, its phase angle, and the modulation index over the fundamental period. In addition, simplified equations to evaluate the maximum value of the peak-to-peak dc-link voltage ripple amplitude in the fundamental period have been derived for different output phase angles. The analysis was carried out for a balanced three-phase system, representing both motor-load and grid-connected applications well. Simple and effective expressions for the dc-link capacitor design have been proposed based on the desired maximum dc-link voltage switching ripple amplitude.

The analytical developments have been verified, both numerically and experimentally, for different values of modulation indices and two output phase angles $\phi$ = 0 (corresponding to most grid-connected inverters) and $\phi$ = 50°. For all considered cases, the correlation between analytical, simulation, and experimental results is very good, which proves the accuracy and effectiveness of the presented developments.