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Article

A Study on Improving Switching Characteristics According to a Circuit Analysis Technique in Converter Applications Using Gallium Nitride Field Effect Transistors

Department of Electrical Engineering, Changwon National University, Changwon 51140, Korea
Energies 2019, 12(17), 3280; https://doi.org/10.3390/en12173280
Submission received: 16 July 2019 / Revised: 24 August 2019 / Accepted: 24 August 2019 / Published: 26 August 2019
(This article belongs to the Section F: Electrical Engineering)

Abstract

:
In this paper, we studied how the switching characteristics of a power conversion system could be improved using gallium nitride (GaN) devices. To this end, a circuit system applying GaN field effect transistors (FETs) was modeled to derive a mathematical differential equation, and the transfer function of the system was obtained through the modeled equation to propose the analysis model. The frequency response of the system where the GaN FET device was applied was analyzed through the proposed modeling circuit, and the method to compensate for characteristics of the system was proposed. The applied method and the proposed model were validated through the comparative analysis on the frequency responses before and after the frequency response. This study’s results were proposed that the problem occurring in systems with GaN FETs could be solved through this theoretical and systematic method.

1. Introduction

The development of silicon semiconductor devices has been steadily increasing over the last few decades. In the power conversion system field, significant advancew have been made in power conversion system technology alongside the development of various structures, circuit topologies, and control technologies by the use of power switching devices. However, the limitations to the technical development of silicon semiconductors have appeared, no further technical improvements to silicon semiconductor devices are expected. More than ever, today’s power systems require high power and density. The high density has been achieved alongside the development of packaging and bonding technologies. Since some 10 years ago, gallium nitride (GaN) technology has been spotlighted as representing next-generation power semiconductor devices that can replace silicon semiconductor devices. In particular, GaN devices have many advantages, such as a wide bandgap (WBG), low on-resistance, high electron transfer speed due to their heterostructure, high on–off speed due to their high electron mobility transistor (HEMT) structures, and excellent high-temperature characteristics. Thus, GaN devices are suitable for using in high-density and high-power systems, and this can be accomplished with a much smaller size than that of a silicon semiconductor device in high-speed switching operations. Since GaN devices have a wider bandgap than other devices do, they have had an electric breakdown field 10 times stronger than that of silicon semiconductor devices, thus, they can be used even at high voltages and high temperatures. GaN devices have a heterostructure that bonds the materials of differing bandgaps. A two-dimensional (2D) channel is formed by creating a 2D electron gas (2DEG) induced by polarization, thereby isolating impurities and minimizing the scattering effect, and resulting in a high electron density and a high electron mobility [1]. Thus, the high frequency switching can be accomplished because high-speed operations are possible, and low on-resistance characteristics can be maintained, thereby enabling high-density and high-power system development, which follow the current trends of the power system development.
Further studies on power system development using WBG devices have been undertaken, and the GaN device market has grown, particularly in Asia [2]. A variety of studies on GaN devices have also been accomplished. For example, a study was conducted on quantitatively extracting the transient characteristics of GaN semiconductors, as this information was not explicitly given by suppliers, and another study analyzed GaN devices’ loss characteristics compared to those of metal-oxide-semiconductor field-effect transistors (MOSFETs) [3]. A study has also been conducted on reduction in parasitic inductance components by ensuring that the bonded wires inside field-effect transistors (FETs) are as close together as possible. Notably, the ringing phenomenon, which occurs in the transient state of GaN devices, is the result of the low turn-on threshold voltage and the small parasitic capacitance of GaN devices. A fast switching operation can be achieved due to this small parasitic capacitance, but GaN devices have a relatively large dV/dt ratio, thereby generating noise due to the parasitic capacitance and the stray inductance resonance of the FET, and the printed circuit board (PCB). Thus, Faulty turn-on may be occurred as a result, which creates a serious problem. Therefore, the study to address this issue was accomplished [4,5,6,7].
Most studies have been focused on hardware improvements for GaN devices. However, since their improvements depend on the experiences and the know-how of PCB designers, or circuit designers, they do not lead to universal technical advancements. To overcome this limitation, a study has been proposed to remove input signal noise and resonance frequency signals by applying a noise removal circuit to improve the frequency response, thereby compensating for the phase delay through software [8]. The present study derived a system as a theoretical mathematical modeling equation by which the systematic noise removal circuit could be applied and the frequency response characteristics could be analyzed. This study then presented a model through which the system’s characteristics could be analyzed theoretically rather than by applying to a general low-pass filter to blindly remove high-frequency signals, as was attempted in previous studies, and proposed the method of applying to the optimal filter to the system by analyzing its frequency response characteristics. This study also proved the validity of the proposed method through their results using the presented method.

2. Derivation of the System Characteristics

Figure 1 shows the process of designing and manufacturing a conventional power conversion system. First, the circuit design is started as shown in Figure 1, and then the system is completed through the PCB design and fabrication. As mentioned in Section 1, GaN devices have unwanted high frequency noise due to the GaN properties and the stray inductance components in the circuit. This increases switching losses, resulting in lower system efficiency.
To solve this, you can compensate by adding a filter. However, simply just applying a filter that removes high frequency noise without considering the characteristics of the system will not only achieve the desired results, but also slow down the dynamics of the system. This causes problems such as phase delay. It also causes faulty turn-on problem in other power conversion systems (especially, complementary output devices). Therefore, in order to solve these problems, we proposed a method for compensating the above problems in domestic papers. However, this method was not a perfect compensation method after all.
Therefore, as shown in Figure 2, we propose a modeling method with a theoretical and mathematical using circuit analysis technique (CAT). In addition, we propose a method to improve the characteristics of power conversion system using GaN devices by analyzing the frequency response of the system and designing the filters using the results. First, separate the converter’s topology into two circuits. To do this, the capacitors coupled to input and output are separated using Miller’s theorem, and we model it as a dependent current source to reflect the operation at the gate stage as the drain stage. After that, the voltage-current relationship was derived by using the operation mode in each circuit, and the transfer function of the system was derived. The derived transfer function obtains the frequency response using an analysis tool such as MATLAB, and uses this information to design appropriate filters and predict the results. Thus we can design optimized filters and add it to the actual circuit, effectively removing high frequency noise, reducing switching losses, and increasing system efficiency. Therefore, as compared with the conventional compensation method, it is possible to ensure quick response characteristics with little phase delay of the signals.

2.1. System Modeling

Figure 3 shows a step-down converter, the most basic power conversion topology. Here, GaNFETs are modeled as FETs with stray inductance and parasitic capacitance as highlighted in blue. The sensing and control parts are not considered in this study. The gate driver can be configured with various types of drives, such as totem-pole, bootstrap, transformer-coupled, and direct drive, as shown in Figure 3, depending on the needs and design of the circuits. However, this diversity and design freedom make up the unwanted RLC resonant circuit in the system, which may cause the unsuspected operation and noise. In Figure 3, in order to theoretically analyze the frequency response, the parasitic capacitance are separated by the Miller effect and divided into two parts to reflect the operating characteristics. A simple concept circuit for this was shown in Figure 4.
Conceptually, this is similar to conventional MOSFET small-signal equivalent circuits, but in contrast to finding AC components, this study separated the circuit into two parts, taking into account the circuit’s operating characteristics and the Miller effect. Therefore, we propose a method of analyzing both small and large signals at the same time and obtaining a transfer function for analyzing the frequency response. The GaN FET has fast electron moving speed and wide band gap, which is advantageous for high speed operation compared to existing FETs, and has the advantage of operating at high temperature without heat radiation design. However, compared to MOSFETs the switching is unstable due to relatively small parasitic capacitance components and low threshold voltages. These can be further exacerbated when high frequency noise components have frequencies near the resonance point in the system. Therefore, through the analysis and method proposed in this study, the frequency response analysis and filter design can be approached more theoretically and practically to ensure stable operation of the system.
Next, the circuit of a GaN FET system was modeled in two parts: the gate-source and the drain-source, from which a mathematical differential equation was derived, thereby deriving the transfer function. The frequency response of the system was analyzed using the derived transfer function, and the filter that removes the section where unnecessary response characteristics are displayed was designed. Then, the system’s response after the filter was applied was then analyzed.
To analyze the characteristics of the power conversion system using the GaN FET, the system of the step-down converter using a GaN FET was firstly modeled. As described in the introduction, the system is characterized by being unstable in a transient state due to their low turn-on threshold voltage and low parasitic capacitance. Considering this, the power conversion circuit was modeled and divided into gate and drain sources [9,10,11]. Figure 5 shows how the drain source circuit was modeled as a circuit device. The operation was divided by time according to the switching operation order (from Mode 0 to 3).
Here i d = ( v g s v g s ( t h ) ± Δ v g s _ r ) · g f s = k · Δ i g and g f s is forward transfer conductance, it is for reflecting to drain-source that the gate voltage resonated by the LC at the gate stage. Here, we used information about the current flowing, Δig is defined by the component due to the voltage variation of the gate stage with the transfer conductance. k is an adjustment gain constant, and is a proportional constant that adjusts to reflect the change of the voltage at the gate and drain stages. In Figure 5, because the circuit was modeled the drain-source operation, the source and the components (Vgs, Cgs, Lg and Rg) at the gate stage are short-circuited. However, the operation due to the voltage variation of the gate stage is considered in the drain-source stage by k·Δig. In Figure 6, a gate-source modeling circuit, uses Miller’s theorem to isolate Cgd capacitance while bringing it to the gate stage. Here Cds can be omitted:
d d t i d ( t ) = 1 L d v c 1 ( t ) + 1 L d v d ( t )
d d t i L s ( t ) = R d s _ o n ( L s + L d c ) i L s ( t ) 1 ( L s + L d c ) v c o ( t ) + 1 ( L s + L d c ) v c 1 ( t )
d d t v c 1 ( t ) = 1 ( C g d + C d s ) i d ( t ) 1 ( C g d + C d s ) i L s ( t )
d d t v c o ( t ) = 1 C o i L s ( t ) 1 C o R L v c o ( t )
Equations (1)–(4) present the differential equations by which voltage-current equations are derived for the modeled circuit upon being switched on. Please refer Appendix A for the mathematical development process to derive the relational and transfer function equations at the time of switching off. Appendix A will be useful for deriving the transfer function for your system by adding or removing parameters to your system that are different from those proposed in this paper. Through the above defined equation and Appendix A, the final transfer function of the drain-source stage is defined as Equation (5):
G ( s ) = b 14 det ( F ) · 1 L d = k 5 L d ( s 4 + k 1 s 3 + k 2 s 2 + k 3 s + k 4 )
Figure 6 shows the gate-source circuit represented as an equivalent circuit. Through this figure, the transfer function can be calculated via Equations (6)–(8) equivalently by the transfer function expansion process between the drain and the source, as calculated above. Please see Appendix A for further details of the mathematical process. We can derive the system transfer function of gate-source circuit as Equation (9) using Equations (6)–(8) and Appendix A:
d d t i g ( t ) = R g ( L g + L s + L d c ) i g ( t ) 1 ( L g + L s + L d c ) v g s ( t ) 1 ( L g + L s + L d c ) v o ( t ) + 1 ( L g + L s + L d c ) v g ( t )
d d t v g s ( t ) = 1 ( A v C g d + C g s ) i g ( t ) 1 ( A v C g d + C g s ) · ( r s ) v g s ( t )
d d t v o ( t ) = 1 C o i g ( t ) 1 C o R L v o ( t )
G ( s ) = m 4 s 3 + m 1 s 2 + m 2 s + m 3

2.2. System Response Characteristic

The system’s frequency response characteristics were calculated using the transfer function obtained in Section 2.1. These transfer functions are Equation (5) and Equation (9). The all factors (k1~k5 and m1~m4) in Equation (5) and Equation (9) are derived from Table 1 and Appendix A. Figure 7 shows the frequency response of the system as the Lg changes with Ld fixed. It can be seen that the resonance occurs at about 2.08 MHz by the currently designed Lg. As can be seen from the table in Figure 7, the smaller Lg was, the larger the resonant frequency was, and the larger Lg was, the smaller the resonant frequency was. The maximum gain on the system is the largest at 78.6 dB at about 658 kHz. Afterwards, whether Lg is large or small, the maximum gain is reduced. Because parasitic capacitance is not controllable, it is not considered. Capacitance can be added externally, but, since this has the effect of increasing the capacitance component, the resonance frequency band is substantially lowered to the left of the graph. This results in a state where the switching becomes extremely unstable.
Figure 8 shows the frequency response characteristics of the system as the Ld changes with Lg fixed. In the present state, Ld causes resonance at about 105 MHz, but the gain is –84.2 dB, which does not affect the system significantly. In particular, since it is a far away from the switching frequency band, it means that the state of Ld does not need to be considered much. However, if the Ld value becomes larger according to the design, the resonant frequency band of the drain-source stage is also lowered.
We can confirm this again in Figure 7 and Figure 8. The PCB design causes resonance due to the stray inductance component of the gate and drain stages. The smaller the stray inductance was, the more stable the system becomes. ΔFr_Lg and ΔFr_Ld in Figure 7 and Figure 8 represent the range of variation of the resonant frequency that can vary depending on the PCB design. Therefore, based on this result, we can also choose the method of reducing inductance, referring to Appendix B. If this is not possible, there is a need for a way to attenuate the gain of a particular frequency band. In this paper, the band-stop filter (BSF) and low-pass filter (LPF) are used to improve the response characteristics of the system (please note that this study does not intend to discuss the characteristics of the filter, but to show that it is possible to improve the characteristics of a power conversion device utilizing GaN devices by applying the filter).
The square wave pulse width modulation (PWM) signal contains the high-frequency component. Both ideal PWM signals and PWM signals that contain noise include the high-frequency component, which will contain the signals in the frequency, the gains of which increase suddenly around the resonance point in the system. This causes system instability or large signal fluctuation upon switching. Consequently, it is necessary to lower or limit the response to this frequency component. Thus, the system’s response characteristics can be improved by combining a band-stop filter and a low-pass filter that removed the specific frequency component.

2.3. Filter Design and Response Results

The frequency response analysis results have been demonstrated that the center frequency of the resonance point was approximately 2.08 MHz. The most profound effect on switching performance is exhibited by the gate-source inductance. There are two sources for parasitic source inductance in a typical circuit, one is the bond wire neatly integrated into the FET package and another is the printed circuit board wiring inductance. Furthermore, the inductor and the parasitic capacitor form a resonant RLC circuit as we know. The resonant circuit is excited by the steep edges of the gate drive voltage waveform and it is the fundamental reason for the oscillatory spikes observed in most gate drive circuits. This resonance can be damped by series resistive components of the loop, which include the driver output impedance, the external gate resistor, and the internal gate resistor, but a reduction of the overall gain is inevitable, so effectively, to remove the resonance frequency and high-frequency signals, a band-stop filter and a low-pass filter were designed. The frequency responses are shown in Figure 9. This figure shows the filter and system’s frequency response curve, in which the band-stop, low-pass filters and converter system, respectively.
In Figure 10, the gain of the BSF is set to −55 dB to attenuate 52.1 dB at the 2.08 MHz frequency, and the attenuating frequency band is defined as Fcp. Fcp band is 1.5–2.8 MHz, about 1.3 MHz. Fcp can be changed and adjusted according to the filter’s corner frequency, number of poles and the type of filter. The results has been showed that the gain was raised suddenly at approximately 2.08 MHz in Figure 9 was attenuated to under 0 dB by the band-stop filter, as verified in Figure 10.
After the system’s cut-off frequency, it was reached the response was rolled off to –20 dB/decade and then attenuated to a –120 dB/decade slope around the resonance point. Thus, an optimized filter was designed and applied to the system using the frequency response analyzed through the system modeling to improve the system’s response characteristics [12]. The switching characteristics can be improved by reducing the switching loss of the FET.
Figure 11 shows the circuit of the designed filter and power conversion part. It is the circuit that was an active second-order band-stop filter for preventing a 2.08 MHz frequency signal, and then a low-pass filter for attenuating a response of higher frequency signal. The filter circuit may be located before and after the gate. However, based on the experimental results, it is better that it be located in front of the gate driver in terms of energy efficiency and effect (however, this is an experimental result and was not accurately analyzed).

3. Experiments and Results

Experiments were conducted using the GaN FET converter module to verify the proposed method that improved the system’s switching characteristics. Using a TI GaN FET (LMG5200), the DC-DC converter module was self-made, and for the controller, a TMS320F28335 module was used. The filter manufactured by us was applied and interfaced. In this experiment, most parameters were chosen by referring to the data sheet provided by TI, and the value of the PCB stray inductance was estimated and applied through measurements.

3.1. Stray Inductance Measurement

The stray inductance in the PCB was divided into resistance and inductance components in the path between two points, as shown in Figure 12, calculated, and estimated based on the voltage value between the two points by injecting a current that changed according a constant time. Figure 13 shows a picture of a real test step-down converter using a GaN FET. The path of stray inductance that can occur on the PCB is shown. The filter circuit was added to the bottom of the board. Refer to the table attached in Figure 13 for wiring information.

3.2. Test and Analysis

Table 1 presents the parameters chosen for the model analysis through applying the TI data sheet information and measured values. The experiment’s results were verified through their applications to an approximately 200 W converter system, which represented around 50% of the rated capacity.
Figure 14a shows the voltage and current measurement results at both switching ends in the GaN FET converter system. Figure 14b shows the expanded figure of the voltage and the current at both switch ends upon turn-off. As you can be seen in Figure 14, because the voltage is ringing by resonance, so current is also ringing.
Figure 15 shows the PWM waveform when the proposed filter is applied to the noise-containing PWM driving signals. A filter analyzed through system modeling was applied for improving the frequency response characteristic. And the results were verified that most frequency components that affected the system had been removed.
Figure 16a shows the voltage and current switching waveforms in the GaN FET conversion system due to the noise-containing PWM signals. Figure 16b shows how the voltage and current switching waveforms in the GaN FET conversion system looked after the filtered signals are applied. The results has been indicated that the ringing waveform’s size and the time upon on–off switching were significantly reduced.
Consistent with the findings of previous studies, when a low-pass filter was applied without the system characteristics being identified, not only was high-frequency noise removed but needed signals were also attenuated, resulting in a significant phase delay. However, if unnecessary signals were removed through the application of the optimal filter after the system’s frequency response was identified through the proposed system modeling analysis, both signal attenuation and phase delay were reduced significantly.
Figure 17 shows an expanded view of the switching time to see how switching losses happened. In Figure 17a, the voltage does not drop to zero at the time of switching turn-on, but rings due to resonance. These eventually result in switching losses. In addition, as shown in Figure 17b, voltage and current were ringing during turn-off. As mentioned in the paper, these are the results of a combination of GaN’s low threshold voltage and LC resonance. Figure 17c,d show that the switching properties were improved when the method proposed in this paper was applied, but there is a slight delay, and small ripples still exist. This is analyzed as a slight phase delay caused by the filter, although it has much less delay and ripple than conventional methods.
By improving the characteristics of this switching, the switching losses are different before and after method is applied as analyzed in Figure 18. Switching is repeated every 5 μs, with increasing loss. Other sections increase little by little with the gradient of conduction losses. In particular, at turn-on time, a large amount of losses occur due to a large ringing voltage when the current is conducted. On the other hand, at turn-off time, the current does not have much ringing in the zero section, so this loss is analyzed to be less than the loss at turn-on. Figure 18 shows the graph of the switching loss calculated using the above two methods. As shown, the method in which the optimized filter was applied was proposed by this study, the switching loss due to ringing was considerably attenuated, as shown by the dotted circles. It can be seen that the proposed method improves the switching loss by about 36.7% compared with the conventional method. Therefore, we proved the validity of the proposed method which improves switching characteristics.
In Figure 19, we have compared simulations and the measured results. Figure 19c,d show simulation results of the spectrum of the signal before and after applying the method proposed in this paper and Figure 19a,b show the measured results. It can be seen that the derived experimental results are similar to the analysis results, but, while the resonance frequency was analyzed as 2.08 MH in the actual experiment, it could be seen that resonance occurs at about 2.5 MHz due to some parameter measurement error. However, because it exists in the attenuation band (1.5–2.8 MHz), it can be seen that the resonance frequency element was attenuated as the experimental result.

4. Discussion and Conclusions

This study modeled a system and induced a mathematical relationship equation for verifying the frequency response characteristics involved in solving major problems in GaN FET power conversion systems. Through the verification of the frequency response characteristics, a filter-applied method was presented to limit frequency responses in a specific range and to improve response characteristics in a high-frequency range. This study has been contributed to facilitating the analysis of system characteristics through theoretical models, through which systems’ characteristics could be analyzed by applying them to various power conversion systems using GaN devices. This study proved that the ringing and faulty turn-on problems in GaN FETs could be solved by designing and adding a filter through the theoretical response characteristics of the system. As a result, switching loss was reduced by about 36.7%, peak voltage by about 37.2%, and current ripple by 49.6% when the proposed method was applied to the existing system.
In the author’s previous paper, q method that compensated for the phase delay problem occurring when a filter was applied was proposed, which was verified through simulations and experiments. The results of our studies are expected to be widely used in GaN systems in the future, as GaN FET power conversion systems may run in higher frequency ranges, and their undesirable characteristics can be compensated for by software. If the function that can control filter characteristics is added to gate drivers in the future, GaN device applications are expected to advance technologically.

Funding

This research received no external funding.

Conflicts of Interest

The authors declare no conflict of interest.

Appendix A

This appendix shows the process of deriving the transfer function of the system through a mathematical process according to the modeling equations of Equations (A1)–(A4):
d d t i d ( t ) = 1 L d v c 1 ( t )
d d t i L s ( t ) = R d s _ o n ( L s + L d c ) i L s ( t ) 1 ( L s + L d c ) v c o ( t ) + 1 ( L s + L d c ) v c 1 ( t )
d d t v c 1 ( t ) = 1 ( C g d + C d s ) i d ( t ) 1 ( C g d + C d s ) i L s ( t )
d d t v c 2 ( t ) = 1 C o i L s ( t ) 1 C o R L v c o ( t )
Equations (A1)–(A4) present the differential equations by which voltage-current equations are derived for the modeled circuit upon being switched off. As presented in Equation (A5), variables are substituted to calculate a transfer function after the variables expressed with each of the differential equations are designated as state variables:
𝕩 = [ i d ( t ) i L s ( t ) v c 1 ( t ) v c o ( t ) ] =   [ x 1 x 2 x 3 x 4 ]      𝕩 ˙ = [ i d ( t ) ˙ i L s ( t ) ˙ v c 1 ( t ) ˙ v c o ( t ) ˙ ] =   [ x 1 ˙ x 2 ˙ x 3 ˙ x 4 ˙ ]
The on and off transfer functions are expressed considering the system operation to calculate the transfer functions, which are divided into Equations (A6) and (A7):
𝕩 ˙ o n =   A o n X + B o n U
𝕩 ˙ o f f =   A o f f X + B o f f U
Since the on–off duty is defined as presented in Equation (A8), a transfer function for a single cycle can be expressed as Equation (A9):
D o n + D o f f = 1
𝕩 ˙ ( o n + o f f ) =   ( D o n A o n + D o f f A o f f ) X + ( D o n B o n + D o f f B o f f ) U
A o n = A o f f = [ 0 0 1 / ( C g d + C d s ) 0 0    ( R d s _ o n ) / ( L s + L d c )    1 / ( C g d + C d s ) 1 / C o 1 / L d 1 / ( L s + L d c ) 0 0 0     1 / ( L s + L d c ) 0 1 / C o R L ]
B o n = [ 1 / L d 0 0 0 ] ,   B o f f = [ 0 0 0 0 ]
Here, since the vector that represents the state variable parameter satisfies Aon = Aoff and the output voltage is a voltage applied to the output capacitor C2, it can be expressed in Equation (A12):
v o = v c o ( t ) = x 4 = [ 0   0   0   1 ] X
By arranging the above equation, the input and output transfer function equations of the system can be expressed as Equations (A13) and (A14):
𝕩 ˙ =   A X + D o n B o n U  
Y ˙ =   X + D U = [ 0   0   0   1 ] X
By substituting the parameter values that are not zero for all variables and arranging the equations, the state equations can be expressed in Equations (A15) and (A16):
[ x 1 ˙ x 2 ˙ x 3 ˙ x 4 ˙ ] = [ 0 0 a 31     0 0 a 22 a 32     a 42 a 13 a 23 0 0 0 a 24 0 a 44 ] [ x 1 x 2 x 3 x 4 ] + [ D b 1 0 0 0 ] v d
y = [ 0   0   0   1 ] [ x 1 x 2 x 3 x 4 ]
The transfer function in the above state equations can be expressed as Equation (A17) and the Laplace inverse matrix of the transfer function is defined in Equation (A18). Then, the 4 × 4 determinant of (sIA) can be calculated via Equation (A19):
G ( s ) = Y ( s ) U ( s ) = ( s I A ) 1 B = [ 0   0   0   1 ] [ s 0 a 13 0 0 s a 22 a 23 a 24 a 31 a 32 s 0 0 a 42 0 s a 44 ] 1 [ 1 / L d 0 0 0 ]
( s I A ) 1 = 1 det ( s I A )   A d j ( s I A )
det ( s I A ) = s {   ( s a 22 ) | s 0 0 s a 44 | ( a 23 ) | a 32 0 a 42 s a 44 | + ( a 24 ) | a 32 s a 42 0 |   }   a 12 {   ( a 21 ) | s 0 0 s a 44 | ( a 23 ) | a 31 0 0 s a 44 | + ( a 24 ) | a 31 s 0 0 |   } + ( a 13 ) {   ( a 21 ) | a 32 0 a 42 s a 44 | ( s a 22 ) | a 31 0 0 s a 44 | + ( a 24 ) | a 31 a 32 0 a 42 |   } ( a 14 ) {   ( a 21 ) | a 32 s a 42 0 | ( s a 22 ) | a 31 s 0 0 | + ( a 23 ) | a 31 a 32 0 a 42 |   }
Equation (A19) can be expressed by the Laplace function, as presented in Equation (A20), through determinant expansion, and the coefficients of each order are defined in Equations (A21)–(A24). By those equations, the determinant, which is a denominator of the transfer function, can be calculated:
det ( s I A ) = s 4 + k 1 s 3 + k 2 s 2 + k 3 s + k 4
k 1 = ( R d s _ o n ) / ( L s + L d c ) +   1 / C o R L
k 2 = ( R d s o n ) / ( ( L s + L d c ) · C o R L 1 / ( L s + L d c ) 2 1 / ( ( L s + L d c ) · C o ) + 1 / ( L d ( C g d + C d s )
k 3 =   1 / ( ( L s + L d c ) · C o R L 1 / ( L d ( C g d + C d s ) { ( R d s _ o n ) / ( L s + L d c ) 1 / C o R L }  
k 4 =   1 / ( L d ( C g d + C d s ) ) · ( R d s _ o n ) / ( ( L s + L d c ) · C o R L )   1 / ( L d C o · ( L s + L d c ) ( C g d + C d s ) )
To calculate the adjoint matrix, which is a numerator of the transfer function, it is expressed in vector F, as presented in Equation (A25), thereby calculating the cofactor of the matrix and the transposed matrix to calculate the adjoint of the matrix through Equations (A26) and (A27). Accordingly, Equation (A18) can be defined as Equation (A28):
( s I A ) = F = [ f 11      f 12     f 13     f 14 f 21      f 22     f 23     f 24 f 31      f 32     f 33     f 34 f 41      f 42     f 43     f 44 ]
F   c o f a c t o r =   B =   [ b 11      b 12     b 13     b 14 b 21      b 22     b 23     b 24 b 31      b 32     b 33     b 34 b 41      b 42     b 43     b 44 ]
B T =   [ b 11      b 21     b 31     b 41 b 12      b 22     b 32     b 42 b 13      b 23     b 33     b 43 b 14      b 24     b 343     b 44 ]
( s I A ) 1 = F 1 = 1 det ( F ) B T = [ b 11 det ( F )      b 21 det ( F )     b 31 det ( F )     b 41 det ( F ) b 12 det ( F )      b 22 det ( F )     b 32 det ( F )     b 42 det ( F ) b 13 det ( F )      b 23 det ( F )     b 33 det ( F )     b 43 det ( F ) b 14 det ( F )      b 24 det ( F )     b 34 det ( F )     b 44 det ( F ) ]
Equation (A28) is substituted into Equation (A17), which is the transfer function equation, and calculated with matrices C and B, thereby obtaining the equation of the transfer function, as presented in Equation (A29):
( s I A ) 1 B = [ 0   0   0   1 ] [ b 11 det ( F )      b 21 det ( F )     b 31 det ( F )     b 41 det ( F ) b 12 det ( F )      b 22 det ( F )     b 32 det ( F )     b 42 det ( F ) b 13 det ( F )      b 23 det ( F )     b 33 det ( F )     b 43 det ( F ) b 14 det ( F )      b 24 det ( F )     b 34 det ( F )     b 44 det ( F ) ] [ 1 / L d 0 0 0 ] = b 14 det ( F ) · 1 L d
Here, b14, the cofactor coefficient of the transfer function, can be calculated through the determinant, as presented in Equation (A30):
b 14 = d e t | f 21    f 22    f 23 f 31    f 32    f 33 f 41    f 42    f 43 | = f 21 | f 32 f 33 f 42 f 43 | f 22 | f 31 f 33 f 41 f 43 | + f 23 | f 31 f 32 f 41 f 42 | = f 23 · f 31 · f 42
Here, as f21 = 0, f43 = 0, f41 = 0, and the cofactor function coefficients are defined as presented in Equation (A31). Their values can be calculated as Equation (A32):
| f 21 f 22 f 23 f 31 f 32 f 33 f 41 f 42 f 43 | = | 0 s a 22 a 23 a 31 a 32 s 0 a 42 0 |
f 23 · f 31 · f 42 = ( a 23 ) · ( a 31 ) · ( a 42 ) = 1 ( L s + L d c ) · 1 ( C g d + C d s ) · 1 C o = k 5
Through the above defined equation, the final transfer function of the system is defined as Equation (A33):
G ( s ) = b 14 det ( F ) · 1 L d = k 5 L d ( s 4 + k 1 s 3 + k 2 s 2 + k 3 s + k 4 )
𝕩 = [ i g ( t ) v g s ( t ) v o ( t ) ] =   [ x 5 x 6 x 7 ]       𝕩 ˙ = [ i g ˙ ( t ) v g s ˙ ( t ) v o ˙ ( t ) ] =   [ x 5 ˙ x 6 ˙ x 7 ˙ ]
𝕩 ˙ =   A X + D o n B o n U  
y =   X = [ 0   1   0 ] X   
[ x 5 ˙ x 6 ˙ x 7 ˙ ] = [ a 55 a 56 a 57 a 65 a 66 0 a 75 0 a 77 ] [ x 5 x 6 x 7 ] + [ b 51 0 0 ] v g
det ( s I A ) = s 3 + m 1 s 2 + m 2 s + m 3
m 1 = ( R g / ( L g + L s + L d c ) + ( 1 / ( A v C g d + C g s ) ( r s ) ) ) +   ( 1 / C o R L )
m 2 = 1 / ( L g + L s + L d c ) · C o R L ) +   ( R g / ( L g + L s + L d c ) ) ( 1 / ( A v C g d + C g s ) · r s ) + ( R g / ( L g + L s + L d c ) ) / C o R L + ( 1 / ( L g + L s + L d c ) ) / ( A v C g d + C g s ) +   ( 1 / ( L g + L s + L d c ) · C o )
m 3 = ( 1 / ( L g + L s + L d c ) ) / ( A v C g d + C g s ) · C o R L + ( 1 / ( L g + L s + L d c ) ) ( 1 / ( A v C g d + C g s ) ( r s ) / C o + ( R g / ( L g + L s + L d c ) ) ( 1 / ( A v C g d + C g s ) / ( r s · C o R L )
m 4 = 1 ( A v C g d + C g s ) · 1 C o R L · 1 ( L g + L s + L d c )
G ( s ) = ( s I A ) 1 B = [ 0   1   0 ] [ b 11 det ( F )     b 21 det ( F )     b 31 det ( F )   b 12 det ( F )      b 22 det ( F )     b 32 det ( F ) b 13 det ( F )      b 23 det ( F )     b 33 det ( F ) ] [ 1 / ( L g + L s + L d c ) 0 0 0 ] = b 12 det ( F ) 1 ( L g + L s + L d c )   = m 4 s 3 + m 1 s 2 + m 2 s + m 3

Appendix B

PCB wiring is plate inductance. Therefore, the inductance can be adjusted using the following equation:
L = μ 0 2 ( ln 2 t + w + 0.5 )   ( t : thickness , w : width , 𝓁 : length )

References

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Figure 1. The traditional WBG device system design and compensation flow.
Figure 1. The traditional WBG device system design and compensation flow.
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Figure 2. The proposed WBG device system design and compensation flow in this paper.
Figure 2. The proposed WBG device system design and compensation flow in this paper.
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Figure 3. The step-down power conversion system structure with GaN FET, internal parameters and stray components.
Figure 3. The step-down power conversion system structure with GaN FET, internal parameters and stray components.
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Figure 4. The concept of circuit separation to divide into two parts.
Figure 4. The concept of circuit separation to divide into two parts.
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Figure 5. Modeling the drain-source circuit in the GaN FET system: (a) Free-wheeling, powering and resonant mode at transient state at turn on; (b) Powering mode at turn on; (c) Resonant mode at transient state at turn off; (d) Free-wheeling mode at turn off.
Figure 5. Modeling the drain-source circuit in the GaN FET system: (a) Free-wheeling, powering and resonant mode at transient state at turn on; (b) Powering mode at turn on; (c) Resonant mode at transient state at turn off; (d) Free-wheeling mode at turn off.
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Figure 6. Modeling the gate-source circuit in the GaN FET system.
Figure 6. Modeling the gate-source circuit in the GaN FET system.
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Figure 7. The system frequency response with variation of gate-inductance (Lg).
Figure 7. The system frequency response with variation of gate-inductance (Lg).
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Figure 8. The system frequency response with variation of drain-inductance (Ld).
Figure 8. The system frequency response with variation of drain-inductance (Ld).
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Figure 9. The frequency response of the band-stop, low-pass filters and converter system.
Figure 9. The frequency response of the band-stop, low-pass filters and converter system.
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Figure 10. The comparison of the frequency response between the original converter system and the compensated system.
Figure 10. The comparison of the frequency response between the original converter system and the compensated system.
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Figure 11. The proposed filter circuit and the power conversion topology with GaN FET. (Second order band-stop and low-pass filters).
Figure 11. The proposed filter circuit and the power conversion topology with GaN FET. (Second order band-stop and low-pass filters).
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Figure 12. The measurement method for the PCB stray inductance.
Figure 12. The measurement method for the PCB stray inductance.
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Figure 13. The stray inductance path in the self-manufactured PCB.
Figure 13. The stray inductance path in the self-manufactured PCB.
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Figure 14. The drain-source voltage and current signals at the time of switching. (a) 1 cycle turn on-off waveform; (b) A zoomed view.
Figure 14. The drain-source voltage and current signals at the time of switching. (a) 1 cycle turn on-off waveform; (b) A zoomed view.
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Figure 15. The gate-source voltage signals (original and filtered).
Figure 15. The gate-source voltage signals (original and filtered).
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Figure 16. The switching waves of drain-source voltage and current in system. (a) The voltage and current switching waveforms before method applied; (b) The voltage and current switching waveforms after method applied.
Figure 16. The switching waves of drain-source voltage and current in system. (a) The voltage and current switching waveforms before method applied; (b) The voltage and current switching waveforms after method applied.
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Figure 17. The comparison of switching waveform before and after applying the proposed method. (a) The voltage and current switching waveforms at turn-on before method applied; (b) The voltage and current switching waveforms at turn-off before method applied; (c) The voltage and current switching waveforms at turn-on after method applied; (d) The voltage and current switching waveforms at turn-off after method applied.
Figure 17. The comparison of switching waveform before and after applying the proposed method. (a) The voltage and current switching waveforms at turn-on before method applied; (b) The voltage and current switching waveforms at turn-off before method applied; (c) The voltage and current switching waveforms at turn-on after method applied; (d) The voltage and current switching waveforms at turn-off after method applied.
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Figure 18. The comparison of switching losses before and after applying the proposed method.
Figure 18. The comparison of switching losses before and after applying the proposed method.
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Figure 19. The comparison of signal spectrum before and after applying the proposed method. (a) System response spectrum measurement results before method applied; (b) System response spectrum measurement results after method applied; (c) System response spectrum simulation results before method applied; (d) System response spectrum simulation results after method applied.
Figure 19. The comparison of signal spectrum before and after applying the proposed method. (a) System response spectrum measurement results before method applied; (b) System response spectrum measurement results after method applied; (c) System response spectrum simulation results before method applied; (d) System response spectrum simulation results after method applied.
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Table 1. The parameters of the dc-dc converter system.
Table 1. The parameters of the dc-dc converter system.
ParameterValueParameterValue
v i n 24 V v o u t 12 V
i i n 7.5 A i o u t 15 A
C g d 0.44 nFk10
C g s 9.36 nF r s 1 mΩ
C d s 0.01 nF r g 0.7 Ω
L g 0.2 uH R L 1.6 Ω
L s 0.5 nH R d s _ o n 16 mΩ
L d 0.2 nH A v 4.8
L d c 400 uH C o 1 uF

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Kim, T.-K. A Study on Improving Switching Characteristics According to a Circuit Analysis Technique in Converter Applications Using Gallium Nitride Field Effect Transistors. Energies 2019, 12, 3280. https://doi.org/10.3390/en12173280

AMA Style

Kim T-K. A Study on Improving Switching Characteristics According to a Circuit Analysis Technique in Converter Applications Using Gallium Nitride Field Effect Transistors. Energies. 2019; 12(17):3280. https://doi.org/10.3390/en12173280

Chicago/Turabian Style

Kim, Tae-Kue. 2019. "A Study on Improving Switching Characteristics According to a Circuit Analysis Technique in Converter Applications Using Gallium Nitride Field Effect Transistors" Energies 12, no. 17: 3280. https://doi.org/10.3390/en12173280

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