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Article

Direct Form Digital Robust RST Control Based on Chebyshev Sphere Optimization Applied in a DC-DC Power Converter

by
Cleonor C. das Neves
1,*,
Walter B. Junior
1,*,
Renan L. P. de Medeiros
2,*,
Florindo A. C. Ayres Junior
2,*,
Iury V. Bessa
2,*,
Isaías V. Bessa
2,*,
Gabriela de M. Veroneze
2,*,
Luiz E. S. e Silva
2,* and
Nei J. S. Farias
2,*
1
Institute of Technology, Faculty of Electrical Engineering, Federal University of Pará—UFPA, Pará, Belém City 66075-110, Brazil
2
Faculty of Technology, Department of Electricity, Federal University of Amazonas—UFAM, Manaus City 69067-005, Amazonas, Brazil
*
Authors to whom correspondence should be addressed.
Energies 2020, 13(15), 3810; https://doi.org/10.3390/en13153810
Submission received: 31 May 2020 / Revised: 10 July 2020 / Accepted: 21 July 2020 / Published: 24 July 2020

Abstract

:
This paper presents a novel direct form to design a digital robust control using RST structure (i.e., name given because of the R, S and T polynomials computed) based on convex optimization such as Chebyshev sphere; this approach was applied to a DC-DC Buck converter. This methodology takes into account parametric uncertainties and a Chebyshev sphere constraint in order to ensure robust performance and stability of the system in the discrete domain. For this purpose, a mathematical model for the DC-DC Buck converter is presented when considering uncertainties in electrical variables, such as load resistance, inductance, capacitance, and source voltage variation, also to obtain the discrete model of the system by using the bilinear transformation. The proposed methodology is compared with two other approaches designed in a discrete domain: the classical pole placement and the robust methodology based on the Kharitonov theorem. Wide-ranging experiments are performed in order to evaluate the behavior of the control methodologies when the system is subject to parametric variations of the load resistance and voltage setpoint variation. The results show that the proposed methodology outperforms the other approaches in 90% of the tests and ensures robust stability and robust performance when the system is subjected to a parametric uncertainties family.

1. Introduction

Nowadays, power converters application is attracting attention in academy due to the global energy demand growth and the search for new types of renewable energy. In a classical distribution system, the consumers are passive loads; however, due to technological improvement and advances in power electronics and power generation, by using renewable sources, these consumers can generate their own energy. They might operate connected on-grid or islanded, so a set of renewable sources and loads that are possible to operate islanded are called microgrids. The DC form is the most common type of power generation by renewable sources, DC systems are focused on several investigations. Thus, the investigation of the DC-DC power converters applications has a wide area of studies and functions, such as photovoltaic systems [1], energy management, microgrids [2,3,4,5], electric vehicles, and others applications.
Meanwhile, many studies focused on stability and performance improvement, so several control strategies applied on DC-DC power converter were studied, such as: robust control [4,5,6,7,8,9]; sliding mode control [10,11]; adaptive control [12]; model predictive control [13]; fault-tolerant control [14,15]; classical pole-zero cancellation [16]; designing the controller in frequency domain [17]; the fractional-order PID controllers [18,19]; and lastly, based on the GPI Observer [20].
In [4,5], robust control methodologies were applied on the cascade DC-DC buck converter, to assess the oscillations in the feeder converter caused by the power variation of the constant power load (CPL). Additionally, the control design based on Kharitonov’s theorem considered the linear parameter varying (LPV) model of the DC-DC converter taking into account an uncertainty family in the type of hyper box; the control strategy was designed in indirect form, in other words, it was designed in s-domain, in sequence the Tustin conversion was used to digital implementation of the controller.
In [6], the sampled data output feedback control applied to the DC-DC buck converter was investigated. In sequence, a reduced-order observer and a robust output feedback controller were designed to ensure the robustness and stability of the system. In [7], a regulation of DC-DC boost converter considering an uncertain family was investigated. The LPV model was developed when considering uncertainties, such as load variation, non-modeled dynamics, and input voltage variation. Subsequently, the proposed methodology merges the cascade controllers and nested in a reduced-order PI observers design, in order to maintain the desirable voltage regulation performance.
Two control methodologies were presented in [8] for mismatched DC-DC buck converters: the first method used a multiple surface sliding mode control to handle mismatched load uncertainty and the other method is based on simultaneous state and disturbance and observer. In addition, the sensorless structures combined with the second-order sliding mode control is a common strategy developed in several reported works [21,22].
In [18], a fractional sliding mode control (FRSMC) applied in a practical buck converter system based on PI and PID structures was investigated; besides that, the voltage setpoint variation was performed. In [19], the effectiveness of the fractional order PID (FOPID) controller applied in a DC-DC buck converter feeding a DC motor was investigated, aiming to compare the performance and robustness with the classical control approaches.
A cascade control structure with internal sliding mode control was applied to the multiphase synchronous DC-DC converter [10]. In the outer voltage loop, a feedforward compensation was designed. Furthermore, disturbance observers in both the inner and outer loop were used in order to compensate the difference between the model and rigged system developed.
According to Chan et al. [11], adaptive current-mode control for DC-DC boost converter is given; therefore, the adaptive law is formed combining the existing current-mode control law with adaptive law that generates the inverse of the load resistance. In [12], a predictive control that is based on both digital average voltage and current (DAV/DAC) for switching the DC-DC converter is proposed, aiming to ensure the stability of the system, besides enabling the system exhibit high output voltage accuracy and overcurrent protection.
A re-configurable structure of the resonant control applied on the DC-DC converter was investigated [13]. Besides that, it was used as a soft-switching technique to acquire high performance. Thus, another resonant element was introduced into the LLC converter. In [14], an analysis of fault-tolerant operation capabilities of an isolated bidirectional full-bridge current source DC-DC converter was investigated. This study regarded the system reconfiguration in another simplified structure.
DC microgrids have been widely used for critical applications, several studies in control use them to enhance the performance and stability of these systems investigated in recent years. In [17], a novel decentralized output constrained control algorithm to ensure the high performance of the single bus DC microgrid is presented; in addition, the goals of this control technique are: high performance of the voltage control of the DC bus, user-defined the load sharing, and minimize the circulating current. Meanwhile, in [23] a unified distributed control strategy applied in a stand alone DC microgrid was proposed. This control strategy integrates three types of control solution for DC microgrid, such as: power control, voltage control, and droop control. Thus, to design the controller first formulate a solution of the optimal power flow to stand-alone DC microgrid, in sequence the dynamic solving algorithm based on primal-dual decomposition method is proposed, the convergence and optimal conditions of its equilibrium point were proved. Six DC microgrid systems based on the DC microgrid benchmark are used to evaluate the effectiveness of the proposed methodology.
In [24], a novel control structure applied in a hybrid DC/AC microgrid is investigated. This technique integrates concepts of the Lyapunov theory and input-output feedback linearization (IOFL) to design the controller and apply in a specific microgrid that take into account several energy sources, i.e. wind genearation, photovoltaic generation, besides that they use a storage device composed by lithium battery and buck-boot converter, each energy source and device has a control subsystem that is designed by using the proposed technique to ensure the stability of the system. Several simulation tests were performed in order to evaluate the effectiveness of the proposed technique.
A recent literature review presents a lack of contribution in the direct form to design digital controllers as well as perform the experimental investigations of the robust control methodologies applied in the DC-DC converters or in DC microgrids. Therefore, this article proposes a direct form to design the digital RST robust control (i.e., name given because of the R, S, and T polynomials computed) when considering the set of parametric interval uncertainties, i.e., the family of uncertainties is a hyper box representation to work with the LPV model of the DC-DC buck converter. This control methodology is applied on a DC-DC buck converter while taking a parametric variation, such as load resistance variation and voltage reference setpoint variation into account; furthermore, the proposed methodology uses the Chebyshev sphere theorem as constraints of the optimization problem to compute the robust controller gains aiming to guarantee the performance and stability of the system. The proposed digital RST robust controller is designed to provide robust performance and robust stability when the system is subject to an uncertain family. Summarizing, this study proposes the following main contributions:
  • a new direct form to design the digital robust control by using convex optimization based on the Chebyshev sphere circumscribed in the Kharitonov’s rectangle, with the purpose to relax the space of solutions and ensure the robust performance and robust stability; and,
  • simulations and experiments were performed to demonstrate the effectiveness of the proposed methodology. The results showed that the proposed approach outperforms a classical control approach as well as the robust control based on Kharitonov’s rectangle.
The remaining of this paper is organized, as follows: Section 2 describes the mathematical model of the DC-DC buck converter as well as the operating conditions; Section 3 discuss the digital robust control based on convex optimization constrained to a Chebyshev sphere design as well as presents a robust control methodology based on Kharitonov rectangle; Section 4 performs the proposed methodology, shows the board system developed, besides that presents a brief description of the tests performed; Section 5 discusses results performed by the performed tests; and finally, Section 6 concludes this study.

2. Mathematical Model of DC-DC Buck Power Converter

Figure 1 shows a well-known DC-DC buck converter topology, when considering a passive LC filter. This system is divided into three parts: hardware, microcontroller, and computer. The hardware part comprises all power elements (green box), the microcontroller part (blue box), and the computer part corresponds to graphical user interface (GUI) in order to have a user-friendly operation (red box).
It is necessary to consider how the power converter operation mode functions in order to obtain the converter mathematical model, so, in this paper, the continuous conduction mode (CCM) is adopted, in other words, the current that passes in the inductor element is not null during any time of the switching period [25]. Figure 2 depicts the equivalent circuit of each stage of the switching element.
Figure 3 illustrates the system’s waveform of all electrical variables, when the DC-DC buck power converter operates in CCM mode; therefore, considering that the condition above presented, the following equations can be obtained to each switch condition, i.e., switch on (Equation (1)) and off (Equation (2)), respectively.
d V C ( t ) d t = 1 C I L ( t ) 1 R C V C ( t ) d I L ( t ) d t = 1 L V C ( t ) + 1 L V s
d V c ( t ) d t = 1 C I L ( t ) 1 R C V C ( t ) d I L ( t ) d t = 1 L V C ( t )
When the switching element ( Q 1 ) is activated, the diode element ( D 1 ) is disabled; therefore, the source feed directs the resistance load and charges the capacitive and inductive elements. On the other hand, when the switching element ( Q 1 ) is not activated, the source does not feed the load; therefore, the diode element conducts and the active components (inductive and capacitive elements) discharge to supply the load. Figure 3 represents these effects during the switching period [25].
Re-writing the (1) and (2) to easy represents in matrix form the system dynamics, as follows.
V ˙ C I ˙ L o n = 1 C 1 R C 0 1 L V C I L + 0 1 L V s
V ˙ C I ˙ L o f f = 1 C 1 R C 0 1 L V C I L
Subsequently, adopting the average state-space model (ASM) that considers (3) and (4), it is possible write the following non-linear system.
V ˙ C I ˙ L = 1 C 1 R C 0 1 L V C I L + 0 d L V s V o = 1 0 V C I L + 0 V s
When considering that the input source V s is fixed, and adopting the controlled duty cycle d ( t ) as input, thus d ( t ) , I L ( t ) and V C ( t ) in (5) are decomposed into a fixed term and a time-varying term:
d ( t ) = δ d ( t ) + d o I L ( t ) = δ I L ( t ) + I L o V C ( t ) = δ V C ( t ) + V C o
where, the operation duty cycle d o is chosen by V o = d o V s , where V o is the desired output voltage. In addition, I L o = d o V s R and V C o = d o V s denote, respectively, the current in the inductor and the voltage in the capacitor. Thus, the linear state space model (SSM) around the operational point (OP) ( d o , I L o , V C o ) and its transfer function G ( s ) are presented below.
δ V ˙ C δ I ˙ L = 1 C 1 R C 0 1 L δ V C δ I L + 0 V s L δ d δ V o = 1 0 δ V C δ I L
G ( s ) = δ V o ( s ) δ d ( s ) = V s L C s 2 + 1 R C s + 1 L C .

3. Digital Robust Rst Control Design by Using Convex Optimization

An essential goal of control systems theory is to guarantee the stability and desired performance, despite the uncertainties due to parametric variations and disturbances. However, classical control design methodologies are not able to handle model uncertainties, forcing the use of local models around an operational point, which represents a nominal condition.
The uncertainties can be classified into two categories: nonstructural uncertainties (nonparametric uncertainties) and structured uncertainties (parametric uncertainties). In this study, control techniques for mathematical models considering parametric uncertainties are investigated; in addition, the extension to discrete domain the main theorems of robust control aiming to design the robust controller in a direct form by using RST structure was considered [26,27,28,29,30].
Several control design methodologies that consider a family of uncertainties uses the Kharitonov theorem to guarantee polynomial stability [26,27,28]. In view of the interval uncertainties, i.e., hyperbox, the polynomial stability can be evaluated by testing four Kharitonov’s polynomials, and when considering the following interval variation of each parameter obtained by a polynomial. Subsequently, the uncertainty region can be delimited by (10), where the superscripts + and − denote the upper and lower bound limit of each uncertainty interval, respectively.
δ ( z ) = δ 0 + δ 1 z + δ 2 z 2 + + δ n z n
Δ = [ δ 0 , δ 0 + ] × [ δ 1 , δ 1 + ] × [ δ 2 , δ 2 + ] × × [ δ n , δ n + ]
According to Bhattacharyya et al. [27], when assuming that the family of the polynomial has a constant degree, it is possible to ensure the Schur’s stability of these uncertainties, they must be computed for the Kharitonov polynomials, as following [26,27].
K 1 ( z ) = δ 0 + δ 1 z + δ 2 + z 2 + δ 3 + z 3 + K 2 ( z ) = δ 0 + δ 1 + z + δ 2 + z 2 + δ 3 z 3 + K 3 ( z ) = δ 0 + + δ 1 z + δ 2 z 2 + δ 3 + z 3 + K 4 ( z ) = δ 0 + + δ 1 + z + δ 2 z 2 + δ 3 z 3 +
According to Kharitonov’s theorem, the family of polynomials (11) is robustly stable if and only if all Kharitonov’s polynomials are Schur stable, for more details about this property see [26,27,29,30].

3.1. Robust Controller Design via Interval Pole Placement Based on Kharitonov’s Theorem

To design the controller, a region of uncertainties must be defined based on the interval parameter variation of the plant model. According to [26,27], the controller can be designed based on the Kharitonov’s theorem applying linear programming to a set of linear inequality constraints. It was considering an n-th order of the strictly proper uncertain plant G ( z , p ) (i.e., the order of numerator is lesser the denominator, in other words, m < n ) and that presents an r R -th and r S -th the controller order that has the following polynomial structure R ( z ) , S ( z ) , respectively, and T ( z ) can be computed by the sum of all coefficients of the R ( z ) polynomial, in other words, it is only a static gain, due to the polynomial S ( z ) presents an integrator, when considering that the uncertain plant is the 0-type (i.e., it does not have an integrator), another way to compute the T ( z ) can be used the Internal Model Control (IMC) methodology to ensure that the system performs the desired behavior, such as that proposed by [31]. Furthermore, it is essential to define the desired constraints that allow the choice of the control structure in order to consider this control structure and order of the controller.
G ( z , δ ) = n ( z , δ ) d ( z , δ ) = b m z m + b m 1 z m 1 + + b 0 a n z n + a n 1 z n 1 + + a 0
R ( z ) = r r R z r R + r r R 1 z r R 1 + + r 0 S ( z ) = ( z 1 1 ) s r S z r S + s r S 1 z r S 1 + + s 0 T ( z ) = R ( 1 )
Thus, (12) and (13) can be computed as a polynomial closed loop, as follows.
P c l ( z ) = R ( z ) n ( z , δ ) + S ( z ) d n ( z , δ )
P c l ( z ) = [ r r R b m ] z m + r R + [ r r R b m 1 + r r R 1 b m ] z m + r R 1 + [ s r S a n ] z n + r S + [ a n ( s r S s r S 1 ) a n 1 s r S ] z n + r S 1 + + [ r 0 b 0 s 0 a 0 ]
Adopting the hyperbox region to represent a desired closed-loop polynomial containing a required performance, this region can serve each coefficient of the desired polynomial as a range depending on uncertain parameters, as described in (17).
D ( z ) = [ d n + r S , d n + r S + ] z n + r S + [ d n + r S 1 , d n + r S 1 + ] z n + r S 1 + + [ d 0 , d 0 + ]
When considering that closed-loop polynomial (cf. (14) and (15)) is inside of the region defined by the desired polynomial region (cf. (16)), the problem can be rewritten as a set of matrix inequalities, as follows.
B A X B +
where,
B = d n + r S d n + r S 1 d n + r S 2 d 0 B + = d n + r S + d n + r S 1 + d n + r S 2 + d 0 + X = r r R r r R 1 r 0 s r S s r S 1 s 0
A = b m 0 0 b m 1 b m 0 b m 2 b m 1 b m 0 0 0 | a n 0 0 | a n 1 a n 0 | a n 2 a n 1 a n | | a 0 a 1 a n
Thus, the problem of pole placement can be rewritten as a linear optimization problem and any linear programming methodology can be used to solve it. According to [26,27], any cost function can be chosen; however, a proper cost function is the sum of controller parameters, aiming at reducing controller gains and control effort. Hence, the problem presented in (17) can be rewritten as a linear optimization problem, as presented in (18).
X = a r g ( m i n ( f ( X ) ) ) s . t . A ( [ a , a + ] , [ b , b + ] ) A ( [ a , a + ] , [ b , b + ] ) X B ( d + ) B ( d )

3.2. Robust Design Methodology Based on Chebyshev Sphere

The optimization problem presented in the previous Subsection can be rewritten based on the Chebyshev sphere to represent the set of inequalities that describes the plant uncertainties. The Chebyshev theorem describes that it is possible to determine the largest compact set B of center and maximum radius, whose Euclidian norm, which is inscribed in a polytope P , is described by the set of the linear inequalities constraints [32]. Hence, the ball set can be observed in Figure 4, which the ball is inscribed in convex set P . Therefore, the set of solutions is more relaxed when compared with the one that is provided by Kharitonov’s rectangle.
To rewrite this optimization problem, suppose that P R n is defined by a set of convex inequalities, i.e., P = x R n | a i x b i , i N n . If R 0 it can be found an x (center of Chebyshev sphere) that solve the linear optimization problem, according to the following relations:
X = a r g ( m i n ( f ( X ) ) ) s . t . A upper ( [ a , a + ] , [ b , b + ] ) A lower ( [ a , a + ] , [ b , b + ] ) X B ( t + ) B ( t )
where,
X = X R A upper = A | | a u p p e r | | A | | a u p p e r | | 0 1 × n 1 A lower = A | | a l o w e r | | A | | a l o w e r | | 0 1 × n 1
where, | | . | | is the norm of coefficients of matrix A. Figure 5 provides a simplified flowchart of the design of the digital robust RST controller methodology for robust pole placement based on Chebyshev sphere constraints in the linear optimization problem (cf. Figure 5, (19) and (20)). The main difference between the Chebyshev convex optimization and the classical form of this problem is the conservativeness that is reduced for a methodology that is based on Chebyshev convex optimization, such that all the solutions to the compact set defined is possible [27,32]. Furthermore, this region ensures that the system obeys the constraints set defined, resulting in a less conservative solution. Figure 5 presents the flowchart of the proposed methodology for direct form to design the digital RST robust control by using the Chebyshev sphere as constraints to solve this problem.
The first step is to obtain the generic model of the plant, and the control structure (cf. showed in (12) and (13)), as shown in Figure 5. In the second step, the uncertainty region must be described. The uncertainty region is made of intervals of each plant parameters, with each coefficient of the polynomial being a range of the values (cf. presented in (9) and (10)). In the third step, the desired performance region is defined (cf. presented (16)) and the closed-loop polynomial is presented to evidence the dependence between each coefficient and controller parameters (cf. (14) and (15)). In the fourth step, the optimization problem is rewritten in order to maximize the radius of the Chebyshev sphere [32]; the constraints of the optimization problem are the same as those that are presented by Bhattacharyya et al. [26,27]. Subsequently, the solution must be tested; if the solution is not feasible, it is necessary to relax the constraints, that is, relaxing the desired performance to augment the uncertainty region. However, if the solution is feasible, a sixth step must be used, where it is written as the controller model using the feasible solution.

4. Methodology

In this section, the procedure to apply the proposed methodology is discussed, all controller gains are presented, and the adopted topology is described. Furthermore, the experimental environment is presented, and a brief description of the developed tests is given.

4.1. Presentation of the Experimental Environment

To perform the experiments, a DC-DC Buck converter test board was developed, c.f. shown in Figure 6. Table 1 presents the main elements that compound the experimental system as well as shows the main values of the parameters.
When considering the data presented in Table 1, it is possible to obtain the mathematical model of the buck converter (cf. Equation (8)), in addition, was considered the digital conversion by using the ZOH method and use the sampling frequency to discretize. The following equation presents the math model of the system in discrete domain.
V C ( z ) d ( z ) = 3.294 z + 3.223 z 2 1.286 z + 0.9842
When considering the uncertainty range of the load variation, the ZOH method was used to discretize the plant model, so the parametric interval transfer function is obtained, as follows.
V C ( z ) d ( z ) = [ 3.098 , 3.346 ] z + [ 2.84 , 3.328 ] z 2 [ 1.181 , 1.317 ] z + [ 0.7748 , 0.9842 ]
To design the controller, the following requirements are desired, such as settling time of 0.5 s and considering the maximum overshoot less than 15%. This condition is validated for classical pole placement; however, when the system is subject to a specific family uncertainty, this point of performance can be unfeasible. Therefore, to design the digital RST robust control for all methodologies investigated in this study, the following desired region was adopted: settling time-varying in the range 0.1–0.9 s and the maximum overshoot varying in the range 10–30%. Therefore, it is possible to determine the desired performance region (cf. presented in (16)). The control structure adopted can be displayed in Figure 7, which shows a generic block diagram to develop the system as well as the control signal can be computed by using the (23) as well as the structure adopted for each control polynomial. The controller gain values for each methodology are presented in Table 2. To compute the controller gains, an automatic computational routine is developed and executed by using the computer with the following specifications: Intel core i7-3770 processor (4 cores, 3.4–3.9 GHz of clock) and 16 Gb of RAM. Using that computer, the control design routine takes less than 6 s to compute the gains.
S ( z ) u = T ( z ) V r e f R ( z ) V c R ( z ) = r 2 z 2 + r 1 z + r 0 S ( z ) = z 1 T ( z ) = r 2 + r 1 + r 0

4.2. A Brief Description of the Experiments

Several tests were performed in order to evaluate the performance of the controllers designed; all the tests developed presented numerical results (simulation) and experimental results (i.e., obtained by the board system developed). Three types of tests were prepared, as follows:
Test 1—the first test focused on voltage setpoint variation. To perform this test, the system starts with the reference voltage of 5.0 V; at every 2 s, the pulse voltage setpoint is varied for 2 s, the first variation is the 1 V, then the pulse setpoint is increased 1 V in variation until 3 V beyond the setpoint was reached. In sequence, the same procedure was performed to decrease the pulse setpoint variation.
Test 2—the second test aimed to evaluate the performance of the digital RST controller when the system was subject to a load resistance variation. First, the DC-DC buck converter was tuned at the operational point of 5.0 V. Additionally, the load resistance value was 4.0 Ω . Then, at each 1.0 s, the load was varied by using the following values of load resistance variation around the nominal value of load resistance Δ R = [ 3.0 , 2.5 , 2.0 , 1.5 ] Ω . For each variation, the oscillation in the capacitor voltage was observed and an evaluation was done to determine which methodology outperforms the others approaches when the system was subject to parametric variation.
Test 3—the last test had the goal of quantifying the performance approaches by using integral indices. For this test, the integral square error (ISE) index was computed in order to assess the performance of the output signal and integral index ISCS to assess the energy of the control effort.

5. Assessment of the Results

This section discusses the main results of the three tests described above. Therefore, the proposed methodology is evaluated and compared to the other two well-known literature methods: the robust control method by Battacharyya et al. [26,27] based on the Kharitonov’s rectangle (cf. presented in Section 3) and the classical pole placement proposed by Landau et al. [31] that did not take into account the optimization process.

5.1. Test 1—Voltage Setpoint Variation

The first test was performed to assess the voltage reference variation. Figure 8 presents the simulation results of (a) presents the system output when the voltage reference varies and (b) presents the control effort. Figure 9 presents the experimental results of test 1.
Figure 8a shows that all control methodologies achieve the desired performance and compensate for the setpoint voltage variation. Figure 8b shows that all methodologies prevent saturation of the control signal. Figure 9a presents the output voltage, notice that all of the methodologies achieve the desired performance; however, the proposed method resents least voltage ripple as well as presents a smoother duty cycle variation, as shown in Figure 9b.
Figure 10 presents the zoomed simulation results of the positive setpoint voltage variation. Notice that the proposed methodology is faster than other approaches as well as presents the least voltage ripple in comparison the others, in addition the control methodology proposed by Landau et al. [31] presents some overshoot when negative setpoint voltage variation occurs, as shown in Figure 10f.
Figure 11 presents the negative setpoint voltage variation zoomed, aiming to show the behavior of each output voltage variation. In all negative variations, the proposed methodology provides better performance than others due to them presenting a voltage sag that delayed the correction of the output voltage; however, all methodologies achieve the desired target. In addition, the proposed methodology presented the minor voltage ripple.
Figure 12 and Figure 13 showed the zoom in output voltage of the experimental test in up and down setpoint variation, respectively. The experimental tests presented that the proposed methodology outperforms the others approaches for up and down setpoint voltage variations, besides that the proposed methodology shows a minor voltage ripple. However, all of the methodologies could correct the voltage setpoint variation. In Figure 13e, when the system vary to 2.0 V of the setpoint reference all methodologies presents the worst dynamic behavior, due the current of the system are near of the limit that promotes a transition of the operation model; however, during the tests, the converter operates in CCM mode and does not promote transition in your operate mode.

5.2. Test 2—Load Variation

The second test was performed in order to assess the load resistance variation, cf. described in the above section. Figure 14 shows the simulation results of the output response when the system was subjected to a load resistance variation, as well as presents the control effort of all control strategies.
Figure 14a presents the voltage output of the system, notice that when the load variation occurs, it causes a reduction in the load resistance, triggering an increase in the voltage ripple, besides all control methodologies investigated could correct these voltage oscillations promoted by the load variation. Meanwhile, Figure 14b presents the control effort to ensure the stability of the system when these load variations occur, notice that any present methodology saturation, so the proposed methodology represents a more significant control effort than other approaches.
Figure 15 shows a zoom in each voltage oscillations caused by the load variation of the system in simulation tests. In Figure 15, each load variation caused a voltage oscillation as well as considering a reduction in the load resistance promote an increase in the voltage ripple, it is worth to note that the proposed methodology quickly corrects these oscillations and presents a minor voltage ripple in comparison to the others approaches.
Figure 16 shows the experimental tests performed on the load variation. It is worth noting that, for each load variation, only the proposed methodology can correct all load variations as well as present the minor voltage ripple in comparison the others approach. According Figure 16b, Landau et al. [31] and Battacharrya et al. [26,27] methodologies presented a saturation in the control effort, due to this saturation they did not correct adequately all load variations, in addition they presented a large variation in the computed duty cycle.
Figure 17 shows the experimental tests of the load variation that presents the output voltage zoomed. Observe that only the proposed method could adequately correct the oscillations caused by the load variation. Besides that, the proposed methodology presents a minor voltage ripple than other approaches.

5.3. Test 3—Performance Indices

In the third test, the performance indices of tests 1 and 2 are computed, in order to quantify the robustness and effectiveness of investigated control methodologies. Figure 18a,b present the simulation and experimental results of the ISE index when the system is subject to a voltage setpoint variation, respectively.
Figure 18a presents that the proposed method outperforms the others approach for all variations, due the better performance presented; however, for the variation of 3 V the proposed methodology has the same value of the others, so, for this variation, is presented a degenerated performance of the proposed methodology, mainly due the large setpoint variation. Figure 18b presents the ISE index computed when considering the setpoint voltage variation of the experimental test. Figure 18b showed that the proposed methodology outperforms the others approaches as well as ratifies the results observed by the simulation test that presents effectiveness and robustness of the proposed methodology.
Figure 19a shows the ISC index computed when considering the setpoint voltage variation in simulation test, aiming to evaluate the energy demanded to correct each setpoint variation. Figure 19a showed that the proposed methodology has greater demand of energy than others approach; however, all variations were corrected, and any saturation was observed for the simulation test. Figure 19b shown the ISC index computed considering the setpoint voltage variation of the experimental test.
Figure 19b presents that the proposed methodology has a greater demand of energy for almost all variations disregarding the points of 1 V and 2 V of the variations, that the proposed methodology presents the minor index in comparison with the other approaches. Figure 20 shown the ISE indices for load resistance variation of the simulation and experimental tests, respectively.
Figure 20a presents the ISE index that was computed from the simulation test considering the load variation, notice that the proposed method outperforms the others approaches in all load variations. Figure 20b presents the experimental indices ISE computed when considering the load resistance variation, this figure presents the proposed methodology presents the better performance in comparison with the others approaches; in addition, only the proposed methodology correct adequately each load resistance variation, and not present any saturation during the test, on the other hand, the others approaches not adequately correct these oscillations, and presents a saturation all times that occurs load variation. These results ratify the proposed methodology is more effectiveness and robustness in comparison the others investigated.
Figure 21a presents the ISC indices for load variation of the simulation test. Then, these ISC indices demonstrates that the proposed methodology has a greater energy demanded in comparison of the others approaches considering the simulation test. Figure 21b showed the experimental indices ISC, so the proposed methodology presents the minor indices, due to the other approaches presenting saturation during the load variation, then these methodologies not adequately corrects these load variations, so only the proposed methodology corrects these oscillations, cf. presented in Figure 16 and Figure 17, ratifying the robustness and effectiveness of the proposed methodology.

6. Conclusions

This paper proposed a direct form to design the digital robust RST control, when considering the Chebyshev sphere a constraint of the linear optimization problem, this control technique aims to ensure the robust stability and robust performance of the system. Additionally, the Chebyshev theorem was used to relax the solution proposed by the Kharitonov’s rectangle, regarding all solutions into the sphere. Several simulations and experiments were performed in order to evaluate the performance and stability when the DC-DC buck converter is subject to a voltage setpoint variation, and parametric variation, in other words, was varied the load resistance. The proposed methodology was compared with two different methodologies, first is the classical methodology that is based on Landau et al. [25] method, and the second is the robust control based on the Battacharya et al. method [20]. Furthermore, the integral indices were computed by using the results that were obtained by the tests to quantify the performance and stability of the system for each control methodology, aiming to better analysis the effectiveness and robustness. Finally, the proposed methodology outperforms the others approaches in all tests performed, it is essential to note that only the proposed methodology could adequately correct the parametric variation during the experimental tests that ratify the effectiveness and robustness of the proposed methodology.

Author Contributions

Conceptualization, C.C.d.N., W.B.J., R.L.P.d.M. and I.V.B. (Iury V. Bessa); Data curation, R.L.P.d.M.; Formal analysis, R.L.P.d.M., F.A.C.A.J., I.V.B. (Iury V. Bessa), I.V.B. (Isaías V. Bessa), G.d.M.V., L.E.S.eS. and N.J.S.F.; Funding acquisition, C.C.d.N.; Investigation, W.B.J., R.L.P.d.M., F.A.C.A.J., I.V.B. (Iury V. Bessa), I.V.B. (Isaías V. Bessa), G.d.M.V., L.E.S.eS. and N.J.S.F.; Methodology, W.B.J., R.L.P.d.M., F.A.C.A.J., I.V.B. (Iury V. Bessa), G.d.M.V. and L.E.S.eS.; Project administration, R.L.P.d.M.; Resources, C.C.d.N., R.L.P.d.M., F.A.C.A.J., I.V.B. (Iury V. Bessa) and I.V.B. (Isaías V. Bessa); Software, R.L.P.d.M., I.V.B. (Isaías V. Bessa) and N.J.S.F.; Supervision, R.L.P.d.M. and N.J.S.F.; Validation, R.L.P.d.M., F.A.C.A.J., I.V.B. (Iury V. Bessa) and N.J.S.F.; Visualization, R.L.P.d.M., F.A.C.A.J., I.V.B. (Iury V. Bessa) and I.V.B. (Isaías V. Bessa); Writing—original draft, R.L.P.d.M. and F.A.C.A.J.; Writing—review & editing, C.C.d.N., W.B.J., R.L.P.d.M., F.A.C.A.J., I.V.B. (Iury V. Bessa), I.V.B. (Isaías V. Bessa), G.d.M.V., L.E.S.eS. and N.J.S.F. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by Samsung Electronics of Amazonia Ltda, under the terms of Federal Law nº 8.387/1991, through agreement nº 004, signed with the Center for R & D in Electronics and Information from the Federal University of Amazonas-CETELI/UFAM and by FAPEAM grant number 062.00272/2020.

Acknowledgments

This research, according for in Article 48 of Decree nº 6.008/2006, was funded by Samsung Electronics of Amazonia Ltda, under the terms of Federal Law nº 8.387/1991, through agreement nº 004, signed with the Center for R & D in Electronics and Information from the Federal University of Amazonas-CETELI/UFAM. The authors acknowledge all scientific contributions by the members of the research groups of e-Controls (UFAM),IFAM, and LACSPOT (UFPA) for development of this research. This research was partially funded by scholarships provided by research support of Foundation of the State of Amazonas (FAPEAM) through scholarships and by FAPEAM grant number 062.00272/2020.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. The typical topology of the DC-DC Buck power converter.
Figure 1. The typical topology of the DC-DC Buck power converter.
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Figure 2. Functioning stages of DC-DC Buck power converter. (a) The switching element is on; (b) the switching element is off.
Figure 2. Functioning stages of DC-DC Buck power converter. (a) The switching element is on; (b) the switching element is off.
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Figure 3. Waveforms of the DC-DC Buck converter when the system operates in continuous conduction mode (CCM) mode.
Figure 3. Waveforms of the DC-DC Buck converter when the system operates in continuous conduction mode (CCM) mode.
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Figure 4. Largest compact set B circumscribed in a convex set of P.
Figure 4. Largest compact set B circumscribed in a convex set of P.
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Figure 5. Flowchart of control design methodology based on Chebyshev sphere.
Figure 5. Flowchart of control design methodology based on Chebyshev sphere.
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Figure 6. DC-DC Buck converter test board developed and experimental environment.
Figure 6. DC-DC Buck converter test board developed and experimental environment.
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Figure 7. Generic block diagram of the control RST topology implementation.
Figure 7. Generic block diagram of the control RST topology implementation.
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Figure 8. Simulation results of the voltage setpoint variation. (a) Voltage variation; (b) Duty cycle.
Figure 8. Simulation results of the voltage setpoint variation. (a) Voltage variation; (b) Duty cycle.
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Figure 9. Experimental results of the voltage setpoint variation. (a) Voltage variation; (b) Duty cycle.
Figure 9. Experimental results of the voltage setpoint variation. (a) Voltage variation; (b) Duty cycle.
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Figure 10. Simulation results of the positive voltage setpoint variation. (a) V r e f = 6.0 V; (b) V r e f = 5.0 V; (c) V r e f = 7.0 V; (d) V r e f = 5.0 V; (e) V r e f = 8.0 V; (f) V r e f = 5.0 V.
Figure 10. Simulation results of the positive voltage setpoint variation. (a) V r e f = 6.0 V; (b) V r e f = 5.0 V; (c) V r e f = 7.0 V; (d) V r e f = 5.0 V; (e) V r e f = 8.0 V; (f) V r e f = 5.0 V.
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Figure 11. Simulation results of the negative voltage setpoint variation. (a) V r e f = 4.0 V; (b) V r e f = 5.0 V; (c) V r e f = 3.0 V; (d) V r e f = 5.0 V; (e) V r e f = 2.0 V; (f) V r e f = 5.0 V.
Figure 11. Simulation results of the negative voltage setpoint variation. (a) V r e f = 4.0 V; (b) V r e f = 5.0 V; (c) V r e f = 3.0 V; (d) V r e f = 5.0 V; (e) V r e f = 2.0 V; (f) V r e f = 5.0 V.
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Figure 12. Experimental results of the positive voltage setpoint variation. (a) V r e f = 6.0 V; (b) V r e f = 5.0 V; (c) V r e f = 7.0 V; (d) V r e f = 5.0 V; (e) V r e f = 8.0 V; (f) V r e f = 5.0 V.
Figure 12. Experimental results of the positive voltage setpoint variation. (a) V r e f = 6.0 V; (b) V r e f = 5.0 V; (c) V r e f = 7.0 V; (d) V r e f = 5.0 V; (e) V r e f = 8.0 V; (f) V r e f = 5.0 V.
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Figure 13. Experimental results of the negative voltage setpoint variation. (a) V r e f = 4.0 V; (b) V r e f = 5.0 V; (c) V r e f = 3.0 V; (d) V r e f = 5.0 V; (e) V r e f = 2.0 V; (f) V r e f = 5.0 V.
Figure 13. Experimental results of the negative voltage setpoint variation. (a) V r e f = 4.0 V; (b) V r e f = 5.0 V; (c) V r e f = 3.0 V; (d) V r e f = 5.0 V; (e) V r e f = 2.0 V; (f) V r e f = 5.0 V.
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Figure 14. Simulation results of the output voltage when the system subject to a load variation. (a) Capacitor voltage; (b) Duty cycle.
Figure 14. Simulation results of the output voltage when the system subject to a load variation. (a) Capacitor voltage; (b) Duty cycle.
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Figure 15. Zoom in simulation results of the output voltage when the system subject to a load variation. (a) R r e f = 2.5 Ω ; (b) R r e f = 3.0 Ω ; (c) R r e f = 3.5 Ω ; (d) R r e f = 4.0 Ω ;.
Figure 15. Zoom in simulation results of the output voltage when the system subject to a load variation. (a) R r e f = 2.5 Ω ; (b) R r e f = 3.0 Ω ; (c) R r e f = 3.5 Ω ; (d) R r e f = 4.0 Ω ;.
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Figure 16. Experimental results of the output voltage when the system subject to a load variation. (a) Capacitor voltage; (b) Duty cycle.
Figure 16. Experimental results of the output voltage when the system subject to a load variation. (a) Capacitor voltage; (b) Duty cycle.
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Figure 17. Zoom in experimental results of the output voltage when the system subject to a load variation. (a) R r e f = 2.5 Ω ; (b) R r e f = 3.0 Ω ; (c) R r e f = 3.5 Ω ; (d) R r e f = 4.0 Ω .
Figure 17. Zoom in experimental results of the output voltage when the system subject to a load variation. (a) R r e f = 2.5 Ω ; (b) R r e f = 3.0 Ω ; (c) R r e f = 3.5 Ω ; (d) R r e f = 4.0 Ω .
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Figure 18. Cost function ISE when occurs the voltage setpoint variation. (a) Simulation and (b) Experimental test.
Figure 18. Cost function ISE when occurs the voltage setpoint variation. (a) Simulation and (b) Experimental test.
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Figure 19. Cost function ISC when occurs the voltage setpoint variation. (a) Simulation and (b) Experimental test.
Figure 19. Cost function ISC when occurs the voltage setpoint variation. (a) Simulation and (b) Experimental test.
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Figure 20. Cost function ISE when occurs the load variation. (a) Simulation and (b) Experimental test.
Figure 20. Cost function ISE when occurs the load variation. (a) Simulation and (b) Experimental test.
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Figure 21. Cost function ISC when occurs the load variation. (a) Simulation and (b) Experimental test.
Figure 21. Cost function ISC when occurs the load variation. (a) Simulation and (b) Experimental test.
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Table 1. Main parameters of the experimental system developed.
Table 1. Main parameters of the experimental system developed.
Par.UnityVal.Description
V s V10.0Voltage of the source
R Ω 1.4–22.4Load resistance
C μ F5600Capacitance element
LmH1.0Inductance element
f s w kHz20.0Switching frequency
f a m kHz2.0Sample frequency
Q 1 --Mosfet IRF540N
D 1 --Diode - 1N4012
Table 2. Gain values of the digital controller of all methodologies investigated.
Table 2. Gain values of the digital controller of all methodologies investigated.
Proposed
Method
Battacharyya et al. [27]Landau et al. [31]
r 2 0.43381.01.2338
r 1 −0.5206−0.80−1.2338
r 0 0.15150.120.2952
T ( z ) 0.06470.320.2952

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C. das Neves, C.; B. Junior, W.; Medeiros, R.L.P.d.; Ayres Junior, F.A.C.; V. Bessa, I.; Bessa, I.V.; de M. Veroneze, G.; E. S. e Silva, L.; J. S. Farias, N. Direct Form Digital Robust RST Control Based on Chebyshev Sphere Optimization Applied in a DC-DC Power Converter. Energies 2020, 13, 3810. https://doi.org/10.3390/en13153810

AMA Style

C. das Neves C, B. Junior W, Medeiros RLPd, Ayres Junior FAC, V. Bessa I, Bessa IV, de M. Veroneze G, E. S. e Silva L, J. S. Farias N. Direct Form Digital Robust RST Control Based on Chebyshev Sphere Optimization Applied in a DC-DC Power Converter. Energies. 2020; 13(15):3810. https://doi.org/10.3390/en13153810

Chicago/Turabian Style

C. das Neves, Cleonor, Walter B. Junior, Renan L. P. de Medeiros, Florindo A. C. Ayres Junior, Iury V. Bessa, Isaías V. Bessa, Gabriela de M. Veroneze, Luiz E. S. e Silva, and Nei J. S. Farias. 2020. "Direct Form Digital Robust RST Control Based on Chebyshev Sphere Optimization Applied in a DC-DC Power Converter" Energies 13, no. 15: 3810. https://doi.org/10.3390/en13153810

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