Hybrid DC Converter with Current Sharing and Low Freewheeling Current Loss

Abstract

A new hybrid high-frequency link pulse-width modulation (PWM) converter using voltage balance capacitor and current balance magnetic coupling is proposed to realize low freewheeling current loss and wide load range of soft switching operation. Series-connected H-bridge converter is adopted for high voltage applications. In addition, a voltage balance capacitor and a current balance magnetic coupling core are employed for achieving voltage and current balance. To extend zero-voltage switching (ZVS) range of switches at lagging-leg of phase-shift PWM converter, soft switching LLC converter is linked to the lagging-leg of phase-shift PWM converter. Therefore, the wide ZVS load operation is realized in the presented hybrid converter. The other high freewheeling current disadvantage in conventional phase-shift PWM converter is improved by a snubber circuit used on low-voltage side. Thus, the primary current during the freewheeling state is decreased and close to zero. In addition, the conduction losses on primary-side components of studied converter are reduced. The secondary-sides of phase-shift PWM converter and LLC resonant converter are series-connected to achieve power transfer between input and output sides. Experimental results using a laboratory prototype are provided to demonstrate the effectiveness of the studied circuit and control algorithm.

1. Introduction

Medium voltage high-frequency link power converters have been presented and developed for boat electric power applications [1], industry power units [2], dc microgrids [3,4,5] and dc traction vehicles [6,7] to reduce the environmental impacts and global warming issue. To deal the medium voltage input such as 750 V, power switches, 1200 V insulated gate bipolar transistor (IGBT) or silicon carbide (SiC), can be adopted in conventional pulse-width modulation (PWM) converters to achieve power transfer or energy conversion. The drawback of IGBT power devices is low switching frequency operation and high turn-off switching loss. The disadvantage of the SiC power devices is their high cost. MOSFET power devices have the advantages of low cost and high performance capabilities to realize and develop modern power converters. Three-level PWM converters [8,9,10] can be used for high voltage input applications by using low voltage stress power switches. Full bridge converters are widely adopted to accomplish high power output. Pulse-width modulation with phase shift technique can improve power devices to be turned on under soft switching condition. However, the main weaknesses of phase-shift PWM converters are high freewheeling current and switching loss under low load condition. In [11], the snubber circuit is used on the output-side in order to lessen voltage overshoots on the rectifier diodes and also decrease the freewheeling current at the commutation state. To improve the switching loss of power switches at lagging-leg of phase-shift PWM converter under low load condition, an auxiliary circuit connected to the lagging-leg has been used in [12]. To achieve high efficiency PWM converter, phase-shift PWM converters with a resonant circuit connected to lagging-leg have been studied and developed in [13,14] to extend the soft switching range. For increasing power rating and circuit efficiency, the modular converter with series or parallel connection of several low power rating circuits has been studied and presented in [15]. The main challenge of modular converter is current balancing issue on each modular. Several current control approaches have been discussed in [16,17] to accomplish the current balance for each modular.

A hybrid PWM converter is studied and presented to achieve the advantages of low freewheeling current loss, the balanced current and voltage on two circuit modules and low switching loss on power switches. Two series-connected circuit modules are adopted to reduce the voltage stress on active devices and current stress on rectifier diodes. A flying capacitor is adopted on the primary-side to achieve voltage balance of input split capacitors. LLC converters sharing the lagging-leg switches of phase-shift PWM converters are used in the presented circuit to realize wide load range of soft switching operation. Two magnetic current balancing components are adopted on phase-shift PWM converters and LLC converters to achieve current sharing between two circuit modules. To reduce the high circulating current problem of conventional phase-shift PWM converters, a passive snubber is connected to the secondary-side rectified terminal. The structure and operation principle of the converter are discussed in Section 2 and Section 3. In Section 4 and Section 5, the circuit analysis and experiments with 1.68 kW prototype are provided. Finally, a conclusion of the studied converter is given in Section 6.

2. Circuit Diagram

In medium input voltage applications, the phase-shift PWM circuit topologies are widely used for medium and high-power converters. However, the conventional phase-shift PWM converter has the drawbacks of hard switching problem of power switches at the lagging-leg and high freewheeling current problem at the commutation state. For high voltage applications, three-level PWM dc converters or cascade converters shown in Figure 1 have been proposed to reduce voltage stress of active switches using high frequency power MOSFETs. The advantages of the cascade converters are less current rating of active switches compared to three-level converters and possible modular operation to extend input voltage range. However, the current sharing and input voltages balance are main problems of cascade full bridge converter. The circuit schematic in Figure 2a can overcome the problems of input voltage and current balance issues using a balance capacitor (highlighted in blue) between two circuit modules and a magnetic coupling element on primary-side (highlighted in red)). For extending the soft switching operation range at lagging-leg switches, LLC converter (remark in purple) and phase-shift PWM converter share the same lagging-leg switches shown in Figure 2b. Since a LLC converter has inductive input impedance characteristics, the wide soft switching operation of lagging-leg switches can be realized in the presented circuit and the weaknesses of conventional phase-shift PWM converters are overcome. Two phase-shift PWM and two LLC circuits are used on the input-side and two full-wave diode-rectifiers are adopted on the output-side. PWM scheme is adopted to control two full bridge converters. The magnetic coupling component MC1 is adopted to achieve current balance of i_p1 and i_p2. If the currents i_p1 and i_p2 are balanced, the induced voltages on primary and secondary sides of MC1 are zero. If |i_p1| > |i_p2|, the induced voltages V_MC1,1 and V_MC1,2 decrease and increase respectively so that |i_p1| and |i_p2| will be decreased and increased respectively. After i_p1 = i_p2, the induced voltages V_MC1,1 = V_MC1,2 = 0. A voltage balance capacitor C_b is connected between two full bridge circuits. Since S₁, S₂, S₅ and S₆ have the same duty cycle (d = 0.5), one can obtain V_Cb = V_C1 = V_C2 = V_in/2. Two full bridge circuits are series connection on primary-sides and parallel connection on secondary-sides with a single transformer T₁ to reduce the current rating on primary-side of phase-shift PWM circuits. Passive snubber circuit, C_p, D_p1 and D_p2, is used to decrease i_p1 and i_p2 to zero at the commutation interval. Then, the high freewheeling current issue in conventional phase-shift PWM converter is eliminated. Since the switching frequency of LLC converters is close to series resonant frequency, the lagging-leg switches S₃, S₄, S₇ and S₈ are turned on at ZVS operation. At the active states (v_AB and v_DE = +V_in/2 or −V_in/2) of full bridge circuits, both PWM converters and LLC converters can achieve power transfer between V_in and V_o. On the other hand, only LLC resonant circuits achieve power transfer at the commutation state (v_AB and v_DE = 0 V).

3. Principles of Operation

In the proposed circuit topology, each active device has T_sw/2 turn-on time. The switching signals S₁–S₄ and S₅–S₈ are identical. The power components in the first and second circuits are identical to simplify the circuit analysis. In the proposed converter, n_T1,p1 = n_T1,p2 (primary turns of T₁), n_T2,p1 = n_T2,p2 (primary turns of T₂), C_S1 = … = C_S8 = C_oss, L₁ = L₂ = L_lk1, L_r1 = L_r2 = L_r, and C_r1 = C_r2 = C_r. Figure 3 gives the PWM waveforms of the studied circuit and the related step circuits during one-half of switching period are provided in Figure 4.

Step 1 [t₀, t₁]: Before time t₀, S₁, S₄, S₅ and S₈ conduct. At time t₀, active devices S₅ and S₁ are turned off. i_p1 and i_p2 will charge C_S1 and C_S5 and discharge C_S2 and C_S6. If the energy on L_o, L₁ and L₂ is larger than C_S1, C_S2, C_S5 and C_S6, then C_S6 and C_S2 are discharged and the zero-voltage switching of S₆ and S₂ can be realized at t₁. Therefore, the time duration in this step is calculated:

$$\Delta t_{01}=\frac{C_{oss}{V}_{in}}{i_{p1}(t_0)}\approx \frac{C_{oss}{V}_{in}}{i_{Lo,\max }/n_1}$$

(1)

where n₁ = n_T1,p1/n_T1,s turns ratio of transformer T₁. Since i_Lr1 < i_Lm1,T2 and i_Lr2 < i_Lm2,T2, the secondary-side rectifier diodes D₄ conducts.

Step 2 [t₁, t₂]: The voltages v_CS2 = v_CS6 = 0 at t₁. The body diodes of switches S₆ and S₂ conduct due to i_p1(t₁) > 0 and i_p2(t₁) > 0. Therefore, the ZVS turn-on operation of S₆ and S₂ are realized. In step 2, V_Cb = V_C2, v_AB = v_DE = v_BC = v_EF = 0, i_p1 and i_p2 decrease and D_p1 conducts. Therefore, the primary voltages of T₁ is equal to n₁v_Cp and the voltage on L_o is equal to v_Cp − V_o1. Since v_Lo < 0, i_Lo decreases in step 2. The time interval in step 2 is calculated in Equation (2):

$$\Delta t_{12}\approx \frac{L_{lk1}{i}_{Lo,\max }}{2n_1^2{v}_{Cp}}$$

(2)

Since the primary voltages of T₁ are positive, the primary currents i_p1 and i_p2 will decrease to zero during the circulating state. LLC resonant circuits are operated at resonant frequency (f_sw ≈ f_r). The rectifier diodes D₄ is conducting to deliver power to output V_o2.

Step 3 [t₂, t₃]: The secondary-side diode current i_D1 decreases to zero at time t₂. The currents i_p1 = i_Lm1 and i_p2 = i_Lm2 so that the wheeling currents are reduced in this step. The inductor current i_Lo flows through passive components D_p1 and C_p1 and i_Lo decreases due to v_Cp < V_o1. LLC resonant converter achieves energy transfer through T₂ and D₄.

Step 4 [t₃, t₄]: Active devices S₈ and S₄ are turned off at t₃. i_Lr1 < 0 and i_Lr2 < 0 so that C_S7 and C_S3 are discharged. At time t₄, C_oss3 is discharged to zero. Due to LLC resonant converters operated at the series resonant frequency, the ZVS turn-on operation of S₇ and S₃ are realized.

Step 5 [t₄~t₅]: v_Cs3 and v_CS7 decrease to zero voltage at t₄. Since i_S7(t₄) and i_S3(t₄) are negative, the antiparallel diodes of S₇ and S₃ are forward biased. Therefore, the ZVS operation of S₇ and S₃ is achieved after time t₄. At step 5, the ac side voltages v_Cb = V_C2, v_AB = v_DE ≈ −V_in/2, v_BC = v_EF ≈ V_in/4 and D₂ and D₃ conduct. Due to |n₁i_p1 + n₁i_p2| < i_Lo, D_p1 still conducts, v_L1 = v_L2 = n₁v_Cp − V_in/2 < 0, and v_Lo = v_Cc − V_o < 0. Thus, i_Lo decreases and i_p1 and i_p2 decrease. LLC resonant converters are resonant with input voltage V_in/2 so that i_Lr1 and i_Lr2 increase. At t₅, |n₁i_p1 + n₁i_p2| = i_Lo so that D_p1 becomes reverse biased and D_p2 becomes forward biased. The time interval between t₄ and t₅ can be calculated as:

$$\Delta t_{45}=t_5-t_4\approx \frac{L_{lk1}{I}_{Lo}}{2n_1(V_{in}/2-n_1{v}_{Cp})}$$

(3)

No power is transferred in step 5 and the duty cycle loss in step 5 is calculated in (4):

$$d_{5,loss}=\Delta t_{45}/T_{sw}\approx \frac{L_{lk1}{I}_{Lo}{f}_{sw}}{2n_1(V_{in}/2-n_1{v}_{Cp})}$$

(4)

Step 6 [t₅, t₆]: This step starts at time t₅ when D_p1 (D_p2) are reverse (forward) biased. Since D_p2 conducts, it can obtain v_Lo = v_Cp2 and i_Lo increases. L₁ and C_p/(n₁)² are resonant in step 6. In order to ensure D_p2 becomes reverse biased before step 7, the half resonant period by L₁ and C_p/(n₁)² must be less than d_eff,minT_sw (the minimum turn-on time). In step 6, v_T1,p1 = v_T1,p2 = −(v_Cp+V_o1) and i_p1 = i_p2 = −(i_Lo + i_Cp)/(2n₁).

Step 7 [t₆, t₇]: At time t₆, i_Dp2 = 0. In this step, passive components D_p1 and D_p2 are reverse biased, v_Lo = V_in/(2n₁) − V_o1 and i_Lo increases. S₆ and S₂ turn off at t₇ and the first half switching cycle is ended.

4. Circuit Analysis

In the proposed converter, phase-shift PWM converter realize power transfer to V_o1 in steps 5–7 in the one-half of switching period and LLC resonant converter achieve power transfer to V_o2 in every switching cycle. Since the switching frequency of LLC converter is fixed and close to series resonant frequency, the output voltage V_o2 is unregulated. The ZVS turn-on of S₃, S₄, S₇ and S₈ can be achieved due to LLC converter operation with the following condition:

$$i_{Lm1,\mathrm{T}2,\max }=i_{Lm2,T2,\max }\ge \frac{V_{in}}{2}\sqrt{\frac{C_{oss}}{L_r}}$$

(5)

where i_Lm1,T2,max and i_Lm2,T2,max are the maximum magnetizing currents on L_m1,T2 and L_m2,T2, respectively. According to the switching frequency, transformer turns ratio, load voltage and the magnetizing inductances, i_Lm1,max and i_Lm2,max are obtained in Equation (6):

$$i_{Lm1,T2,\max }=i_{Lm2,T2,\max }=\frac{\Delta i_{Lm1}}{2}\approx \frac{n_2{V}_{o2}{T}_{sw}}{4L_m}$$

(6)

The dead time between S₃ and S₄ is calculated in Equation (7):

$$t_d>\frac{C_{oss}{V}_{in}}{i_{Lm1,T2,\max }}=\frac{4L_m{C}_{oss}{V}_{in}}{n_2{V}_{o2}{T}_{sw}}$$

(7)

From the given dead time t_d, the maximum magnetizing inductances L_m1,T2 = L_m2,T2 = L_m,T2 are expressed in Equation (8):

$$L_{m,T2}\le \frac{n_2{V}_{o2}{T}_{sw}{t}_d}{4C_{oss}{V}_{in}}$$

(8)

Since the LLC converter has unity voltage gain at resonant frequency, the output voltage V_o2 is calculated in Equation (9):

$$V_{o2}=\frac{V_{in}}{4n_2}$$

(9)

The zero-voltage switching condition of S₁, S₂, S₅ and S₆ is expressed in Equation (10):

$$L_{lk1}{i}_{p1}^2(t_0)+\frac{n_1^2{L}_o{i}_o^2(t_0)}{4}\ge \frac{C_{oss}{V}_{in}^2}{2}$$

(10)

According to flux balance on leakage inductance on the secondary-side, the average voltage on C_p is obtained as V_Cp ≈ V_in/(2n₁) − V_o1. The output voltage V_o1 on steady state is calculated in Equation (11) by applying flux balance on L_o:

$$V_{o1}\approx \frac{V_{in}}{4n_1(1-d_{eff})}$$

(11)

where the effective duty cycle d_eff = d − d_5,loss and d is duty ratio of phase-shift PWM converter. Thus, the load voltage V_o is expressed in Equation (12) and the dc voltage gain is calculated in Equation (13):

$$V_o=V_{o1}+V_{o2}=\frac{V_{in}}{4(1-d_{eff})n_1}+\frac{V_{in}}{4n_2}$$

(12)

$$G_{dc}=\frac{V_o}{V_{in}}=\frac{1}{4n_1(1-d_{eff})}+\frac{1}{4n_2}=\frac{n_2+n_1(1-d_{eff})}{4n_1{n}_2(1-d_{eff})}$$

(13)

The ripple current Δi_Lo is expressed in Equation (14):

$$\Delta i_{Lo}\approx \frac{(V_{o1}-V_{Cp})(0.5-d_{eff})T_{sw}}{L_o}=\frac{d_{eff}(1-2d_{eff})V_{in}{T}_{sw}}{4n_1(1-d_{eff})L_o}$$

(14)

The minimum output inductance L_o is derived in Equation (15) under the given ripple current Δi_Lo:

$$L_{o,\min }\ge \frac{d_{eff}(1-2d_{eff})V_{in}{T}_{sw}}{4n_1(1-d_{eff})\Delta i_{Lo}}$$

(15)

The ripple currents on the magnetizing inductors of T₁ are calculated in Equation (16):

$$\Delta i_{Lm1,T1}=\Delta i_{Lm2,T1}\approx \frac{V_{in}{d}_{eff}{T}_{sw}}{2L_{m,T1}}$$

(16)

The theoretical voltage stress of S₁~S₈ is V_in/2. The voltage stress of D₁ and D₂ are equal to V_in/n₁. The voltage stresses of D₃ and D₄ are equal to V_in/(2n₂). The approximate voltage ratings of diodes D_p1 and D_p2 are $V_{in}/[4n_1(1-d_{eff})]$. The approximate average currents of D₁ and D₂ are equal to dI_o and the average currents of D₃ and D₄ are (0.5 − d)I_o. The inductor ratio L_m1,T2/L_r1 of LLC converter is selected as 8. From the obtained L_m1,T2, the L_r1 and L_r2 are equal to L_m1,T2/8 and C_r1 and C_r2 are equal to $1/[4{\pi }^2{f}_{sw}^2{L}_{r1}]$.

5. Design Considerations and Test Results

The design procedures and the test results are provided in this section with the following electric specifications: V_in = 750–800 V, V_o = 48 V, I_o = 35 A and f_r (resonant frequency of LLC converter) = f_sw (switching frequency) = 60 kHz. The assumed load voltages V_o1 = 28 V and V_o2 = 20 V. Since f_sw = f_r, the voltage gain of LLC resonant circuit is equal to unity. Therefore, n₂ of transformer T₂ can be calculated and expressed in Equation (17):

$$n_2=\frac{V_{in,\max }}{4V_{o2}}=10$$

(17)

G20N50C power MOSFETs with 500 V/20 A voltage/current stress and C_oss = 300 pF are used for power devices S₁~S₈. The maximum magnetizing inductance of T₂ can be calculated as:

$$L_{m,T2}\le \frac{n_2{V}_{o2}{T}_{sw}{t}_d}{4C_{oss}{V}_{in,\min }}\approx 1.8\mathrm{mH}$$

(18)

where t_d = 0.5 μs. The magnetic core EER42 is used to implement transformer T₂ with the magnetizing inductances L_m1,T2 = L_m2,T2 = 0.664 mH, the primary turns n_T2,p1 = n_T2,p2 = 30 and the secondary turns n_T2,s = 3. Therefore, the series resonant inductances L_r1 = L_r2 = L_m1,T2/8 = 83 μH and the series resonant capacitances C_r1 and C_r2 are expressed as $C_{r1}=C_{r2}\approx 1/[4{\pi }^2{f}_{sw}^2{L}_{r1}]\approx 85\mathrm{nF}$. From the assumed d_eff,max = 0.3, the turns ratio n₁ of transformer T₁ is calculated as:

$$n_1<\frac{V_{in,\min }}{4V_{o1}(1-d_{eff,\max })}\approx 9.5$$

(19)

The magnetic core EER42 is used to design transformer T₁ with the following parameters: L_m1,T1 = L_m2,T1 = 4 mH, n_T1,p1 = n_T1,p2 = 57 and n_T1,s = 6. The duty cycle loss d_5,loss is assumed 0.01. Therefore, the necessary inductances L₁ and L₂ of full bridge converter are calculated in Equation (20):

$$L_1=L_2=L_{lk1}=\frac{2d_{5,loss}{n}_1(V_{in,\min }/2-n_1{v}_{Cp})}{I_{Lo,rated}{f}_{sw}}\approx 24\mathsf{\mu }\mathrm{H}$$

(20)

If the ripple current ratio Δi_Lo/I_o,rated is assumed 0.2, then the minimum output inductance L_o is obtained in Equation (21):

$$L_{o,\min }\ge \frac{d_{eff,\max }(1-2d_{eff,\max })V_{in,\min }{T}_{sw}}{4n_1(1-d_{eff,\max })\Delta i_{Lo}}\approx 8\mathsf{\mu }\mathrm{H}$$

(21)

The inductance L_o = 10 μH is used in the prototype circuit. MPR40100PT with V_RRM = 100 V/I_F = 40 A are adopted for the secondary-side diodes D₁–D₄, D_p1 and D_p2. The other capacitors C₁ = C₂ = 180 μF/450 V, C_b = 2 μF and C_o1 = C_o2 = 2000 μF. The magnetic cores EER 42 are used for current balance magnetic cores MC1 and MC2 with n_p = n_s = 24.

Figure 5 gives the test results of switching waveforms of S₁, S₄, S₅ and S₈ at 750 V and 800 V input cases under full load. The switching signals S₁ (S₄) and S₅ (S₈) are identical and the PWM signals of S₄ (S₈) are lagging to the PWM signals of S₁ (S₅). Figure 6 shows the experimental voltages v_AB and v_DE and currents i_p1 and i_p2 of the phase-shift PWM converters under 20% and 100% loads. The primary-side currents i_Lp1 and i_Lp2 are well balanced. The duty cycle on v_AB and v_DE at 100% load is larger than the duty cycle at 20% load due to d_5,loss in step 5 is related to I_o. One can observe that the freewheeling currents of i_p1 and i_p2 are improved and close to zero. Figure 7 provides the experimental waveforms of the LLC resonant circuits at 20% and 100% loads. The inductors currents i_Lr1 and i_Lr2 are well balanced. Since f_sw = f_r, S₃, S₄, S₇ and S₈ are turned on at ZVS operation over whole load range. Figure 8 provides the test waveforms of capacitor voltages at primary-side under the full load with 800 V input. The capacitor voltages V_C1, V_C2 and V_Cb are all balanced. Figure 9a,b show the measured secondary-side currents of phase-shift PWM converter at 100% load. Passive snubber diode D_p1 is forward biased when the ac side voltages v_AB and v_DE are zero voltage (the circulating state) and diode D_p2 is forward biased when diode current i_D1 or i_D2 is greater than inductor current i_Lo. Figure 9c provides the test waveforms of the output currents of LLC resonant converter at 100% load. The measured input current I_in, load current I_o and load voltage V_o at 800 V input and 100% load are provided in Figure 9d. Figure 10a,b illustrate the experimental voltage and current of S₁ at 20% and 100% loads. One can observe that S₁ is turned on under zero voltage for both 20% and 100% loads. Likewise, the measured waveforms of S₄ at lagging-leg at 20% and 100% loads are provided in Figure 10c,d. S₄ is also turned on under zero voltage for both 20% and 100% loads. The other switches at leading-leg and lagging-leg have the same turn-on characteristics as S₁ and S₄, respectively. The measured results shown in Figure 5, Figure 6, Figure 7, Figure 8, Figure 9 and Figure 10 of the proposed hybrid converter and theoretical waveform analysis are agreed each other. Figure 11a provides the picture of a laboratory prototype. Figure 11b gives the measured efficiencies of the proposed converter and the full bridge LLC converter in reference (Lin, 2018) at 750 V input and different load conditions. The nominal rated power of the studied circuit is 1680 W and the measured circuit efficiency at 750 V input is 93.1%.

6. Conclusions

This paper presents a PWM circuit topology to achieve a low voltage rating on active devices, wide soft switching load range and low freewheeling current compared to the conventional phase-shift PWM converter. Two series-connected phase-shift PWM circuits are used at input-side so that the voltage rating of active devices is reduced. One balance capacitor is used to accomplish voltage balance issue for two input split capacitors. LLC circuit shares the lagging-leg switches of phase-shift PWM circuit so that the ZVS operation capability of lagging-leg switches is improved. Magnetic coupling elements are used to achieve current-sharing issue between two phase-shift PWM circuits. Snubber circuit is employed on the output-side of phase-shift PWM circuit to improve the freewheeling problem at the circulating state. The feasibility and performance of the presented circuit are verified by a laboratory prototype with 1.68 kW rated power.