1. Introduction
In several modern power electronic systems, a transformer is one of the most critical devices serving as voltage scaling up/down, electrical isolation, and power transmission. One of the typical topologies of the power electronic system with transformers commonly used in power distribution and transportation fields is shown in
Figure 1 [
1]. Connected with power electronic switches on both sides, these transformers are working under voltage with magnitude from several to tens of kV, while the frequency is in the range from hundreds of Hz to tens of kHz (depending on the electrical capability of modern IGBT and MOSFET). Because of their working conditions characteristics, these transformers are called medium voltage medium frequency (MVMF) transformers. Compared with a conventional transformer working under 50/60 Hz sinusoidal voltages in an HV power delivery system, an MVMF transformer has quite a different overall layout with a smaller size. Combined with power electronic switches, these transformers also have higher controllability than the conventional ones [
2]. So, they are widely used in modern power electronic applications, such as railway traction, DC grids, etc. Recently, MVMF transformers have further reduced size to reach lower costs and higher power densities. However, along with the development of MVMF transformers, challenges exist such as increased hysteresis loss and conductor loss due to higher working frequency. These factors can lead the transformer to overheating. Additionally, another important challenge is related to insulation reliability, since the MVMF transformer may be faced with fast insulation degradation due to electrical overstress [
3].
The waveform of the voltage applied to the MVMF transformer is the medium-frequency PWM pulse. It has a much shorter rise time compared with the sinusoidal voltage. So, the electrical stress faced by the transformer’s insulation system would be different from that of traditional transformers working under power frequency sinusoidal voltages. Previous research on inverter-fed motors shows that when pulse voltage with short rise time is added to the multi-turn winding, oscillation on the rising edge of the voltage between turns can be induced. As a result, a transient voltage with a much higher peak value than the static voltage drop between turns is reached [
4]. What is more, the voltage distribution among turns is uneven. Usually, the turns closest to the voltage source output terminals would suffer from the highest peak voltage values [
5]. Since transformers also have multi-turn windings, when working in MVMF power electronic conditions, the similar phenomenon of interturn overvoltage and uneven voltage distribution may also exist. If so, the probability of partial discharge (PD) occurrence in the interturn insulation of the transformer would be higher [
6]. Continuous PD can degrade the insulation material quickly and greatly shorten the time-to-failure of the transformer in MVMF application [
7]. When PD is combined with temperature rise due to increased hysteresis loss and conductor loss, the insulation aging rate may be even faster [
6]. As MVMF transformers are developing to be smaller in size, which means the insulation distance may also be reduced inevitably, insulation issues caused by unusual electrical stress would probably be more serious. In addition, for transformers with multi-layer windings, not only the interturn insulation, but also the interlayer insulation may suffer from electrical overstress brought from the pulse operating voltage. Therefore, research on the insulation problems of the MVMF transformers is also necessary.
Some researchers have already investigated the electrical stress on the MVMF transformers and take strategies to deal with it. In [
8], the author conducts an FEM electric field simulation and finds that the electrical field concentrates mostly in one side of the turns of HV winding that is facing the LV winding. Zheng in [
9], proposes a segmented winding structure to reduce the largest interlayer voltage in an MVMF transformer’s winding. Authors in [
10] find that adding an angle ring and electrostatic ring within the transformer’s structure can reduce the value of peak electric field intensity. For the design of MVMF transformers in [
11,
12], authors apply extra semi-conductive layers on the surface of the winding insulation. Electric field simulation shows that this method can effectively reduce the electric field intensity in air gaps between winding and core. Although this research can surely be advantageous to the improvement of insulation capabilities of MFMV transformers, they mostly focus on the steady-state electric field/voltage simulation. As mentioned before, the most obvious difference between MVMF and conventional transformers with respect to the insulation problem is the transient overvoltage and uneven voltage distribution that may happen within the MVMF transformer’s winding when working under pulse voltage with a short rise time. Steady-state simulation ignores the transient response in the MVMF transformer’s winding when exposed to pulse voltage with very short rise time and frequency much higher than the power frequency. Consequently, the maximum electrical field magnitude applied to the winding insulation is underestimated.
Yet, some previous research on the electrical stress of inverter-fed motors provides good suggestions regarding the way of studying the electrical stress of MVMF transformers working under similar electrical condition, since they pay a lot of attention to transient voltage drop within the winding. In [
13], Wan conducts an FEM calculation to obtain stray parameters of a motor prototype’s winding and builds an equivalent circuit model of the winding. Based on that, interturn voltage drop simulation under pulse voltage is conducted. Results show that the overshoot of the voltage drop on the first turn is higher than that on other turns, which means voltage distribution within the winding is uneven. In [
14], Wen conducts interturn voltage simulation similar to that of Wan’s and finds that reducing the capacitance to ground of the turns can decrease the peak interturn voltage value. Krings analyzes inter-coil (consists of several turns) voltage waveform of an HV motor working under PWM voltage [
15]. He discovers that the voltage drop between the first two coils is usually the highest and increasing the rise time of pulse voltage makes the voltage between different adjacent coils distribute more evenly. The experiment results on a real prototype are in high accordance with that of simulation. Moghadam conducts experiments on interturn voltage within a single coil of a motor under different electrical parameters [
16]. The author finds that besides shorter rise time, the longer pulse width can also bring a stronger interturn voltage drop, leading to a more serious electrical stress on the coil’s insulation.
Table 1 summarizes the comparison among the reviewed studies and this paper with respect to contributions and inadequacies from the perspective of MVMF transformer.
Considering that the winding structure of the transformer is not the same as that of the motor, conclusions from the studies on electrical stress of inverter-fed motors cannot be directly used for that of MVMF transformers. Although, in decades before, studies have been conducted focusing on surge distribution in power frequency transformers [
17,
18], the electrical stress brought from repetitive PWM voltage may not be the same as these single pulses. Besides, the MVMF transformer is different from conventional power transformers with respect to the size and layout of windings and cores, when added with similar pulse voltage, the electrical stress may also show different characteristics. Therefore, investigation on electrical stress suffered by MVMF transformers through transient voltage analysis is necessary.
Aiming at investigating the transient maximum electrical stress of MVMF transformer that is not covered by previous papers and combined with the advanced methods from the studies on inverter-fed motors, this article builds an equivalent circuit model of a transformer’ HV winding through software Ansys Q3D and MATLAB. Based on that, a simulation on the electrical stress in the winding is conducted. The results confirm the existence of interturn and interlayer overvoltage. Mechanism of the occurrence of interturn/layer overvoltage and the factors that can influence it are analyzed. According to the mechanism, measures to improve the insulation capability of an MVMF transformer can be proposed.
4. Analysis on the Mechanism of Overvoltage
With the FEM calculation by Ansys Q3D discussed in the last section, stray parameters of the winding are obtained. These parameters include resistance and self-inductance of each turn along with mutual (interturn/layer) capacitances and mutual inductances between different turns (expressed as Rx, Lx, Cx-y, and Mx-y, respectively, x and y vary from 1 to 120). Based on that, an equivalent circuit model of the transformer’s HV winding is constructed in MATLAB’s module Simulink, shown in
Figure 5. Value ranges of the stray parameters are listed in
Table 3, where R, L, and C in the table refer to RX, LX, and Cx-y in
Figure 5, respectively. A voltage source that can generate pulse voltage with adjustable magnitude, frequency, and rise time is connected between the first turn and the last turn of the winding’s circuit model. Set the pulse voltage’s peak-to-peak value and frequency as 1500 V and 1 kHz, respectively, and the rise time as 100 ns, the first simulation is conducted. During this simulation, the interturn voltage drops within the first six turns are recorded (expressed as V1–2, V2–3, V3–4, V4–5, and V5–6, respectively). Typical waveforms of these interturn voltage drops in a half period are shown in
Figure 6. It is clear that strong oscillations exist on the rising edge of the pulse voltage. This oscillation lasts for more than 30 μs and leads to a peak voltage value above 22 V, which is much higher than the static voltage value (around 4.7 V). To understand why this overvoltage would happen and which factors can bring influence on it, analysis is needed.
Since the model in
Figure 5 is a very complex model with 120 turns and three layers, analyzing the mechanism of occurrence of overvoltage through this complete model would be very complicated. Yet, in this transformer prototype, interturn insulation distance (0.6 mm) is shorter than interlayer insulation distance (1 mm). So, interturn capacitance is larger than the interlayer capacitance and would play a more important role in affecting the transient interturn voltage. Therefore, to reduce the complexity of the overvoltage mechanism analysis, we simplify this model into a single-layer winding with (
n + 1) turns, in which the interlayer capacitances are ignored. This simplified circuit model can be seen in
Figure 7. R, L, and C values of each turn are regarded as the same, and the mutual inductance is ignored to reduce the complexity of the following calculation on the output voltage. Then, we conduct Laplace transformation for the impedance in this circuit. Impedance Z
i+1,i+2 (0 < I ≤
n) between adjacent points (point 1 and 2, 2 and 3,…N + 1 and N + 2) can be expressed by (3).
To find why pulse voltage can generate overvoltage between turns, the relationship between the input pulse voltage
Vin and interturn output voltage should be expressed. We regard the voltage drop on the (
n + 1)th turn as the output voltage
Vout; then, the transfer function between
Vin and
Vout is obtained through (4). Through factorization, (4) can be simplified into (5). In this equation,
n + 1 means the total number of turns.
Then, we can change the circuit model in
Figure 7 into an open-loop system shown in
Figure 8. Considering that the pulse voltage generated from the practical voltage source is not an ideal step voltage, rise time surely exists. So, the input voltage should be expressed with the combination of a step function and a first-order inertia link 1/(
Ts + 1) in Function 1 according to the principle of automatic control [
23], where T is the time constant, and the rise time equals 2.2 T. Function 2 is a typical two-order system. With these transfer functions in
Figure 8, we would be able to analyze the mechanism of the overvoltage and factors that can influence it quantitatively based on the theory of automatic control. Considering the value ranges of R, L, and C obtained from the FEM calculation in
Table 3, poles of Function 2 are certainly in the form of A ± jB (both A, B < 0). So, the waveform of interturn voltage drop is a pulse voltage with damping oscillation on its rising edge as seen in
Figure 6, which is similar to that from previous research on the inverter-fed motors [
4]. From function 2, natural frequency ω
n and damping ratio
ξ can be expressed by (6).
We can see that increasing the values of
R and
C can lead to a higher damping ratio, so the oscillation is supposed to be weaker, while increasing the value of
L can reduce the damping ratio, giving rise to a stronger oscillation. To prove this deduction, we conducted the simulation with the simplified circuit in
Figure 7 to see the changing of the overshoot with the changing of the abovementioned parameters. During the simulation, the value of
n in (5) was set to 1 to reduce the simulation time; then, the model in
Figure 7 changed into the simplest winding with only two turns. The simulation parameters and the obtained overshoot of the
Vout are shown in
Table 4. Set the transient peak voltage value as
Vpeak and static voltage value as
Vstatic; then, overshoot σ is obtained through (7).
Values of the parameters in Group A are in accordance with the value ranges of stray parameters of turns of the transformer model from FEM calculation (listed in
Table 3). The other three groups in
Table 4 are applied for the comparison of the overshoot under different
L,
R, and
C values. The rise time of the pulse voltage is set to be 20 ns and the peak voltage as 1 V. Comparing the results of group A with groups B and C, we can see that increasing the value of L can lead to a higher overshoot, while a larger R can reduce the overshoot, which is in accordance with the change in damping ratio. However, the comparison between group A and group D shows that larger capacitance gives rise to a larger overshoot even though the damping ratio of Function 2 is higher. This phenomenon is attributed to the decreasing of natural frequency ω
n with an increasing C shown in (6).
The natural frequency ω
n in Function 2 (expressed in (6)) corresponds to the resonant frequency of the circuit. As described in
Section 3.2, the pulse voltage has a large content of high-frequency components, of which the highest frequency
fu is calculated approximately in (2). When a circuit is added with pulse voltage, these high frequency components can induce resonance on the output voltage, which is one of the important reasons why the overshoot exists. Considering the values of
L and
C and rise time t
r in this circumstance, ω
n is much larger (approximately 894 MHz) than
fu (approximately 15.9 MHz). So, if the
C is kept constant, reducing the rise time can make the
fu higher and closer to ω
n. Consequently, stronger resonance is induced. Correspondingly, when keeping the rise time unchanged, a higher value of
C reduces the ω
n and makes it closer to
fu. Both these two changes can make the overshoot of the output voltage higher. Keeping other parameters the same as that of Group A in
Table 4, we repeat the simulation by increasing the capacitance
C continuously, and the overshoot with the changing of
C can be seen in
Figure 9. The curve of the overshoot can be divided into two regions. In region 1, the decreasing of natural frequency ω
n with an increasing
C plays the dominant role in the changing of the overshoot, leading to a stronger resonant oscillation. Meanwhile, the damping ratio
ξ also keeps increasing, and its effect on suppressing the oscillation becomes stronger. So, when C reaches nearly 80,000 pF, the curve meets a saturation. In region 2, where
C is higher than 80,000 pF, the increasing
ξ due to increasing
C plays the dominant role in changing the overshoot, leading to a weaker oscillation. In the practical situation of a transformer, the interturn capacitance can never be so large as to reach more than 80,000 pF. So, we can draw the conclusion that the interturn voltage overshoot is supposed to increase with the increase in interturn capacitance.
For different values of
C, the overshoot of the output voltage in
Figure 7 (
n = 1) under different rise times are shown in
Figure 10 (
R and
L values are kept as the same as that in Group A of
Table 4). We can see, with the decreasing rise time, overshoot increases at first and, then, converges to a stable value. The reason is that for a rise time short enough, the frequency of the high-order harmonics of the pulse voltage can cover the ω
n, which means the strongest resonance is already induced, and further reducing the rise time would not bring much difference. We take the value of the rise time as a critical value with which the overshoot ceases to increase obviously with further reduction in the rise time. We can see that a higher capacitance leads to a larger critical rise time. The reason is that a higher capacitance can reduce the resonant (natural) frequency ω
n expressed in (6). Then,
fu comes closer to ω
n if the rise time does not change, and strong resonance is more easily triggered. Correspondingly, if the rise time reduces (from 100 ns and follows the curve displayed in
Figure 10), a relatively longer rise time can already make the frequency of high-order harmonics cover the ω
n to trigger the strongest resonance. This result confirms the explanation for the mechanism of how stray capacitance and rise time influence the overshoot on the voltage drop between different turns.
The above analysis of the influence of stray capacitance and the pulse voltage rise time on the overvoltage is based on the most simplified one-layer two-turns model. Whether it is suitable for predicting the electrical stress in the complicated three-layer 120-turns model built for the selected practical transformer in
Figure 5 needs verification. This will be discussed in the following section.