Design of PV MVDC Converter with Wide Output Voltage Range for Series DC System

Abstract

This paper presents a topology of PV MVDC converter with wide output voltage range for a series DC system and its control strategy. In the series DC system, the PV MVDC converters are input-independent, and their outputs are series-connected. A high-level system voltage is achieved for power collection and transmission. This series boost system is flexible and very suitable for decentralized renewable energy application. A modular topology is present for the MVDC converter to improve its applicability. A reconfigurable topology and its modulation method are proposed for the module of the converter. By regulating of duty cycle of switches, the module can be reconfigured to step-up or step-down mode. The operating principles and theoretical derivations of the reconfigurable topology are discussed in detail in this paper. Multimode control strategy for the converter is designed to adapt to complex operation conditions in a series DC system. With the proposed topology and control strategy, the series-connected PV MVDC converter achieves wide input and output voltage range to adapt to the operating characteristics of the series DC system; 3 kV/80 kW DC–DC module and 20 kV/500 kW PV MVDC converter are developed and operating stably in practice. The operation results are presented in the paper.

1. Introduction

PV systems are developed rapidly all over the world. The scale of PV power plants is constantly expanding. In 2015, the largest capacity of PV power plants in China was 20 MW, and in 2019 it has reached 2 GW. However, many bulk PV power plants are built in remote places that are at the end of the grid, and electricity delivery is a huge challenge. The PV MVDC system is a novel solution for power collection and transmission in bulk PV plants. Compared with the traditional AC collection system, the PV DC collection system has fewer conversion links, no reactive power loss, and lower transmission line costs [1,2,3]. The cost of the system is distinctly reduced, and the efficiency is improved.

Parallel and series are two basic PV MVDC system structures. Figure 1 shows the structure of series PV MVDC system. Different PV units are connected in series at their MVDC ports. The distributed series DC system is suitable for renewable energy system. The main advantages of the series system include the following. (1) Without a second centralized step-up stage, the series PV system could achieve higher level voltage output. (2) Without centralized converters, converters are distributed near the PV array and connected in MVDC ports. Fewer collection cables are needed, and the loss of the system is reduced. In the series system, the broken-down converters will be bypassed. The remaining converters will share the system voltage. As the series number is increased, less additional voltage should be shared if there is a broken-down converter. Individual broken-down converters will not affect system operation.

In the series PV system, as in Figure 1, all the converters conduct a common DC output current, and the output voltage of the converter is determined by the output power ratio of the converter and system, as shown in Equations (1) and (2).

$$V_{coa}=\frac{P_{coa}}{{\sum }_{i=1}^N{P}_{coi}}{V}_s$$

(1)

$$I_s=I_{coi}=\frac{{\sum }_{i=1}^N{P}_{coi}}{V_s}$$

(2)

where $V_{coi}$, $I_{coi},$ and $P_{coi}$ are the output voltage, current, and power of Converter #i, respectively. $V_s$ and $I_s$ are the output voltage and current of the series system, respectively. It can be seen from Equation (1) that different output power of converters will cause uncommon output voltage of the converters. The converters need to have wide range of output voltage to adapt to the operating characteristics of series DC system.

Several studies have addressed series-connected PV DC–DC converters in series LVDC system. Series PV system is applied to overcome mismatch between PV panels. Non-isolated step-up converter is employed in practical application. The voltage of the converter is below 100 V; the voltage ratio is less than 2 [4,5,6,7,8]. The voltage of the series system is less than 1000 V.

Unlike the LVDC system, the converters for the MVDC system should have isolated structure for safety. With ultra-wide voltage range from 0 to dozens of kilovolts, the converter voltage gain should be various between 0 to hundreds in the series MVDC system.

DAB is widely used as a DC–DC module in the DC transformer. However, it is suitable for the application with a fixed voltage gain [9]. The control methods of extended-phase-shift (EPS) and dual-phase-shift (DPS) are proposed in [10,11] to widen the operating range of DAB. A high-frequency-link DC–DC converter based on a modular multilevel converter is proposed in [12,13]. This topology is fit for MVDC and HVDC application. However, the voltage of these topologies is stepped up only by transformer, and the boosting capacity is limited.

An isolated buck–boost converter can operate in buck and boost mode to widen the output voltage range. A lot of efforts have been made to increase the output voltage of the buck–boost converter. An isolated buck–boost converter based on semiactive rectifier is proposed in [14,15,16,17]. Buck and boost modes are achieved to widen the voltage range. A three-level isolated buck–boost converter with clamped inductor is proposed in [18]. With five variable voltage levels in the primary side, output voltage range is further wider. The boost mode is achieved by semiactive rectifier in the high voltage side in both [14,15,16,17,18]. A buck and DAB cascade to form a buck–boost topology in [19,20]. By coordinated control of buck and DAB, buck and boost modes can be achieved. A switched-capacitor-based submodule and a DAB cascade to form a buck–boost in [21]. The proper HFL (high frequency link) voltage buck–boost adaptive matching switching strategy is developed. However, the two stages cascade structure decreases the efficiency in [19,20,21]. Step-up and step-down modes are achieved by coordinated control of active switches of the primary and secondary side in these existing buck–boost converters. The voltage stress of active switches limits the output voltage rating of the converter; high voltage output is difficult to be realized. Additionally, the driver and controller for active switches in high voltage side will dramatically increase the complexity and cost of the converters.

Aiming for PV series MVDC converter application, an isolated buck–boost topology is proposed, and the modulation method is developed in this paper. By adjusting the duty cycle, the step-up mode and step-down mode can be shifted easily. By only employing diodes in the high voltage side of the transformer, the output voltage of modules can be up to 10 kV. Only controller and switch drives are needed in the low voltage side of transformer to simplify the control system. Therefore, a wide range of voltage gain and high output voltage can be obtained. Based on the proposed topology, a PV MVDC converter with IPOS structure for series DC system is developed. Multimode control strategy for the converter is designed to adapt to complex operation conditions in the series DC system.

This paper analyzes the principle, modulation method, and soft switching realization conditions of the reconfigurable DC–DC topology. Topology and control strategy of the PV MVDC converter based on the DC module are also proposed; 3 kV/80 kW DC–DC modules and 20 kV/500 kW series-connected PV MVDC converters were developed, and laboratory tests result were analyzed in the paper.

2. Principle of the Converter

2.1. Topology of Series-Connected PV MVDC Converter

The proposed topology of the converter is shown in Figure 2. In order to achieve high output voltage at MVDC level and high voltage gain, IPOS structure is applied in the converter.

An isolated reconfigurable DC–DC topology is proposed for the modules. By adjusting the duty cycle of the module and the number of operation modules, the converter achieves wide input and output voltage range.

2.2. Proposed Reconfigurable DC–DC Topology for Module

The proposed isolated reconfigurable DC–DC topology is shown in Figure 3. $L_{lk}$ is the leakage inductor of the transformer. By adjusting the duty cycle of switches $Q_0~Q_4$ in the primary side, the topology can be reconfigured to achieve step-up mode and step-down mode. Only diodes are involved in the secondary side; high voltage output can be achieved by employing high voltage silicon rectifier stack.

A modulation method is proposed to realize the two modes. The duty cycle of the lower arm switches $Q_2$ and $Q_4$ is fixed to half of the switching cycle. The duty cycle of upper arm switches $Q_1$ and $Q_3$ is the same and denoted as D. The phase between the two bridge arms is 180 degrees. The result of NAND of switching sequence of $Q_1$ and $Q_3$ is used as the switching sequence of clamp switch $Q_0$. By adjusting the duty cycle D, step-up and step-down modes can be achieved.

When the duty cycle D is less than 0.5, the circuit operates in step-down mode. The voltage of clamping capacitor $V_{c2}$ is lower than input voltage $V_{in}$; $D_0$ conducts and $L_{in}$ is bypassed. When the duty cycle D is greater than 0.5, the circuit operates in step-up mode. The voltage of clamping capacitor $V_{c2}$ is higher than input voltage $V_{in}$; $D_0$ is cut off and $L_{in}$ works.

The wide range of input, output voltage, and voltage gain is achieved, and it enables the topology to adapt to the variable operating conditions in the series system. Zero voltage start-up could be realized through step-down mode without pre-charging. Module cutting in online in IPOS can also be realized.

3. Principle and Theoretical Derivation of the Reconfigurable DC–DC Topology

3.1. Principle of the Reconfigurable Topology

3.1.1. Principle of Step-Up Mode

In step-up mode, it can be divided into step-up continuous mode (step-up-CCM) and step-up discontinuous mode (step-up-DCM) according to if the input inductor current $i_{Lin}$ is continuous. Step-up-CCM mode is divided into step-up-CCM1 mode and step-up-CCM2 mode according to if the leakage current of the transformer is continuous. Figure 4 is the switching sequence diagram in step-up-CCM mode.

In Figure 4, $T_s$ is the switching cycle of the switches $Q_0$~$Q_4$. $L_{in}$ is the input inductor. $i_{Lin}$ and $v_{Lin}$ are the voltage and current of $L_{in}$. $L_{Llk}$ is the leakage inductor. $i_{Llk}$ and $v_{Llk}$ are the voltage and current of $L_{lk}$. N is the transformer turn ratio.

Figure 5 shows the circuit flow paths in step-up-CCM1 mode. Each switching cycle contains eight operating modes.

Stage 1 $[t_0-t_1$]: Switches $Q_0$, $Q_2,$ and $Q_3$ are turned on. The input voltage $V_{in}$ is lower than the clamping capacitor voltage $V_{C2}$. The input diode $D_0$ is off. $v_{Lin}$ is equal to $V_{in}-V_{C2}$ and $i_{Lin}$ decreases. $v_{Llk}$ is equal to $-(V_{C2}-V_o/N$), and $i_{Llk}$ increases in the negative direction. The diodes $D_2$ and $D_3$ conduct.

Stage 2 [$t_1-t_2$]: At $t_1$, the switch $Q_2$ is turned on, and $Q_0$ is turned off. The voltage of the input inductor $L_{in}$ is equal to $V_{in}$, current flows through $Q_1$ and $Q_2$, and $i_{Lin}$ increases positively. The leakage inductor voltage is equal to $V_o/N$, and $i_{Llk}$ decreases in the negative direction.

Stage 3 [$t_2-t_3$]: At $t_2$, $Q_2$ is turned off, and $Q_4$ is turned on. Current flows through $Q_3$ and $Q_4,$ and $i_{Lin}$ continues to increase. The leakage inductor voltage $v_{Llk}$ is equal to $V_o/N$, and $i_{Llk}$ decreases in the negative direction.

Stage 4 [$t_3-t_4$]: At $t_3$, $Q_3$ is turned off. The clamping switch $Q_0$ is turned on, clamping the voltage of $Q_2$ and $Q_3$. $v_{Lin}$ is equal to $V_{in}-V_{C2}$, and $i_{Lin}$ decreases. $v_{Llk}$ is equal to $V_{C2}+V_o/N$, and $i_{Llk}$ decreases in the negative direction.

Stage 5 [$t_4-t_5$], stage 6 [$t_5-t_6$], stage 7 [$t_6-t_7$], and stage 8 [$t_7-t_8$] are similar to stage 1~4.

In step-up-CCM2 mode as shown in Figure 4b, the leakage inductor withstands the positive voltage and the leakage inductor current decreases to 0 in Stage 2. The voltage and current of leakage inductor in Stage 3 and 4 are both 0.

In step-up-DCM mode, $i_{Lin}$ decreases to 0 in Stage 1 and 4, and the inductor voltage is 0. The other stages are the same as the step-up-CCM mode.

3.1.2. Principle of Step-Down Mode

According to the operating state of the leakage inductor current $i_{Llk}$, it can be divided into three modes: continuous mode step-down-CCM and discontinuous modes step-down-DCM1 and step-down-DCM2. The operating conditions of the three modes are described in detail later. Figure 6 and Figure 7 are the switching sequence diagram and equivalent circuit diagram in step-down mode, respectively. In the step-down mode, the conduction time of $Q_1$ and $Q_3$ is less than 0.5$T_s$. $Q_0$ is always turned on in step-down mode. The input diode $D_0$ always conducts. Each switching cycle contains eight operating modes.

Figure 7 shows the circuit flow paths in step-down-CCM mode. Each switching cycle contains eight operating modes.

Stage1 $[t_0-t_1$]: At $t_0$, $Q_1$ and $Q_4$ are turned on. $v_{Llk}$ is equal to $V_{C2}+V_o/N$, and $i_{Llk}$ decreases in negative direction. The high-voltage side of the transformer is subjected to negative voltage, and the diodes $D_2$ and $D_3$ conduct.

Stage2 [$t_1-t_2$]: At $t_1$, $i_{Llk}$ decreases to 0 and then increases in the positive direction. $v_{Llk}$ is equal to $V_{C2}-V_o/N$, and $i_{Llk}$ decreases in the positive direction. The high voltage side of the transformer is subjected to positive voltage, and the diodes $D_1$ and $D_4$ conduct.

Stage3 [$t_2-t_3$]: At $t_2$, $Q_1$ is turned off. $i_{Llk}$ continues to flow through the freewheeling diodes of $Q_2$ and $Q_4$, $v_{Llk}$ is equal to $-V_o/N$, and $i_{Llk}$ decreases in the positive direction. The high voltage side of the transformer is subjected to positive voltage, and the diodes $D_1$ and $D_4$ conduct.

Stage4 [$t_3-t_4$]: $Q_4$ is turned off; $Q_2$ is turned on. $i_{Llk}$ feeds the input capacitor through the anti-parallel diodes of $Q_2$ and $Q_3$. $v_{Llk}$ is equal to $-\left(V_{C2}+V_o/N\right)$, and $i_{Llk}$ decreases in the positive direction. The high voltage side of the transformer is subjected to positive voltage, and the diodes $D_1$ and $D_4$ conduct.

Stage5 [$t_4-t_5$], Stage6 [$t_5-t_6$], Stage7 [$t_6-t_7$], and Stage8 [$t_7-t_8$] are similar to stage 1–4.

In step-down-DCM1 mode, $v_{Llk}$ in Stage1 and Stage2 is $V_{C2}-V_o/N$. $i_{Llk}$ increases in positive direction. In Stage4, $i_{Llk}$ is reduced to 0 and $v_{Llk}$ is 0, as shown in Figure 6b. In step-down DCM2 mode, $i_{Llk}$ is decreased to 0 in Stage3, as shown in Figure 6c.

3.2. Theoretical Derivation of Topology

In order to deeply understand the operating characteristics of the reconfigurable topology and relationship between different modes, the theoretical derivation of voltage gain in step-up and step-down is carried out, and the transition boundary conditions between the modes is also discussed.

3.2.1. Derivation of Step-Down Mode

In step-down-CCM mode, leakage current is continuous. Volt–second balance according to the leakage inductor $L_{lk}$ in Figure 3 can be obtained:

$$\frac{1}{4}{V}_o\left(1-2D\right)+(V_o+N{V}_{in})\left(\frac{1}{4}-\frac{1}{2}D+D_{Llk0}\right)=\left(N{V}_{in}-V_o\right)\left(D-D_{Llk0}\right)$$

(3)

where $D_{Llk0}$ is shown in Figure 6a and described as:

$$D_{Llk0}=\frac{\left(6D-1\right)N{V}_{in}-2 V_o}{8N{V}_{in}}$$

(4)

The output current $I_o$ can be obtained as:

$$\begin{array}{c}{I}_o=\frac{V_o}{R}=\frac{V_o+N{V}_{in}}{N^2{L}_{lk}{f}_s}{\left(\frac{1}{2}-\frac{1}{4}D+D_{Llk0}\right)}^2+\frac{\left(N{V}_{in}-V_o\right){\left(D-D_{Llk0}\right)}^2}{N^2{L}_{lk}{f}_s}+[\frac{N{V}_{in}}{N^2{L}_{lk}{f}_s}\left(\frac{3}{4}D+\frac{1}{2}\right)\\ +\frac{V_o}{N^2{L}_{lk}{f}_S}\left(\frac{1}{2}-\frac{5}{4}D+2D_{Llk0}\right)]\left(\frac{1}{4}-\frac{D}{2}\right)\end{array}$$

(5)

where $f_s$ is the switching frequency.

The voltage gain in step-down-CCM mode $M_{step-down-CCM}$ can be expressed as:

$$M_{step-down-CCM}=\frac{V_o}{V_{in}}=-2K_{Llk}N+\frac{N\sqrt{{\left(4K_{Llk}\right)}^2-\left(4D^2-4D-3\right)}}{2}$$

(6)

where $K_{Llk}=2N^2{L}_{lk1}{f}_S/R$.

In step-down-DCM1 mode, the derivation method is similar with step-down-CCM. The output current can be expressed as:

$$I_o=\frac{V_o}{R}=D\frac{ND{V}_{in}-D{V}_o}{N^2{L}_{lk}{f}_s}+\frac{8ND{V}_{in}-\left(6D+1\right)V_o}{16N^2{L}_{lk}{f}_s}\left(1-2D\right)+\frac{4N{V}_{in}D-2V_{o}D-U_o}{4N^2{L}_{lk}{f}_s}\frac{4N{V}_{in}D-2V_{o}D-U_o}{4\left(V_o+N{V}_{in}\right)}$$

(7)

The voltage gain in step-down-DCM1 mode $M_{step-down-DCM1}$ can be expressed as:

$$\begin{array}{c}{M}_{step-down{-}_{DCM1}}=\frac{V_o}{V_{in}}=\frac{N\sqrt{{\left(8K_{Llk}+1+4D+20D^2\right)}^2+256K_{Llk}\left(D+2D^2\right)}}{16K_{Llk}}\\ -\frac{N\left(8K_{Llk}+1+4D+20D^2\right)}{16K_{Llk}}\end{array}$$

(8)

In the step-down-DCM2 mode, the output current can be expressed as:

$$I_o=\frac{V_o}{R}=\frac{N{V}_{in}-V_o}{N^2{L}_{lk}{f}_s}D\left(\frac{1}{2}-D_{Llk2}\right)$$

(9)

The voltage gain in step-down-DCM2 mode $M_{step-down-DCM2}$ can be expressed as:

$$M_{step-down-DCM2}=\frac{2ND}{\sqrt{D^2+2K_{Llk}}+D}$$

(10)

On the boundary of step-down-CCM mode and step-down-DCM mode, the volt–second balance based on leakage inductor has the following relationship:

$$\frac{\left(N{V}_{in}-V_o\right)D}{N}=\frac{V_o+N{V}_{in}}{4N}\left(1-2D\right)+\frac{V_o\left(1-2D\right)}{4N}$$

(11)

The output current $I_o$ can be obtained as:

$$I_o=\frac{V_o}{R}=\frac{(12D^2-8D+1)V_o+\left(1-4D^2\right)N{V}_{in}}{16L_{lk}{f}_s{N}^2}+\frac{V_o+N{V}_{in}}{16L_{lk}{f}_s{N}^2}{\left(1-2D\right)}^2+\frac{\left(N{V}_{in}-V_o\right)D^2}{L_{lk}{f}_s{N}^2}$$

(12)

The critical condition between step-down-CCM and step-down-DCM can be expressed as:

$$K_{Llk}=\frac{2L_{lk}{f}_s{N}^2}{R}$$

(13)

$$K_{step-down-crit1}=\frac{\left(-20D^2+8D+1\right)}{4\left(6D-1\right)}$$

(14)

The operation condition $K_{Llk}\ge K_{step-down-crit1}$ corresponds to step-down-CCM mode. The operation condition $K_{Llk}<K_{step-down-crit1}$ corresponds to step-down-DCM mode, as shown in Figure 8.

On the boundary of step-down-DCM1 mode and step-down-DCM2 mode, the volt–second balance based on leakage inductor has the following relationship:

$$\frac{\left(N{V}_{in}-V_o\right)D}{N}=\frac{V_o\left(1-2D\right)}{4N}$$

(15)

The critical condition between step-down-DCM1 and step-down-DCM2 can be expressed as:

$$K_{Llk}=\frac{2N^2{L}_{lk}{f}_S}{R}$$

(16)

$$K_{step-down-crit2}=\frac{1-4D^2}{8}$$

(17)

The operation condition $K_{Llk}\ge K_{step-down-crit2}$ corresponds to step-down-DCM1 mode; the operation condition $K_{Llk}<K_{step-down-crit2}$ corresponds to step-down-DCM2, as shown in Figure 9.

3.2.2. Derivation of Step-Up Mode

In step-up-CCM1 mode, the input inductor volt–second balance can be obtained:

$$\left(V_{C2}-V_{in}\right)\left(1-D\right)=V_{in}\left(D-\frac{1}{2}\right)$$

(18)

The relationship between $V_{in}$ and $V_{C2}$ can be expressed as:

$$\frac{V_{C2}}{V_{in}}=\frac{1}{2\left(1-D\right)}$$

(19)

In the step-up-CCM1 mode, the leakage inductor current is continuous; the relationship between $V_o$ and $V_{C2}$ can be obtained by Equation (5):

$$\frac{V_o}{V_{C2}}=\frac{-\left(1-4D^2+4K_{Llk}\right)N}{4\left(1-D\right)}+\frac{N\sqrt{{\left(1-4D^2+4K_{Llk}\right)}^2+16{\left(1-D\right)}^2}}{4\left(1-D\right)}$$

(20)

The voltage gain in step-up-CCM1 mode $M_{step-up-CCM1}$ can be expressed as:

$$M_{step-up-CCM1}=\frac{V_o}{V_{in}}=\frac{V_{C2}}{V_{in}}\times \frac{V_o}{V_{C2}}$$

(21)

$$M_{step-up-CCM1}=\frac{V_o}{V_{in}}=\frac{-\left(1-4D^2+4K_{Llk}\right)N}{8{\left(1-D\right)}^2}+\frac{N\sqrt{{\left(1-4D^2+4K_{Llk}\right)}^2+16{\left(1-D\right)}^2}}{8{\left(1-D\right)}^2}$$

(22)

In the step-up-CCM2 mode, the voltage gain in step-up-CCM2 mode $M_{step-up-CCM2}$ can be expressed as:

$$M_{step-up-CCM2}=\frac{N}{\sqrt{{\left(1-D\right)}^2+4K_{Llk}}+\left(1-D\right)}$$

(23)

In step-up-DCM1 mode, the voltage gain $M_{step-up-DCM1}$ can be expressed as:

$$M_{step-up-DCM1}=\frac{A_{CCM}+\sqrt{A_{CCM}{}^2+4D-{0.5}^{2}R/L_{in}{f}_s}}{2}$$

(24)

where

$$A_{CCM}=\frac{-\left(1-4D^2+4K_{Llk}\right)}{4\left(1-D\right)}+\frac{\sqrt{{\left(1-4D^2+4K_{Llk}\right)}^2+16{\left(1-D\right)}^2}}{4\left(1-D\right)}$$

(25)

The voltage gain in step-up-DCM2 mode $M_{step-up-DCM2}$ can be expressed as:

$$M_{step-up-DCM2}=\frac{A_{DCM}+\sqrt{A_{DCM}{}^2+4D-{0.5}^{2}R/L_{in}{f}_s}}{2}$$

(26)

where

$$A_{DCM}=\frac{2N\left(1-D\right)}{\sqrt{{\left(1-D\right)}^2+4K_{Llk}}+\left(1-D\right)}$$

(27)

On the boundary of step-up-CCM mode and step-up-DCM mode, the volt–second balance based on input inductor has the following relationship:

$$L_{in}\frac{{\Delta }{i}_{Lin}}{\left(D-\frac{1}{2}\right)T_s}=V_{in}$$

(28)

$$I_{in}=\frac{1}{2}{\Delta }{i}_{Lin}=\frac{V_o{}^2}{R{V}_{in}}=\frac{V_{in}\left(D-0.5\right)}{2L_{in}{f}_s}$$

(29)

${\Delta }{i}_{Lin}$ is the current difference within $\left(D-1/2\right)T_s$.

The critical condition between step-up-CCM and step-up-DCM can be expressed as:

$$K_{Lin}=\frac{2L_{in}{f}_S{N}^2}{R}$$

(30)

$$K_{Llk}=\frac{2L_{lk}{f}_S{N}^2}{R}$$

(31)

$$K_{step-up-crit}={\left(\sqrt{{\left(1-D\right)}^2+4K_{Llk}}+1-D\right)}^2\left(D-0.5\right)$$

(32)

The operation condition $K_{Lin}\ge K_{step-up-crit}$ corresponds to step-up-CCM mdoe, and the operation condition $K_{Lin}<K_{step-up-crit}$ corresponds to step-up-DCM mode, as shown in Figure 10.

3.2.3. Analysis of Voltage Gain

Figure 11 shows the relationship between voltage gain and duty cycle. When the duty cycle is adjusted between 0 and 1, the reconfigurable DC–DC topology can achieve a smooth continuous change of voltage gain from 0 to the maximum value. Usually, the duty ratio is below 0.8 to achieve satisfied efficiency. In addition to the duty cycle, the voltage gain is also related to $K_{Llk}$. $K_{Llk}$ is described in Formula (31). As $K_{Llk}$ increases, the voltage gain curve becomes flatter. Therefore, reducing $K_{Llk}$, that is, reducing the leakage inductor or increasing the load resistance, helps to increase the voltage gain. In order to widen the range of ZVS, we should increase the value of $K_{Llk}$. In practice, we should consider both the voltage gain requirement and ZVS to select an appropriate value of $K_{Llk}$.

3.3. Analysis of ZVS Condition of the Topology

3.3.1. ZVS of Step-Down Mode

In step-down mode, ZVS of the upper bridge arm switch $Q_3$ can be realized by resonating between the leakage inductor $L_{lk}$ and the junction capacitors of switches $Q_2$ and $Q_3$. The ZVS of the switch $Q_1$ is similar to $Q_3$. In order to realize the ZVS of the switch $Q_3$, the storage energy of leakage inductor at $t_3$ in Figure 6a or $t_2$ in Figure 6b needs to be greater than or equal to the energy stored in the switch $Q_2$ and $Q_3$, which has the following relationship:

$$\frac{1}{2}{L}_{lk}{\left(i_{Llk}\right)}^2\ge \frac{1}{2}(C_{ooQ2}+C_{ooQ3})V_{in}{}^2$$

(33)

$${\omega }_{\sigma }=\sqrt{L_{lk}(C_{ooQ2}+C_{ooQ3})}$$

(34)

where $C_{ooQ2}$ and $C_{ooQ3}$ are the junction capacitors of switches $Q_2$ and $Q_3,$ respectively. ${\omega }_{\sigma }$ is the resonance frequency.

According to Equation (6), ZVS condition can be obtained in the step-down-CCM mode as follows:

$$\begin{array}{c}{K}_{Llk}\ge \frac{\left(3-4D^2+4D\right)}{4\left(2D-1\right)+4\sqrt{4D^2+12D+9-128f_S{\omega }_{\sigma }}}\\ +\frac{\left(1-2D\right)-\sqrt{4D^2+12D+9-128f_S{\omega }_{\sigma }}}{16}\end{array}$$

(35)

$K_{Llk}$ is described in formula (31).

According to Equation (8), ZVS condition can be obtained in the step-down-DCM1 mode as follows:

$$K_{Llk}\ge \frac{4D{\left(2D+1\right)}^2-2\left(1+4D+20D^2\right)\left(D-f_S{\omega }_{\sigma }\right)}{\left(D-f_S{\omega }_{\sigma }\right)\left(D-f_S{\omega }_{\sigma }+16\right)}$$

(36)

In order to realize the ZVS of the switch $Q_2$, the energy stored of leakage inductor at $t_2$ in Figure 6a or $t_1$ in Figure 6b,c needs to be greater than or equal to the energy stored in the switch $Q_2$ and $Q_3$, which has the following relationship:

$$\frac{1}{2}{L}_{lk}{i}_{Llk}{}^2\ge \frac{1}{2}(C_{oos2}+C_{oos3})V_{in}{}^2$$

(37)

$${\omega }_{\sigma }=\sqrt{L_{lk}(C_{ooQ2}+C_{ooQ3})}$$

(38)

The ZVS of the switch $Q_4$ is similar to $Q_2$. ZVS condition of $Q_2$ and $Q_4$ can be obtained in the step-down-CCM mode as follows:

$$\begin{array}{c}{K}_{Llk}\ge \frac{\left(3-4D^2+4D\right)}{4\left(1-2D\right)+4\sqrt{4D^2+12D+9-64f_S{\omega }_{\sigma }}}\\ +\frac{\left(2D-1\right)-\sqrt{4D^2+12D+9-64f_S{\omega }_{\sigma }}}{16}\end{array}$$

(39)

ZVS condition of $Q_2$ and $Q_4$ can be obtained in the step-down-DCM1 mode as follows:

$$K_{Llk}\ge \frac{8\left(D+2D^2\right)-\left(1-\frac{f_S{\omega }_{\sigma }}{D}\right)\left(1+4D+20D^2\right)}{8{\left(1-\frac{f_S{\omega }_{\sigma }}{D}\right)}^2+8\left(1-\frac{f_S{\omega }_{\sigma }}{D}\right)}$$

(40)

ZVS condition of $Q_2$ and $Q_4$ can be obtained in the step-down-DCM2 mode as follows:

$$K_{Llk}\ge \frac{2f_S{\omega }_{\sigma }{D}^2}{{\left(D-f_S{\omega }_{\sigma }\right)}^2}$$

(41)

In the step-down mode, the lower bridge arm switches can realize ZVS in a wide operation area, and the upper bridge arm switches realize ZVS under heavy load.

3.3.2. ZVS of Step-Up Mode

In step-up mode, ZVS can be realized by turning off the switch $Q_0$ in advance. In this process, the leakage inductor $L_{lk}$ is resonated with the junction capacitors $C_{ooQ0}$, $C_{ooQ2}$ and $C_{ooQ3}$ of $Q_0$, $Q_2$, and $Q_3$; ZVS on the upper bridge arm switch $Q_3$ is realized. The ZVS process of the switch $Q_1$ is similar to $Q_3$. The resonance frequency ${\omega }_{\sigma }$ can be expressed as:

$${\omega }_{\sigma }=\sqrt{L_{lk}(C_{ooQ0}+C_{ooQ2}+C_{ooQ3})}$$

(42)

In order to achieve ZVS on the switch $Q_3$, the turn-off time in advance of the clamp switch $Q_0$ is denoted as $t_{\sigma }$. It can be expressed as:

$$t_{\sigma }=\frac{\pi }{2}\sqrt{L_{lk}(C_{ooQ0}+C_{ooQ2}+C_{ooQ3})}$$

(43)

In order to realize ZVS, the stored energy of the leakage inductor needs to be greater than or equal to the energy of the junction capacitance of $Q_0$, $Q_2,$ and $Q_3$, so the following relationship must be satisfied:

$$\frac{1}{2}{L}_{lk}{\left(i_{Llkpk}-I_{Lin}\right)}^2\ge \frac{1}{2}(C_{ooQ0}+C_{ooQ2}+C_{ooQ3})V_{c2}{}^2$$

(44)

$i_{Llkpk}$ is the peak current of leakage inductor.

According to Equation (23), ZVS condition can be obtained in the step-up-CCM2 mode as follow:

$$K_{Llk}\le 4{\left(1-D\right)}^2+8\left(1-D\right)\sqrt{\frac{{\left(1-D\right)}^2}{4}+\frac{2{\left(1-D\right)}^2-2f_s{\omega }_{\sigma }}{\left(1-D\right)R}{N}^2}$$

(45)

The time to turn off the clamp switch in advance can be calculated according to the circuit parameters, which can realize the bridge arm switch ZVS in a wide operation range.

3.4. Design of the Main Circuit Parameters

In order to reduce the current stress on the switches, the input inductor $L_{in}$ should guarantee operating in step-up-CCM mode at rated normal current. The value of inductor $L_{in}$ depends on the current ripple limitation of $i_{Lin}$. ${\alpha }_1$ is defined as current ripple coefficient of $i_{Lin}$. ${\Delta }{i}_{Lin}$ is the peak to peak current ripple in the step-up mode. ${\Delta }{i}_{Lin}$ can be expressed as:

$${\Delta }{i}_{Lin}=\frac{V_{in}\left(2D-1\right)/2}{2f_s{L}_{Lk}}$$

(46)

$$L_{in}\ge \frac{\left(2D-1\right)V_{in}}{4f_s{I}_{in}{\alpha }_1}$$

(47)

The transformer leakage inductor $L_{lk}$ participates in realizing ZVS that has been introduced in Section 3.2.3. In step-up mode, the ZVS condition is described as (45). The formula is sorted out as:

$$L_{lk}\ge \frac{(C_{ooQ0}+C_{ooQ2}+C_{ooQ3})V_{c2}{}^2}{{\left(i_{Llkpk}-I_{Lin}\right)}^2}$$

(48)

$$L_{lk}\ge \frac{(C_{ooQ0}+C_{ooQ2}+C_{ooQ3})V_{in}{}^2}{{\left(i_{Llkpk}-I_{in}\right)}^2{\left(2-2D\right)}^2}$$

(49)

In step-down mode, the ZVS condition is described as (43).

$$\frac{1}{2}{L}_{lk}{\left(i_{Llk}\right)}^2\ge \frac{1}{2}(C_{ooQ2}+C_{ooQ3})V_{in}{}^2$$

(50)

$$L_{lk}\ge (C_{ooQ2}+C_{ooQ3})\frac{V_{in}{}^2}{{\left(i_{Llk}\right)}^2}$$

(51)

The leakage current inductor will be selected from the larger calculation results of step-up and step-down modes. The larger value of leakage inductor will achieve ZVS operation within a wider range load. However, a large leakage inductor will reduce the voltage gain. A compromise value of leakage inductor should be considered.

The application of output capacitors $C_3$ of the modules achieves output voltage decoupling between modules. In order to decrease the ripple of output current, an output inductor will be employed to form LC filter. The output capacitor is the equivalent capacitor of series modules there.

The capacitor $C_2$ is the clamp capacitor in step-up mode. The selection of $C_2$ depends on the voltage ripple of $V_{c2}$. ${\alpha }_2$ is defined as voltage ripple coefficient of $V_{c2}$. ${\Delta }{v}_{c2}$ is voltage ripple in the step-up mode.

$$C_2\ge \frac{\left(1-D\right)I_{Lin}}{2f_s{\Delta }{v}_{c2}}=\frac{\left(1-D\right)I_{Lin}}{2f_s{\alpha }_2{V}_o/n}$$

(52)

In step-down mode, $C_2$ works as a snubber. The value is less than in step-up mode. Therefore, the value of $C_2$ in step-up mode is mainly considered.

3.5. Comparison of the Proposed and Other Isolated Converters

Table 1. Comparison between the proposed converter and other isolated converters.

Topology	[9]	[12]	[14]	[18]	[19]	[21]	Proposed Topology
Number of switches in low voltage side	4	8	4	6	6	8	5
Number of switches in high voltage side	4	8	2	2	4	4	0
Number of diodes	0	0	2	4	0	0	5
Number of inductors	0	0	1	1	1	1	1
Number of capacitors	2	8	5	4	2	6	3
Design cost	Medium	High	Medium	High	High	High	Medium
Efficiency	Medium	Medium	High	Medium	Low	Low	High
Boosting capability	Low	Low	Medium	Medium	Strong	Strong	Strong
Voltage gain	Fixed	Fixed	Wide range	Narrow range	Wide range	Wide range	Wide range
Output voltage	Low	High	Low	Low	Low	Low	High

lists the comparison of the proposed and other isolated converters related to circuit structure and performance. Compare to previous work on isolate buck–boost topology, the merits of the proposed DC–DC topology in MVDC application include: (1) The topology has two modes of step-up and step-down to widen the input and output voltage range. The modulation method in the manuscript realizes automatic switching between two modes, and the voltage gain is continuously adjustable and can be various in a very wide range. (2) In step-up mode, high voltage gain is obtained by not only transformer and but also boost inductor. (3) There are no active switches but only diodes in the high voltage side of the topology, high output voltage up to 10 kV is easy to be obtained in this topology. This could be great helpful to reduce the number of modules and the volume of the converter. (4) Only controller and switch drives are needed in the low voltage side of transformer in the proposed topology to simplify the control system. In the traditional buck–boost converter, the controllers, switch drivers, and auxiliary power supply on the high voltage side should sustain a high voltage of common mode and differential mode. These will increase the complex and reduce the reliability of the converter.

4. Control Strategy of the Converter

In order to adapt to the complex operation condition in series DC system, the output characteristics of the converter are designed as shown in Figure 12. The control strategy system of the converter is shown in Figure 13. With three operating modes of MPPT, constant voltage and constant current, autonomous control of the converters are achieved to satisfied the requirement of the series DC system.

In order to output maximum PV power, the converter will be in MPPT mode. According to Equation (1), if serious mismatch of irradiance between PV units happens, the converter with relative larger power might operate in constant voltage mode to avoid overvoltage. When the grid voltage is lower than the rated voltage due to DC grid fault, as the output current increases to the maximum setting value, the converter operates in constant current mode to avoid overcurrent. In the start-up and shut-down process, the converter will operate in constant voltage mode to prevent overvoltage.

Figure 12 shows the mode shift process of a series system with three converters. When the MPPT power of the PV arrays are equal, the output current is $I_{o1}$, the output voltages of the converters are balanced, and the operating points of the Converter#1, Converter#2, and Converter#3 are A1, B1, and C1 in Figure 12, respectively. The modules of the three converters operate in step-up mode; the converter operates in MPPT mode. When the irradiances of the three PV arrays are seriously mismatched, the output voltages of converters will be unbalanced. In Figure 12, as the irradiance of the No. 1 array drops to a very low level, Converter#1 moves to A2 and still operates in MPPT mode. The irradiance of the No. 2 array drops a little, Converter#2 moves to B2 and operates in MPPT mode. The voltage of Converter#3 reaches the maximum setting value, and the operating point moves to point C2. The modules of Converter#2 and Converter#3 still operate in step-up mode at this time. Converter #3 operates in the constant voltage mode. Due to low output voltage of Converter#1 at point A2, the converter modules work in step-down mode.

There are three closed loops in the control strategy in Figure 13. They are input voltage loop, output current loop, and output voltage loop. $v_{in}$, $i_{in}$, and $v_{out}$ are the sample values of input voltage, input current, and output voltage, respectively. $V_{inref1}$ is the reference of input voltage from the calculation of MPPT. $V_{outref}$ is the output voltage loop reference in constant voltage mode. $V_{inref2}$ is the result of voltage compensator. The voltage loop mode controller decides whether $V_{inref}$ is $V_{inref1}$.or $V_{inref2}$. $I_{outref}$ is the output current loop reference. In MPPT mode, input voltage loop and output current loop work. In output voltage mode, output voltage loop is effective in addition. In the constant current mode, the current reference is set to the maximum value of output current. The converters could autonomously operate without central control by the control strategy.

In the operation process, the input voltage of the converter various from MPPT voltage to open voltage of the PV array. The output of voltage is various from 0 to the maximum setting value. By adjusting the duty ratio, super wide voltage gain is achieved. The input and output voltage could be matched automatically through closed loop control. In Figure 11, the range of module voltage gain is from 0 to 20. Then the range of converter voltage gain is from 0 to over 20 N, where N is the operation module number in the converter. The super wide range of voltage gain guarantees voltage match between input and output in each mode.

In practice, there is a parameters difference between modules. It will lead to voltage unbalance between modules in the converter. A module voltage sharing control loop could be included in the control strategy to prevent over voltage of modules.

In order to achieve high-efficiency operation in the wide operation range, cutting in module online to adjust operating module number is applied in the converter. When the output voltage of the converter is relatively low, the number of operating modules could be reduced, and the power and output voltage of each module are increased. The DC–DC modules could operate near the maximum efficiency operating point. When the output voltage of the converter is increased, the number of operating modules is increased to prevent overvoltage.

5. Experiment Result

According to the proposed reconfigurable DC–DC topology, the 3 kV/80 kW PV DC–DC module is developed as shown in Figure 14, and the main parameters are shown in

Table 2. Parameters of the DC module.

Parameters	Value
Input inductor $L_{in}$	0.3 mH
Switch frequency	5 kHz
Transformer leakage inductor $L_{lk}$	10 uH
Input voltage	300~800 V
Output voltage	0~3000 V
Transformer turns ratio	3.5

. A 20 kV/500 kW series-connected PV MVDC converter is developed, as shown in Figure 15.

A ±30 kV/3 MW demonstration system with two groups of series PV MVDC systems is installed, as shown in Figure 16. Each series PV system includes three PV units. Each PV unit includes a 20 kV/500 kW converter and a 500 kW PV array. The ±30 kV DC series system is connected to AC grid by MMC, as shown in Figure 1. Experiments for DC module and converters have been carried out.

5.1. Experimental Result of DC Module

Figure 17 shows the waveforms of the reconfigurable DC–DC module in step-up mode and step-down mode. In Figure 17a, the switches $Q_1$ and $Q_3$ have a duty cycle of 0.65, the input voltage $v_{in}$ is 600 V, and the output voltage $v_o$ is 3 kV. The circuit works in step-up-CCM1 mode. Figure 17b shows the waveform of the module in step-down mode. The switches $Q_1$ and $Q_3$ have a duty cycle of 0.4, the input voltage of the module $v_{in}$ is 600 V, and the output voltage $v_o$ is 1430 V. The module works in step-down-DCM2 mode.

The efficiency curves of DC module are shown in Figure 18. The maximum efficiency is 97.4% and 96.7% in step-up mode and step-down mode, respectively.

The experimental result for the module voltage ratio is shown in Figure 19. The input voltage module is set to 400 V. By regulating the duty cycle from 0 to 0.75, the output voltage gain increases from 0 to 2 kV. The module is shifted between step-up and step-down mode smoothly. The high-level of the transformer primary voltage is equal to input voltage if the duty cycle is less than 0.5. The voltage is higher than input voltage and equal to clamping capacitor voltage $v_{c2}$ if the duty cycle is more than 0.5. The duty cycle between 0.495 and 0.505 should be avoided to prevent short circuit in a bridge arm in step-down mode. The experimental results verify the theoretical derivation in Section 2.

By gradually increasing the duty cycle, soft start-up can be realized. Figure 20 shows the process of cutting in Module#1 online. The transformer voltage $v_{mac}$ and current $i_{mLlk}$ of Module#1 are gradually increased to share the voltage and current with other modules. In the process, there is no surge voltage and current.

The experimental result shows that DC module with reconfigurable topology can operate in step-up mode and step-down mode normally. The modules achieve a wide range of output voltage by adjusting the duty cycle. Zero voltage start-up and module cutting-in online can be realized.

5.2. Experimental Result on Prototype

A prototype for the PV series DC system is built to verify the proposed topology and control strategy, as shown in Figure 21. Three modules that represent three PV converters are included in the system. Each module’s input is connected with a PV Simulator. Three modules’ outputs are series connected and output to a DC grid.

In Figure 22, three modules are series connected to 1 kV DC grid. The output voltages of the three modules are about 350 V before startup. When Module#1 is started up, the output voltage of Module#1 is increased to 557 V. Module#1 operates on constant voltage mode to avoid overvoltage. The output capacitor voltages of other two modules are 245 and 270 V as shown in Figure 22a. In the shutdown process as shown in Figure 22b), Module#1 is shut down; the capacitors of the other two modules share the voltage. The output current $i_o$ is reduced to 0.

Figure 23 shows the complete startup process of the three modules without central control. In the process, each module is started up independently. As the last module is started up, three modules start to output current.

Figure 24 shows operating characteristics when PV power changes rapidly. The series DC system is connected to 8 kV DC grid. When the three PV Simulator have the same PV curve, three modules output the same power. The duty cycles of the three modules are almost the same in Figure 24a. When PV Simulator#1 quickly switches to the lower PV power curve, the output voltage and power of Module#1 is decreased, as shown in Figure 24b. Due to the lower output voltage, Module#1 operates in step-down mode.

5.3. Experimental Result of MVDC Converter

Experiments of three converters in DC series system are carried out. Figure 25 shows the actual operating waveform in a sunny day. Converter #2 and #3 finish the start-up process first. The series DC system begins to output power when Converter#1 starts up. Three converters operate in MPPT mode most of the time and share the output voltage of the system because of stable irradiance. The output voltages of the converters are 19, 20, and 21 kV, respectively.

Figure 26 shows the detail of operation status of converters in Figure 21. $v_{mac}$ and $v_{mo}$ are the transformer voltage and output voltage of the module, respectively. At 10:35 a.m. in Figure 25, three converters all operate in MPPT mode. Each converter works with eight modules. The input MPPT voltage of each converter is 650 V. The output voltages of the modules $v_{mo}$ of each converter are 2.62, 2.51, and 2.39 kV, respectively. The modules are operating in the step-up mode.

Figure 27 shows the converter waveforms in a cloudy day. The converters share the output voltage before 12:40 p.m. as the PV output power are stable. The PV power is changed rapidly due to clouds partially shielding the PV arrays from 12:40 p.m. to 14:50 p.m. During this period, the output voltage of the converters is varied as the output power is changed rapidly. The converters re-share the output voltage according to output power ratio in series system. The converters adjust the duty cycle of modules to match the input and output voltage. The partial shading of PV arrays also happened after 16:40 p.m., and the output voltages are unbalanced at that time.

Figure 28 shows the detail of operation status of converters in Figure 27. The operating status of the modules is shown as the unbalanced irradiances are happened on the three PV units. At 12:39 p.m. in Figure 27, the output voltages are unbalanced and the output voltages are 12.47, 23.99, and 24.35 kV, respectively. Each converter operates with eight modules. The modules of Converter#1 operate in step-down mode and the output voltage is decreased to 1.56 kV. The modules of Converter#2 and #3 operate in step-up mode, and the output voltage is increased to about 3 kV. All the converters still operate in MPPT mode.

Figure 29 shows the case of extreme unbalanced irradiances at 17:32 p.m. in Figure 27. The output voltage of Converter#1–#3 is 11.45, 26.80, and 22.33 kV, respectively. Converter#1 and #3 operate in MPPT mode with eight operating modules, and the output voltage of modules is 1.43 and 2.79 kV, respectively. Due to severely unbalanced output power, Converters#2 operates in constant voltage mode to avoid overvoltage. The output voltage of modules is 2.98 kV with nine operating modules. Part of PV power of Converter#2 is curtailed.

Figure 30 shows the transition process from MPPT mode to constant voltage mode. At $t_1$, the output voltage of converter reaches the maximum value and the converter shifts from MPPT mode to constant voltage mode to avoid overvoltage. In this process, the transformer voltage $v_{mac}$ is increased until the converter shifts to constant voltage mode. In the constant voltage mode, the transformer current $i_{Llk}$ is decreased to keep the voltage value.

Whenever the irradiances are stable or changed rapidly in the experiments, the converters in DC series system can always operate normally. Most of the time, the converters operate in MPPT mode to output the maximum power. The constant mode prevents converters from overvoltage in the case of extreme unbalanced output power.

6. Conclusions

This paper proposes a topology and control strategy for PV MVDC converters suitable for DC series system. The modular IPOS structure is applied for the converter. A reconfigurable DC–DC topology and modulation method is proposed for the converter module. By adjusting the duty cycle, the step-up mode and step-down mode can be shifted easily. Zero voltage soft start-up and module cutting online are realized in the module. Unlike other isolated buck–boost topologies, only diodes are employed in the high voltage side of the transformer; the output voltage of modules can be various from 0 to up to 10 kV. Only controller and switch drives are needed in low voltage side of transformer to simplify the control system. Therefore, a wide range of voltage gain and high output voltage can be obtained in the proposed topology. As the number of modules in the IPOS structure is decreased, the volume and cost of the converter could be reduced. The control strategy, which is suitable for converters in the DC series system, is proposed to ensure the converter operate normally in all the cases. A ±30 kV/3 MW demonstration system with two groups of series PV MVDC systems is installed. The PV MVDC converters operate stably in the DC series system. Through experimental verification and actual operating data, the feasibility of topology and control strategy are proven.