Simulation of a Low-Voltage Direct Current System Using T-SFCL to Enhance Low Voltage Ride through Capability

Abstract

Owing to the increasing penetration level of distributed energy resources (DER) and direct current (DC) load, the usage of low-voltage direct current (LVDC) systems has expanded to achieve efficient operations. However, because the LVDC system reaches the peak fault current at a faster rate than the alternating current (AC) system, a solution that protects the system components is necessary to maintain system integrity. It is required by the low-voltage ride-through (LVRT) that the DERs maintain their interconnections with the LVDC system and support fault recovery. In this study, a method is proposed to allow the application of the superconducting fault current limiter (SFCL) to reduce the fault current and enhance the LVRT capability. However, when the DER maintain a connection to support fault recovery, the conventional resistive-type SFCL must withstand the burden of high-temperature superconducting (HTSC) operation during fault state dependence on LVRT. Therefore, this study proposes a trigger-type SFCL to reduce the burden of the HTSC element and enhance the LVRT capability. The voltage sag related to the LVRT was improved owing to the SFCL. The proposed solution was confirmed using PSCAD/EMTDC, which is a commercial software.

1. Introduction

Low-voltage direct-current (LVDC) systems, which comprise DC loads and DC-based distributed energy resources (DER), such as photovoltaics (PV) and wind turbines, have been emphasized to achieve efficient operations [1,2,3,4]. When a fault occurs in the LVDC system, the peak of the fault current is higher and faster than that of the alternating current (AC) system because of the discharge of the DC capacitor within the interconnected system parts between the LVDC and AC [4,5,6,7]. In conventional LVDC systems which experience faults, DERs are detected simultaneously from the LVDC system to protect themselves [4]. In the case of a fault in a power system, the LVDC system is affected considerably, and collapses owing to the voltage sag at the point of common coupling (PCC) following the disconnection of the DER [7,8]. Therefore, in the case of high-penetration DERs, the LVDC system requires a continuous connection method to the LVDC system to meet the low-voltage ride through (LVRT) demands and maintain stable operation. The LVRT is a grid code in which the DER has to maintain connection and support the fault recovery according to the voltage sag and fault duration [9,10,11].

References [12,13,14] used methods that limit the fault current to protect system components. Reference [12] suggested the increase of the line impedance to limit the fault current. References [13,14] proposed the change of the capacity of the capacitor in the DC link to limit the fault current. Despite the capabilities of these methods, limiting the fault current with higher impedance and reducing the DC capacitance will increase the line losses and will lower the power quality.

References [15,16,17] introduced methods to enhance the LVRT capability. Reference [15] proposed the application of superconducting magnetic energy storage (SMES) in an AC system. Reference [16] analyzed the application of a supercapacitor in a microgrid. Reference [17] changed the design of a controller in a wind power system. However, the effects of using components and applying design changes could vary in different systems and could affect adversely the DER of LVDC systems. Therefore, this study proposes the application of a trigger-type superconducting fault current limiter (SFCL; T-SFCL) which improves the shortcomings of existing methods and achieves stable operation by setting resistance of the T-SFCL parts. According to the suggested method, the voltage sag and fault current characteristics were analyzed according to the capacity of the current limiting resistor (CLR). The fault current was limited, and the voltage sag related to the LVRT was demonstrated according to the SFCL components. In addition, the burdens of high-temperature superconducting (HTSC) is reduced owing to the CLR bears the fault current during the LVRT period. The effectiveness of the proposed method was confirmed using PSCAD/EMTDC, a commercial program.

2. Analysis Methodology and LVDC System Modeling

2.1. LVDC System Modeling with DERs

As the penetration rate of DER increases, an LVDC system that operate highly effec-tively is preferred. An LVDC system consisting of PV and DC loads is connected to the AC system through a rectifier. To verify the effects of the proposed solution, the modeling of the LVDC system is described. Figure 1 shows a schematic of the configuration of the LVDC system, and the parameters used are listed in

Table 1. Parameters of the low-voltage direct current (LVDC) system.

Classification	Parameter
line impedance	3.48 + j7.44%/km, 2.7 km
direct current (DC) load	0.166DC kV, 100 kW
total photovoltaic (PV) power	0.166DC kV, 50 kW
transformer	22.9AC/0.38AC kV, 1 MVA
converter	0.166DC/0.75DC kV, 50 kW
rectifier	0.38AC/± 0.75DC kV, 100 kW

[10]. To achieve stable operation, the LVDC system has to solve the fault current problem attributed to the discharge of the DC capacitor, and the connection time of the DERs according to the LVRT capability. In the LVDC system, the fault current increases rapidly due to the discharge of the capacitors included in rectifier and converter, and this causes damage to the equipment. The connection status of the PV is determined according to the LVRT regulations. The LVRT capability should be enhanced by improving the voltage sag [10,11,12]. Therefore, a SFCL was installed between the DC bus and rectifier to reduce the fault current and improve the voltage sag of the DC bus, which corresponds to the connection point of the PVs. A positive-to-negative fault occurs on the DC power line at 0.5 s according to the simulation scenario outlined in

Table 2. Fault scenario parameters.

Classification	Parameter
fault start time	0.5 s
fault duration time	2 s
fault type	positive-to-negative
fault resistance	0.01 Ω

. To confirm the LVRT capability, fault duration time is 2 s.

2.2. Fault Analysis in LVDC Systems

When a fault occurs between the rectifier and the DC bus, the total fault current is the sum of the fault currents from the grid and the PV, as shown in Figure 2, which describes the fault analysis of the LVDC system. According to the characteristics of the LVDC system, the fault current increases rapidly, and the voltage sag occurs instantaneously owing to the discharge of the DC capacitors. In the previous study [10], application for fault current limiter and protection relay on the rectifier was studied, and for this paper was considered only $i_{fault\_pv}$. The SFCL solves both problems related to current and voltage. Therefore, this study focused on improving the DC bus voltage sag and limiting the fault current by the converter.

In the capacitor-discharge stage, Equation (1) represents the peak fault current caused by the DC capacitors included in the converter [10,18,19]. $I_0$ and $V_0$ are the initial values of voltage across the capacitor and the line current before the the fault. And R and L are the equivalent resistance and inductance of the cable up to the fault location.

$$i_{fault\_pv}(t)=C\frac{d{v}_c}{dt}=-\frac{I_0{\omega }_0}{\omega }{e}^{-\alpha t}\sin \left(\omega t-\beta \right)+\frac{V_0}{\omega L}{e}^{-\alpha t}\sin \omega t$$

(1)

where, $\alpha =R/2L$, $\beta =arctan\left(\omega /\alpha \right)$, ${\omega }^2=1/LC-{\left(R/2L\right)}^2$ and ${\omega }_0=\sqrt{{\delta }^2+{\omega }^2}$.

When the voltage across the capacitor drops to zero, the second stage (the diode freewheeling stage), begins and the inductor causes a fault current. This stage, the fault current is represented by Equation (2), where $I_0^{\prime }$ means the fault current when the voltage of the capacitor drops to zero.

$$i_{fault\_pv}\left(t\right)=I_0^{\prime }{e}^{-\left(R/L\right)t}$$

(2)

In the last stage (grid-side current feeding stage), after the capacitor and line inductance exhaust the source, current is received from the PV [18,19].

$$i_{fault\_pv}\left(t\right)=\frac{v_c}{R}\left(1-e^{-t/\gamma }\sin \omega t\right)$$

(3)

where, $\gamma =(L_s+L)/R$, cable parameters (R, L) and converter input inductance ($L_s$).

2.3. Low-Voltage Ride-Through

Despite the disconnection of DER to protect itself from system failure, the high penetration of DER increases the effect of failure. In the worst case, the reduced voltage and frequency affect other generators which could potentially cause a grid collapse. The LVRT describes the regulation process. According to this process, the connection of the DER is determined by the area that defines the regular range of voltages and fault duration when the DER is connected to the power system [9,10,11]. Even if a fault occurs, maintaining the connection of the DER supports fault recovery, and has the advantage of enabling microgrid operation by separating the faulty section [7].

Figure 3 shows the LVRT regulations in the Republic of South Korea [9]. In the case of area A, the DER must maintain its connection with the power system. Even if the voltage of the PCC drops to zero, the DER must be connected to the power system for at least 150 ms, and operation during continuous connectivity is depended on voltage conditions. If the voltage is not recovered and falls within area B, the DER should be disconnected from the power system. Therefore, it is necessary to improve the voltage sag to increase the time the DER could be connected to the LVDC system.

2.4. Proposed Solution to Limit Fault Current and Enhance LVRT Capability

To reduce the effect of the fault current from the AC and DC grids, a method is suggested to allow the application of the SFCL. As shown in Figure 4, among the various SFCLs, the T-SFCL is applied, which can reduce the burden of HTSC elements for long fault durations. T-SFCL, which differs from the resistive-type SFCL (R-SFCL) composed only of HTSC elements, consists of an HTSC element, switch (SW), and CLR. The operation of the SW in T-SFCL is set to start within 1.5 ms after the quenching of the HTSC element. To analyze the effect of the SFCL based on considerations of the fault characteristics of the DC system, the design of the T-SFCL is divided into two phases, namely, (a) before and (b) after SW operation. Before SW operation, the resistance of HTSC element increases owing to the quenching, which creates a current-limiting characteristic and suppresses the rapidly generated fault current. After SW operation, the CLR bears the fault current instead of the HTSC element, thereby reducing the burden on the HTSC element. In addition, T-SFCL is flexible in enhancing the LVRT capability because unlike R-SFCL, the CLR can be set at various magnitudes of resistance. Equation (4) explains the resistance of the HTSC elements according to the time, and the parameters used are listed in

Table 3. Parameter of high-temperature superconductor.

Parameter	${\mathit{R}}_{\mathit{n}}$	${\mathit{T}}_{\mathit{F}}$	${\mathit{a}}_1$	${\mathit{a}}_2$	${\mathit{b}}_1$	${\mathit{b}}_2$
Value	Variable Ω	0.01 s	−80/s	−160/s	Rn Ω	Rn/2 Ω

[10]. The $R_n$ is the resistance of the HTSC elements as a result of quench phenomenon, and the $t_0$, $t_1$ and $t_2$ are the quench starting time, first recovery starting time and secondary recovery starting time. The $T_F$, $a_1$, $a_2$, $b_1$ and $b_2$ mean the coefficients of experimental results [10,20]. In the normal state, the resistance of the HTSC element is zero. Therefore, T-SFCL has an advantage in that it does not affect such as system loss [20,21,22,23,24,25,26].

$$R(t)=\{\begin{array}{ll}0\hfill & ,t<t_0\hfill \\ R_n{\left[1-\exp (-\frac{t-t_0}{T_F})\right]}^{\frac{1}{2}}\hfill & ,t_0\le t<t_1\hfill \\ a_1(t-t_1)+b_1\hfill & ,t_1\le t<t_2\hfill \\ a_2(t-t_2)+b_2\hfill & ,t_2\le t\hfill \end{array}$$

(4)

Equation (5) explains the DC bus voltage which determines the connection time of the PV. In the event of a fault, the voltage sag at the DC bus is improved by the resistance of the SFCL. The connection time of PV is improved according to the changing range from area B to A. Therefore, the SFCL can enhance the LVRT capability according to the improvement of the voltage sag [22].

$$V_{DCbus}=\frac{R_{line}+R_{SFCL}}{R_{source}+R_{trans}+R_{line}+R_{SFCL}}\cdot V_{source}$$

(5)

where, $V_{DCbus}$ is the voltage of the DC bus, $R$ are the resistance of each component, and $V_{source}$ is the voltage of converter with the PVs. In the case of T-SFCL, $R_{SFCL}$ is the combined resistance of CLR and HTSC.

3. Simulations to Verify the Effects of the Proposed Method

Computer simulations were performed for the LVDC system using PSCAD/EMTDC, a commercial software based on different SFCL case studies, to verify the proposed effects on fault current, voltage sag, and LVRT characteristics. In

Table 4. Case studies for the verification of the effects of the fault current (SFCL: superconducting fault current limiter, R-SFCL: resistive-type SFCL, T-SFCL: trigger-type SFCL).

Case	High-Temperature Superconductor (HTSC)	Current Limiting Resistor (CLR)	Remark
case A	-	-	without SFCL
case B	1 Ω	-	with R-SFCL
case C	1 Ω	0.5–5 Ω	with T-SFCL

, case studies were set according to the SFCL type. It is important to investigate the voltage on the DC bus because maintaining the connection between the PVs and the LVDC system depends on the LVRT regulation and determines the connection duration. In addition, the fault current generated by the LVDC system was generated faster by the discharge of the DC capacitors. To reduce the risk due to the fault current, the limiting effect of the SFCL in the LVDC system was inspected.

3.1. Effects of Limiting Fault Current

The results of the various case studies with different fault currents were analyzed as shown in Figure 5. In case A, in the absence of SFCL, the fault current rapidly increased to 2.49 kA due to the discharge of PV and DC capacitors after the occurrence of the fault. As the discharge of DC capacitors occurs within very short time periods, the fault current dropped from 2.49 kA to 0.22 kA. Subsequently, the PVs were disconnected owing to the LVRT regulation, and the current was reduced to zero.

In case B, a resistive-type SFCL with a resistance of 1 Ω was applied. According to the increased resistance of the HTSC element, the peak of the fault current was limited from 2.49 kA to 1.45 kA owing to the fact that the current was inversely proportional to the resistance. Even if the fault current is limited, it is expected to flow through the HTSC element, which is damaged during the fault.

In case C, the effect of the proposed method was verified, wherein all HTSC elements and the CLR were set to have resistances equal to 1 Ω; these settings are the same as those of R-SFCL. The fault current was limited from 2.49 kA to 1.54 kA, and its peak value was increased compared with case B. Because the HTSC element and CLR were connected in parallel, the total resistance was reduced compared with that in case B.

In Figure 5c, there is a problem in that the peak of fault current increases with the CLR. Figure 6 shows the fault current analysis according to the CLR. As the CLR decreases, the total resistance decreases because of the parallel interconnections before SW operation, and the peak of the fault current is increased.

Figure 7 shows the fault currents flowing through the HTSC elements and CLR according to the CLR capacity. Although the peak of the fault current in case C is larger than that in case B (Figure 5), the burden on the HTSC element was reduced when it was connected in parallel, as shown in Figure 7. During SW operation, the burdens of HTSC elements were eliminated by commutation that the fault current flowed only for 1.5 ms, and it flowed to CLR. As shown in Figure 6 and Figure 7, as the resistance of the CLR increases, the peak of the fault current decreases whereas the burden of HTSC element increases. Therefore, it is necessary to set the appropriate CLR resistor taking into consideration the enhancement of the LVRT capability.

3.2. Effects of Voltage Sag and Enhancement of LVRT Capability

Figure 8 shows the results of the voltage sag and LVRT regulation as a result of the application of the SFCL. In case A, the bus voltage, which depends on the discharge of the DC capacitors, drops momentarily to 0.11 p.u. Since the resistance of SFCL is 0 Ω, according to Equation (5), the voltage sag occurs the most. If the voltage does not recover at 0.11 p.u, the PV is disconnected 190 ms after the fault starts as a result of the LVRT regulation process. Even if the fault is quickly recovered, there is a problem that the PVs are disconnected and cannot contribute to the recovery of the fault.

In case B, the voltage sag is improved compared with case A (no SFCL). As shown in Equation (3), this is the result of the reactions by the resistance of the HTSC element increasing owing to quenching characteristics. As a result, the duration of the connection by the LVRT was delayed to 520 ms, and the performance of the interconnection was enhanced. However, there is a problem in that the HTSC must bear all the fault curves if fault recovery is not performed.

The results of the case in which the proposed T-SFCL was installed, which is most effective for the voltage sag and enhancement of LVRT, are shown in Figure 8c. The CLRs in the T-SFCL were applied to the faulted line by the SW, which performed operations simultaneously at very fast rates following the quench of the HTSC. Owing to the high resistance, the discharge of the DC capacitors was slow, and the magnitude of the DC bus voltage in relation to the fault circuit was increased considerably. In addition, increasing the resistance of the CLR from 0.5 Ω to 3 Ω further improved the voltage sag. This indicates that the connection duration of the PV was gradually enhanced to 360 ms and 760 ms according to the LVRT regulation scheme.

Figure 9 shows the voltage sag of the DC bus according to CLR. Because the operation time of the Korean protection system with coordination is 500 ms, it has the advantage of being capable to operate as a microgrid if the PV maintains the connection for 500 ms. By increasing the CLR, the voltage sag improved, and the connection of PVs was maintained. However, when the CLR was 0.5 Ω, the PV could not withstand a continuous connectivity for a period of 500 ms owing to the LVRT regulation. Therefore, when considering microgrid operations, the CLR should be set to at least 1 Ω. Although a large CLR is effective for the current limit and the voltage sag, the effect of the connection times of DER by LVRT exceeds the protection coordination time, causes an excessive economic investment, and increases the burden of the HTSC element.

Table 5. Simulation results of all studied cases.

Case	HTSC [Ω]	CLR [Ω]	Peak Fault Current [kA]	Voltage Sag [p.u]	Connection Duration [s]
case A (w/o SFCL)	-	-	2.49	0.11	0.19 (+0%)
case B (R-SFCL)	1	-	1.45 (−41.7%)	0.26	0.52 (+173%)
case C (T-SFCL)	1	0.5	1.62 (−34.9%)	0.13	0.36 (+89%)
	1	1	1.54 (−38.1%)	0.24	0.51 (+168%)
	1	3	1.47 (−40.9%)	0.41	0.76 (+300%)
	1	5	1.22 (−51.0%)	0.51	0.84 (+342%)

lists summaries of the voltage sag, peak of the fault current, and connection duration results of all the case studies evaluated herein. Looking at the results of cases B and C, the application of SFCL is effective in limiting the fault current. When the HTSC element has the same resistance in cases B and C, there is a difference in the improvement of the voltage sag despite the similar effects of the limiting fault currents. In case C, a higher resistance CLR was applied by the SW which operated at a fast rate in the case of T-SFCL at the time when the discharge of the DC capacitors was completed. The proposed method confirmed that the fault current was effectively limited, and the LVRT capability was enhanced according to the improvement of the voltage sag. In addition, as the resistance of CLR increased, the voltage sag was improved through the effective enhancement of the capability of LVRT. When considering the microgrid operation, the CLR should be set to at least 1 Ω.

4. Conclusions

The SFCL is an effective solution that limits the fault current and improves the voltage sag. However, its constituent HTSC elements endure the fault current for a long time depending on the requirement that DERs have to maintain connectivity in area A of the LVRT regulation scheme. This study proposed the application of T-SFCL, which improved the problems of existing methods and achieved stable operation. The application of T-SFCL was effective in limiting the fault current and improving the voltage sag. The peak of the fault current was limited because of the increased resistance of the HTSC element. In addition, the voltage sag improved by increasing the CLR, which in turn improved the LVRT capability. In addition, the burden of the HTSC element was reduced through an effective CLR setting based on considerations of the fault current and LVRT. As a result, DER can support fault recovery for longer time periods and can enable microgrid operation. Therefore, the proposed method was used as a solution to operate the LVDC system in a stable manner. In the future, further research on the economic effect of SFCL, configuration of system, thermal capacity of HTSC, and the control method of converter are crucial.