Passivating Silicon Tunnel Diode for Perovskite on Silicon Nip Tandem Solar Cells

Abstract

Silicon solar cells featuring tunnel oxide passivated contacts (TOPCon) benefit from high efficiencies and low production costs and are on the verge of emerging as the new photovoltaic market mainstream technology. Their association with Perovskite cells in 2-terminal tandem devices enables efficiency breakthroughs while maintaining low fabrication costs. However, it requires the design of a highly specific interface to ensure both optical and electrical continuities between subcells. Here, we evaluated the potential of tunnel diodes as an alternative to ITO thin films, the reference for such applications. The PECV deposition of an nc-Si (n⁺) layer on top of a boron-doped poly-Si/SiO_x passivated contact forms a diode with high doping levels (>2 × 10²⁰ carrier·cm⁻³) and a sharp junction (<4 nm), thus reaching both ESAKI-like tunnel diode requirements. SIMS measurements of the nc-Si (n⁺) (deposited at 230 °C) reveal an H-rich layer. Interestingly, subsequent annealing at 400 °C led to a passivation improvement associated with the hydrogenation of the buried poly-Si/SiO_x stack. Dark I–V measurements reveal similar characteristics for resistivity samples with or without the nc-Si (n⁺) layer, and modeling results confirm that highly conductive junctions are obtained. Finally, we produced 9 cm² nip perovskite on silicon tandem devices, integrating a tunnel diode as the recombination junction between both subcells. Working devices with 18.8% average efficiency were obtained, with only 1.1%_abs PCE losses compared with those of references. Thus, tunnel diodes appear to be an efficient, industrially suitable, and indium-free alternative to ITO thin films.

1. Introduction

The photovoltaic solar cells industry is largely dominated by crystalline silicon (c-Si) technologies, which hold around 80% of market shares based on the ITRPV 2022 report [1]. The development of passivated contacts in the last decade led to further improvements in c-Si solar cells’ world record (WR) photovoltaic conversion efficiencies (PCE): PCE_WR = 26.8% for the low-temperature route (i.e., silicon heterojunction (SHJ), hydrogenated amorphous silicon thin films) and PCE_WR = 26.4% for the high-temperature one (i.e., tunnel oxide passivated contacts (TOPCon), poly-Si/SiO_x stacks) [2,3,4]. These technologies are currently mature and ready to be implemented at an industrial level. The ITRPV predicts 20% of market shares by 2032 for SHJ and 42% for TOPCon [1]. Many photovoltaic research centers and industrials are now investigating tandem devices, associating a wide bandgap absorber to the c-Si solar cell, in order to push efficiencies above the 29.4% c-Si limit [5]. Among the wide band gap absorbers, perovskite (Pk) materials are of high interest as they benefit from high efficiencies (PCE_WR = 25.8%), bandgap tunability, and low production costs [6,7]. Tandem devices coupling a Pk top cell with a c-Si bottom cell already achieved 32.5% efficiency and have the potential to reach 42% [8,9]. The most cost-effective way to couple the two subcells is in series, using a 2-terminal configuration, due to reduced cell-to-module interconnections. However, it requires the design of a specific interface design to ensure both optical and electrical continuities between subcells. Currently, transparent conductive oxide interlayers are the reference for such applications and record devices feature thin indium tin oxide recombination layers (ITO_rec) at the interface between the c-Si and Pk subcells. However, indium is a critical material due to high and volatile prices and sourcing issues [10]. Therefore, its consumption should be minimized for a technology to reach the terawatt scale [11]. Silicon tunnel diodes obtained by stacking two degenerated p- and n-type Si layers are expected to provide efficient recombination current due to band-to-band tunneling [12,13]. Thus, they could represent an indium-free alternative to ITO_rec layers. Pk/c-Si tandem devices integrating such tunnel diodes as recombination junctions already achieved efficiencies above 25% for pin structures (SHJ & TOPCon bottom cells) and 22.8% for nip structures (SHJ bottom cells) [14,15,16,17]. Here, we investigated the potential of n/p tunnel diodes for application as a recombination junction for nip devices featuring TOPCon bottom cells as well. Thus, we proposed an industrially suitable process for such n/p tunnel diode fabrication and provide a comparison with a reference ITO_rec-based recombination junction through advanced characterizations and devices fabrication.

In this work, we focused on bottom cells featuring double-side poly-Si on SiO_x passivated contacts. Such cells enable high versatility for top cell processing as they benefit from robust layers and can withstand high-temperature treatments. On top of that, the poly-Si layers present high doping levels and are particularly well suited for recombination junction formation. With plasma-enhanced chemical vapor deposition (PECVD) of phosphorus-doped nanocrystalline Si layers (nc-Si (n⁺)) on top of boron-doped passivated contacts, we fabricated industrially compatible nc-Si (n⁺)/poly-Si (p⁺)/SiO_x passivating tunnel diodes. First, we investigated the tunnel diode passivation quality and conductivity with dedicated characterization samples. Then, we produced monolithic Pk/c-Si 9 cm² nip tandem solar cells with tunnel diodes as recombination junctions and compared them with reference devices featuring ITO_rec interlayers instead. Thus we assessed the potential of our tunnel diodes to provide efficient carrier recombination in 2-terminals nip Pk/c-Si tandem devices.

2. Results and Discussion

2.1. n⁺/p⁺ Tunnel Diode Fabrication

The p-type (n-type) high-temperature passivated contacts are fabricated with ex-situ doping of 15 nm-thick low-pressure chemical-vapor-deposited polycrystalline Si films by B₂H₆ (PH₃) plasma immersion ion implantation. These poly-Si/SiO_x stacks are then annealed at 875 °C to ensure crystallization and dopants activation. Passivated contacts’ detailed processing sequence can be found in reference [18]. HRTEM (high-resolution transmission electron microscopy) images of the tunnel diode (Figure 1a) confirm the growth of homogenous polycrystalline Si films with a grain size of about 15 nm, similar to the layer thickness. Electrochemical capacitance-voltage (ECV) profiling (Figure 2a) reveals high doping levels in these p-type poly-Si/SiO_x stacks and carrier concentrations above 3 × 10²⁰ holes·cm⁻³ were measured. This highlights the suitability of our passivated contacts fabrication process for the formation of tunnel diodes.

The nc-Si (n⁺)/poly-Si (p⁺) tunnel diodes are then formed with an industrial 2-steps process including, first, wet chemical cleaning of the poly-Si (p⁺)/SiO_x passivated contacts, and second, PECV deposition of the in-situ phosphorous-doped nanocrystalline Si films. During the wet chemical cleaning, the poly-Si (p⁺) surfaces are deoxidized in an HF/HCl bath and rinsed with ozonized water. It results in the growth of a thin chemical oxide between the n- and p-type layers, as can be seen on energy dispersive X-ray spectroscopy (EDX) imaging of the tunnel diode (Figure 1b). Such an ultra-thin oxide layer is known to prevent dopant inter-diffusion issues [19,20]. Subsequently, 25 nm nc-Si (n⁺) films are deposited at 230 °C in an industrial PECVD reactor from silane and phosphine precursors dissociated at 0.3 W.cm⁻². Figure 1a depicts nc-Si (n⁺) layers consisting in an amorphous phase, including a mix of small grains with sizes from approximately 2 nm to 10 nm. The diffraction image (Figure 1d) obtained with Fast Fourier Transform (FFT) from nc-Si (n+) (black square region in Figure 1c) shows both diffraction peaks and more or less continuous rings. They are a signature of, respectively, crystalline and amorphous phases. These two phases are intertwined in the 3 spatial dimensions at nanometer scale. ECV measurements (Figure 2a) reveal high doping levels in the nc-Si (n⁺) layers too, with electrically active dopants concentrations above 2 × 10²⁰ atom.cm^-3. Interestingly, high carrier concentrations (>1 × 10²⁰ carrier·cm⁻³) are measured in both n- and p-type layers even at the junction edges. This demonstrates very sharp junctions with widths below our ECV tool accuracy (WEP CVP21). Thus, our stacks reach both prerequisites for an efficient ESAKI-like tunnel diode [21]. Using SCAPS, we plotted in Figure 2b the band diagram associated with the experimental doping levels measured by ECV [22]. It highlights that such doping levels enable tunneling between the nc-Si (n⁺) conduction band and poly-Si (p⁺) valence band through a calculated junction width below 4 nm (between n- and p-type degenerated layers).

2.2. Passivation Quality Assessment

Specific lifetime samples (Figure 3) featuring double-side poly-Si (p⁺)/SiO_x stacks were produced on n-type CMP (chemical mechanical polishing) wafers. The passivation quality was evaluated via iV_OC (implied open circuit voltage) extraction from photoconductance decay measurements with a Sinton tool in transient mode.

Table 1. iV_OC of lifetime samples at different processing steps (ΔiV_OC = iV_{OC, post annealing} − iV_{OC, pre annealing}).

Steps	Poly-Si (p+) Formation (Both Sides)	nc-Si (n+) Deposition (Front Side)	400 °C (N2)	600 °C (N2)	400 °C (N2 + O2)
iVOC (mV)	691.3 (±3.7)	680.1 (±10.4)	681.7 (±1.0) ΔiVOC = +7.3	671.7 (±3.6) ΔiVOC = −8.4	688.7 (±3.4) ΔiVOC = +8.0

summarizes the passivation quality (average value of 9 samples) of the precursors with double-side p-type passivated contacts and after nc-Si (n⁺) deposition on front sides, using the process sequence described in part 2a. Our symmetrical precursors with double-side poly-Si (p⁺)/SiO_x present 691 mV state-of-the-art iV_OC values. However, the following deposition of nc-Si (n⁺) induces an average iV_OC degradation of 11.2 mV and enhances variability.

Additionally, we performed 3 different annealings of the tunnel diodes (5 min in lamp oven) and evaluated their impact on the passivation quality (average value of 3 samples). Interestingly, the annealing of the tunnel diode at 400 °C under N₂ or N₂ + O₂ atmospheres allowed passivation recovery of about 8 mV, whereas annealing at 600 °C induced further iV_OC losses of 8.4 mV.

Figure 4 presents secondary ion mass spectroscopy (SIMS) measurements of H, P, and B atoms in lifetime samples for tunnel diodes annealed (under N₂) up to 600 °C. We plotted the measurement data for P and B independently of the annealing temperature, as the profiles did not change upon annealing. Interestingly, the as-deposited nc-Si (n⁺) layer contains high hydrogen concentrations, especially close to the surface. Annealing the tunnel diode at 400 °C induces H diffusion (and/or exodiffusion) and depletes the H concentration in the nc-Si (n⁺) layer, with still high H content at the tunnel diode oxide. Thus, we believe that the passivation recovery observed after such annealing could be explained by hydrogenation of the buried poly-Si/SiO_x stack [23]. Annealing at 600 °C led to complete H effusion from the stacks, thus explaining why no passivation gain was observed for such a temperature.

This highlights that the deposition of an nc-Si (n⁺) layer on a poly-Si (p⁺)/SiO_x stack could provide a double role: formation of the recombination junction and hydrogenation of the buried passivated contacts for bottom cell efficiency improvement.

2.3. Conduction Assessment

Samples featuring double-side poly-Si (p⁺)/SiO_x stacks on p-type CMP wafers have been produced for contact resistivity measurements. The tunnel diode is then formed on the front side with nc-Si (n⁺) deposition according to the process sequence presented in part 2a. (Figure 5a). Additionally, reference samples were fabricated, replacing the nc-Si (n⁺) PECV deposition step by a 12 nm thick ITO_rec physical vapor deposition (PVD) one (Figure 5b). By doing so, we will be able to compare the conductivity of our nc-Si (n⁺)—poly-Si (p⁺) tunnel diodes with ITO_rec—poly-Si (p⁺) reference recombination junctions. The test structures were then completed with double side PV deposition of 100 nm thick ITO_contact and 100 nm Ag layers for contact formation.

After passivated contacts fabrication and before nc-Si (n⁺) or ITO_rec deposition, half of the samples underwent an additional firing step of 2 s at 950 °C in a lamp oven. This treatment is known to enable pinhole formation in the SiO_x layers to enhance the carrier transport through the oxide. Doing so, we expect the “substrate” to be more conductive, thus enabling more accurate resistivity characterization of the recombination junctions.

Figure 5c presents the dark I–V (current–voltage) measurements of those structures on 25 cm² samples. The measurement setup imposed current limitations around 200 mA.cm⁻². The I–V characteristics present strong non-linearity for the samples without the firing of the passivated contacts independently of the recombination junction (nc-Si (n⁺) and ITO_rec). However, as expected, firing the passivated contacts enabled pinholes formation through the SiO_x layers and led to both ohmic I–V characteristics and stack conductivity improvement.

Interestingly, samples with nc-Si (n⁺) exhibit close I–V characteristics compared with references with ITO_rec, indicating equivalent conductivity properties for both approaches. Interestingly, Figure 5c even shows nc-Si (n⁺)—poly-Si (p⁺) tunnel diodes slightly more conductive than the ITO_rec—poly-Si (p⁺) reference counterparts.

We developed an electrical calculation model to simulate the dark I–V characteristics of our structures—based on the solution of an equivalent circuit (Figure 6a)—representing the stack of the resistivity samples. We calculated the measured current (I_TOT) as a function of the applied voltage (V_app) using the following electrical components and I–V equations (the detailed numerical approach is presented in Appendix A) [24].

The tunnel oxide films limit the current flowing through the passivated contacts. Thus, for the associated electrical component, the current (I_ox) was defined as a function of the voltage (V_ox) with the following simplified I–V equation:

$$I_{ox}=sign\left(V_{app}\right) J_0 \left(e^{\left(\frac{sign\left(V_{app}\right) V_{ox} q}{n k_b T}\right)}-1\right)$$

(1)

where J₀ is the saturation current, q is the absolute value of the electron charge, n is the ideality factor, k_b is the Boltzmann constant, and T is the absolute temperature.

The tunnel diode is expected to enable band-to-band tunneling, and the following empirical equation was used:

$$I_{tun}=a_t V_{tun }{\left(V_{dd}-V_{tun}\right)}^2$$

(2)

where I_tun is the current flowing through the tunnel diode, a_t is the tunnel diode pre-factor, V_tun is the voltage across the tunnel diode, and qV_dd is the energy between n-type conduction and p-type valence bands.

The other interfaces and bulk materials are assumed to have ohmic I–V characteristics and are modeled together in a single electrical component with the following equation:

$$I_{Rs}=\frac{V_{Rs}}{R_s}$$

(3)

where I_Rs is the current flowing through the component, V_Rs is the voltage across the component, and R_s is a global series resistance.

A component in parallel of this stack accounts for shunts leakage through the structure and is modeled with:

$$I_{shunt}=\frac{V_{app}}{R_{shunt}}$$

(4)

where I_shunt is the current, V_app is the voltage, and R_shunt is the shunt resistance.

First, we ran electrical calculations without taking into account any tunnel diodes in the modeled stack in order to determine relevant parameters for Equations (1), (3), and (4). The parameters presented in

Table 2. Parameters used for Equations (1), (3), and (4).

RS	Rshunt	J0	n
1.20 Ω·cm2	60 Ω·cm2	0.1 A·cm−2	1.3

led to efficient fits between the simulated and experimental I–V characteristics (Figure 7) and were used for the following calculations.

Figure 6b presents calculation results for simulations including the tunnel diode in the modeled stack. The tunnel diode conductivity has been varied by changing the tunnel diode prefactor (a_t) value. It can be seen that the peak-to-valley behavior characteristic of tunnel diodes is displaced for larger values of a_t. For values above 10 A·cm²·V⁻³, this behavior appears for currents higher than our setup limitation. Thus, transparent tunnel diodes on experimental I–V characteristics are proof of highly conductive diodes. Interestingly, when the tunnel diode resistivity is increased (a_t value decreased), the total slope of the dark I–V characteristic decreases, even for low current values. Thus, comparing the slope of our tunnel diodes with one of reference recombination junctions seems relevant to assess equivalent conductivity properties for both approaches.

Figure 8a,b present the dark I–V characteristics of the tunnel diode (Figure 5a) at different temperatures on 0.08 cm² samples under liquefied N₂ cooling (Janis ST-500, Keithley 4200-SCS). At 250 mV, we observe around 5%_rel current losses (15 mA·cm²) over a 100 °C temperature variation. Thus, the current exhibits extremely low dependency on the measurement temperature. Figure 8c presents the current activation energy calculated with Equation (5) and reveals E_a below 10 meV. Such a low activation energy confirms a high band-to-band tunneling current [24,25].

$$E_a=\frac{d\left(lnI\right)}{d\left(\frac{q}{k_b T}\right) }$$

(5)

where E_a is the activation energy, I the current, q the absolute value of the electron charge, k_b the Boltzmann constant, and T the absolute temperature.

2.4. Tandem Integration

To complete the study, 9 cm² nip Pk/c-Si tandem devices integrating tunnel diodes recombination junctions were fabricated (Figure 9b) and compared with reference devices featuring ITO_rec-based ones instead (Figure 9a). The bottom cells consist in CMP c-Si cells (M2 format, 244.26 cm²), featuring double poly-Si/SiO_x stacks, phosphorus-doped on the rear side, and boron-doped on the front side. The recombination junction was then built on the front side with 25 nm nc-Si (n⁺) PECV deposition (tunnel diode) according to the process described in part 2a or with 12 nm ITO_rec PV deposition (reference). To ensure optimal wettability of the bottom cell front surface before Pk top cell spin coating, a UV-Ozone treatment was performed for 30 min for reference devices presenting ITO_rec. However, if such a treatment is a reference on ITO_rec films, it could lead to the degradation of the tunnel diodes Si layers due to unwanted surface oxidation [26,27]. Thus, samples with nc-Si (n⁺) were integrated without UV-Ozone surface treatment. The 9 cm² Pk top cell was then fabricated with spin coating of 30 nm SnO₂ (electron transport layer), 300 nm MaPBI₃ (methylammonium lead iodide, absorber), and 50 nm PTAA (poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine, hole transport layer). Finally, the devices were completed, and contacts were formed with double side PV deposition of 100 nm ITO_contact and evaporation of 200 nm Ag layers (full area on the rear side and patterned on the front side).

Figure 9c shows the AM1.5 (Air Mass 1.5) devices’ I–V characteristics and

Table 3. AM1.5 IV parameters for Pk/c-Si tandem devices with different RJ (average of 3 cells).

Interlayer	VOC (mV)	ISC (mA.cm−2)	FF (%)	PCE (%)
ITOrec	1676 ± 19	15.7 ± 0.2	75.6 ± 0.8	19.9 ± 0.2
nc-Si (n+)	1688 ± 40	16.1 ± 0.8	69.3 ± 0.8	18.8 ± 0.4

shows the associated I–V parameters’ average values. Integration of the silicon tunnel diode in nip Pk/c-Si tandem devices led to a champion device presenting 19.0% PCE and 70% FF. Obtaining high V_oc and fill factor values confirm the tunnel diodes provide efficient carrier recombination current between both subcells.

Devices with tunnel diode (nc-Si (n⁺)) recombination junctions show an average of 1.1%_abs PCE and 6.3%_abs FF losses compared with those of references (ITO_rec). These losses are caused by non-optimized SnO₂—nc-Si (n⁺) interfaces leading to internal series resistances, therefore limiting our devices’ fill factors and efficiencies values. We attributed the high SnO₂—nc-Si (n⁺) resistivity to the growth of a parasitic interfacial SiO_x layer.

Therefore, the tunnel diode presents high recombination tunneling current and leads to functional Pk/c-Si solar cells with high FF values. Thus, they represent an indium-free alternative to ITO_rec-based recombination junctions. However, the contact between the bottom cell last silicon layer (nc-Si (n⁺) and top cell ETL still has to be improved by either reducing the interface oxidation sensitivity or by exploring the use of other ETL materials.

3. Conclusions

Silicon tunnel diodes have already been investigated for application as recombination junctions in Pk/c-Si tandem devices for pin structures with SHJ or TOPCon bottom cells and for nip structures with SHJ bottom cells. Here, we studied n/p tunnel diodes (nip structure) to reveal their potential to form efficient recombination junctions on TOPCon bottom cells too.

We showed that an industrially adapted one-step process featuring an nc-Si (n⁺) layer PECV deposition on a boron-doped passivated contacts enables the formation of a well-crystalized and highly doped n⁺/p⁺ tunnel diode reaching both ESAKI requirements for an efficient tunnel diode (strong active doping levels and sharp junction). The nc-Si (n⁺)/poly-Si (p⁺)/SiO_x stacks show good passivation of the c-Si bottom cell (iV_oc = 680.1 mV). A subsequent annealing step at 400 °C leads to an 8.0 mV gain attributed to hydrogenation of the passivated contacts by the H-rich nc-Si (n⁺) layer. Dark I–V measurements of resistivity structures highlight low resistivity nc-Si (n⁺)—poly-Si (p⁺) tunnel diodes. They even seem more conductive than the ITO_rec—poly-Si (p⁺) reference recombination junction. The tunnel diode presents both high surface passivation quality and good conductivity, and thus, is an efficient alternative to ITO_rec-based recombination junctions.

The fabrication of 9 cm² Pk/Si nip tandem devices integrating tunnel diodes as recombination junctions enables fill factors of up to 70% and efficiencies of up to 18.8%. This assesses efficient carrier recombination between subcells. However, such cells still present 6.3%_abs fill factor losses compared with references with ITO_rec-based recombination junctions. This is likely due to internal series resistances coming from a non-optimized SnO₂—nc-Si (n⁺) interface.