Three-Leg Quasi-Z-Source Inverter with Input Ripple Suppression for Renewable Energy Application

Abstract

Single-phase inverters are widely employed in renewable energy applications. However, their inherent 2ω-ripple power can substantially affect system performance, leading to fluctuations in the maximum power points (MPP) of photovoltaic (PV) systems and shortening the lifespans of fuel cell (FC) systems. To alleviate input ripple, a three-leg quasi-Z-source inverter (QZSI) and its associated control strategy are proposed. The QZSI consists of a quasi-Z-source network, an H-Bridge inverter, and an active power filter (APF). The active filtering structure comprises filtering capacitors and the third bridge leg. The proposed control strategy consists of three loops: open-loop simple boost control, output voltage control, and 2ω-ripple suppression control. Open-loop simple boost control is utilized for shoot-through state modulation, output voltage control is applied to the two bridge-legs of the H-Bridge, and the additional third bridge-leg adopts a quasi-PR control (QPR) method that injects specific frequency harmonic voltage and suppresses newly generated low-frequency components of the input current. This method effectively avoids the drawbacks of utilizing passive filtering strategies, such as high-value impedance networks, low power density, and weak system stability. A simulation platform of 300W 144VDC/110VAC50Hz is constructed. The simulation results indicate that the addition of the third bridge leg under full load conditions reduces the input-side inductor current ripple ΔI from 1.89 A with passive filtering to 0.513 A, representing a reduction of 72.86%. The second harmonic ripple of the input current is reduced from 18.2% to 4.5%, and the fourth harmonic ripple is reduced from 16.5% to 2.1%. The DC bus voltage ripple ΔV_PN falls from 70.75 V to 6.54 V, representing a reduction of 90.76%. The Total Harmonic Distortion (THD) of the output voltage and current are both less than 1%. The simulation results validated the feasibility of the proposed approach.

1. Introduction

It is widely recognized that the DC side of single-phase inverter systems can generate double frequency (2ω) current ripple as a result of pulsating power [1]. The 2ω ripple power can exert harmonic stresses on the DC side of the inverter, causing overheating and inefficiencies, as well as significantly impacting system functionality [2]. In photovoltaic power generation applications, low-frequency pulsating currents can affect the Maximum Power Point Tracking (MPPT) of the circuit and the energy utilization of the photovoltaic panel, ultimately resulting in a reduction in the power generation efficiency of photovoltaic power generation systems [3,4,5,6,7]. In addition, for the chargers of electric vehicles, in the Vehicle-to-Grid (V2G) operation mode, the secondary ripple component on the DC side is more severe, further reducing the life and performance of the battery pack [8,9]. For three-phase systems, in the event of an asymmetrical fault, the AC side will also produce 2ω ripple, and the 2ω ripple can seriously affect the DC bus voltage and even the generation side. Therefore, research efforts focused on suppressing low-frequency pulsating power in new energy supply systems as an important research direction. The methods of suppressing 2ω ripple in traditional inverters are usually divided into passive filtering and active filtering [10,11].

Passive techniques involve the use of inductors and capacitors as LC passive filters on the DC side to absorb low-frequency ripple. The passive power decoupling technology employed in traditional voltage-source and current-source inverters does not require additional active switches, making it simple to implement with straightforward control. Voltage-source inverters usually employ large-capacity electrolytic capacitors to suppress high-frequency switching ripple voltage and low-frequency ripple voltage [12]. However, the equivalent series resistance of the electrolytic capacitor leads to power loss during operation, which can cause its temperature to rise and significantly shorten the lifespan of the electrolytic capacitor. Two-stage inverters are widely utilized in applications where the input voltage on the DC side undergoes significant changes, or when there is a substantial difference between the input voltage on the DC side and the output voltage on the AC side. Such inverters comprise a DC-DC converter in the front stage and an inverter in the rear stage. However, ripple power may generate a secondary ripple current in the input current of the rear-stage inverter. This secondary ripple current flows back to the front-stage DC-DC converter and the DC input source, increasing the current stress of the power switches and resulting in power loss. Typically, a DC-side electrolytic capacitor is utilized to absorb the secondary ripple current in parallel, which places significant demands on the capacitor. To mitigate this issue, the authors of [13] proposed a current compensation control scheme with repetitive control. Additionally, [14] and [15] propose different control methods to suppress the secondary ripple current of the Two-Stage Power Factor Correction (PFC) converter and AC/DC/AC converter, respectively. The impedance-source converters are widely used in various fields, such as fuel cells, photovoltaic arrays, and electric vehicles [16,17,18]. However, there is secondary ripple power on the DC side of single-phase impedance-source inverters, and impedance-source converters generally require a large impedance-source network to filter out low-frequency ripple [16,19,20]. To decrease the demand for electrolytic capacitors, impedance-source inverters typically optimize the impedance-source network parameters in terms of passive power decoupling topology. The authors of [21] proposed an effective method for suppressing secondary ripple that reduces the capacitor requirements for single-phase Z-source/quasi-Z-source inverters, storing secondary ripple energy in C₁ and C₂. Compared to traditional quasi-Z-source inverter photovoltaic power generation systems, although the capacitance value is reduced, the voltage stress of the switch increases slightly, leading to a decrease in efficiency.

Active filtering is the method of using active filters usually composed of power switches and energy storage elements to buffer low-frequency ripple [22,23,24]. To reduce the demand for DC side inductors and capacitors, a separate active power buffer can be designed. Low-frequency ripple power can be handled using additional power electronic devices and energy storage elements. Since the voltage or current of the storage element in the separate active power buffer can be controlled independently, the volume of the power buffer can be reduced through increasing the AC variation in the voltage or current of the storage element. The authors of [25] integrated the single-phase switched boost inverter (SBI) with a separate boost-type active power buffer to reduce passive components on the switch impedance network. The authors of [26] proposed an Active Low-Frequency Ripple Control Device (ALFRCD) and control method for Building-Integrated Photovoltaic (BIPV) systems, which reduces the use of electrolytic capacitors and improves the lifespan and reliability of the photovoltaic system through introducing a boost-type active low-ripple control device. The authors of [22] proposed three control methods for the voltage and ripple of the energy storage capacitor of the active power buffer, including voltage set-point control, ripple ratio control, and minimum voltage set-point control. Buck-boost-type active power buffers have wide voltage adjustment characteristics, and there is no upper limit on the voltage set-point of the energy storage capacitor; however, when it is much lower than the DC bus voltage, it may affect the effectiveness of the secondary ripple suppression. In addition, to suppress the influence of dc-link voltage ripple on the back-stage DAB, the authors of [27] proposed a feedback linearization control strategy; however, this technique is designed for two-stage converters and cannot achieve good ripple suppression for single-stage inverters.

However, conventional inverters contain only one degree of control freedom, and when the desired AC side voltage amplitude is higher than the given DC voltage value, a DC-DC converter must be integrated to form a two-stage structure to meet the demand [28].

Compared to conventional inverters, the quasi-Z-source inverter (QZSI) [29] offers several advantages that make it an attractive alternative. Firstly, the QZSI has two independent degrees of control freedom—the shoot-through duty cycle and the modulation—providing greater flexibility in controlling the output. Secondly, its unique impedance network structure allows for both boost and buck functions of a DC-DC converter, resulting in a single-stage system that is more cost effective. Thirdly, the QZSI permits bridge leg shoot-through and exhibits stronger anti-electromagnetic interference (EMI) capability. These features make the QZSI a more appealing option for power electronics applications. Similar to traditional inverters, QZSI can also absorb 2ω ripple using passive filtering techniques. [30,31] analyzed the relationship between the 2ω current and capacitor voltage of the impedance network and the impedance network parameters based on the small signal model. The authors of [30] provided a principle for designing LC parameters using the allowable ripple percentage of inductor current and capacitor voltage under symmetric parameter conditions. The authors of [31] stated that a higher percentage of ripple is needed to meet the demand under asymmetric parameters. However, the method proposed in [30,31] requires large-capacity capacitor and inductor impedance networks, which will not only lead to large volume, heavy weight, and high cost of inverters, but will also reduce the efficiency and reliability of the system.

The authors of [32,33] proposed methods to reduce the 2ω ripple through adjusting the shoot-through duty cycle. The authors of [32] proposed a current damping control method, which can completely eliminate the low-frequency ripple in the inductor current of the impedance network. However, this method requires a complex and sophisticated control system. On the other hand, [33] presented a hybrid pulse width modulation technique that can significantly reduce the required inductance and capacitance values. Nevertheless, the system must be paralleled with a large-capacity DC power supply terminal capacitor.

To minimize the 2ω ripple on the DC input side without increasing the parameters of the impedance network, this paper proposes a novel single-phase three-leg QZSI topology. This topology is based on the active filtering techniques of traditional inverters and injects harmonic voltage into an additional third bridge leg to buffer low-frequency pulsating power, effectively suppressing input current ripple. Compared with the passive filtering suppression method, the additional power switching device used in this approach is smaller in size and weight. Furthermore, the impedance network only needs to avoid the switching frequency ripple setting, which significantly improves the power density of the inverter. The paper is organized as follows: Section 2 introduces the circuit topology and ripple suppression principle of single-phase three-leg QZSI, Section 3 discusses the control strategy of the system, Section 4 designs the system parameters, Section 5 shows simulation results, and Section 6 concludes this work.

2. Circuit Topology and Operating Principle of the Proposed Inverter

2.1. Traditional Quasi-Z-Source Inverter and the Analysis of Its Secondary Ripple

The traditional single-phase QZSI contains two bridge legs, and there are two operating modes: the shoot-through state and the non-shoot-through state. The circuit topology is shown in Figure 1.

The equivalent circuits for the non-shoot-through state and the shoot-through state are shown in Figure 2 and Figure 3, respectively.

As the impedance network is a symmetrical network, C₁ = C₂ and L₁ = L₂, which can be obtained as follows:

$$V_{C1}=V_{C2}\hspace{1em}{V}_{L1}=V_{L2}$$

(1)

where V_C1 and V_C2 represent the voltages across the capacitors C₁ and C₂, while V_L1 and V_L2 denote the voltages across inductors L₁ and L₂, respectively.

In the non-shoot-through state, the inductors L₁ and L₂ store energy, while capacitors C₁ and C₂ release energy. Equations (2) and (3) can be obtained using Kirchhoff’s Voltage Law (KVL) and Kirchhoff’s Current Law (KCL):

$$\begin{array}{l}{V}_{L1}=V_i-V_{\mathrm{PN}}-V_{L2}\\ V_{L2}=-V_{C2}\\ V_{\mathrm{PN}}=V_{C1}-V_{L2}\end{array}$$

(2)

where V_i represents the DC input current, and V_PN represents the DC bus voltage.

$$\begin{array}{l}{i}_{C1}=i_{L2}-i_{\mathrm{VD}}\\ i_{C2}=i_{L1}-i_{\mathrm{VD}}\\ i_{\mathrm{PN}}=i_{C2}+i_{L2}\end{array}$$

(3)

where i_C1 and i_C2 represent the currents flowing through capacitors C₁ and C₂, respectively. i_VD represents the current flowing through diode VD. i_L1 and i_L2 represent the currents flowing through inductors L₁ and L₂, respectively. i_PN represents the DC bus current.

In the shoot-through state, H-Bridge is short-circuited and the diode VD is in the off state. The inductors L₁ and L₂ release energy, while the capacitors C₁ and C₂ store energy. Equations (4) and (5) can be obtained from KVL and KCL:

$$\begin{array}{l}{V}_{L1}=V_i+V_{C2}\\ V_{L2}=V_{C2}\\ V_{\mathrm{PN}}=0\end{array}$$

(4)

$$\begin{array}{l}{i}_{C1}=i_{L2}\\ i_{C2}=i_{L2}\\ i_{\mathrm{PN}}=i_{C2}+i_{L2}\end{array}$$

(5)

At steady-state, the voltages across the inductors L₁ and L₂ are both zero within one cycle. Using Equations (2) and (4) and the volt-second balance, Equation (6) can be obtained:

$$\begin{array}{l}{\overline{V}}_{L1}=\frac{(V_i-V_{PN}-V_{L2})T_1+(V_i+V_{C2})T_0}{T}=0\\ {\overline{V}}_{L2}=\frac{-V_{C2}{T}_1+V_{C1}{T}_0}{T}=0\end{array}$$

(6)

where ${\overline{V}}_{L1}$ and ${\overline{V}}_{L2}$ are the average values of the voltage across the inductors over one cycle, T₀ is the time in the shoot-through state, T₁ is the time in the non-shoot-through state, and the period T = T₀ + T₁.

At steady state, the capacitor current is zero over one period. Using Equations (3) and (5) and the charge balance, Equation (7) can be obtained:

$$\begin{array}{l}{\overline{I}}_{C1}=\frac{(i_{\mathrm{PN}}-i_{L2})T_1+i_{L1}{T}_0}{T}=0\\ {\overline{I}}_{C2}=\frac{(i_{\mathrm{PN}}-i_{L1})T_1+i_{L2}{T}_0}{T}=0\end{array}$$

(7)

where ${\overline{I}}_{C1}$ and ${\overline{I}}_{C2}$ are the average values of the capacitor currents over one period.

Equation (8) can be obtained from Equations (6) and (7),

$$\begin{array}{l}{V}_{C1}=\frac{T_1}{T_1-T_0}{V}_i=\frac{1-D}{1-2D}{V}_i\\ V_{C2}=\frac{T_0}{T_1-T_0}{V}_i=\frac{D}{1-2D}{V}_i\\ {\overline{I}}_{L1}={\overline{I}}_{L2}\end{array}$$

(8)

where D represents the duty cycle of the shoot-through state, while $D=\frac{T_0}{T}$. ${\overline{I}}_{L1}$ and ${\overline{I}}_{L2}$ are the average values of the inductor currents about L₁ and L₂.

From Equations (2) and (8), Equation (9) can be obtained:

$$V_{\mathrm{PN}}=V_{C1}-V_{L2}=V_{C1}+V_{C2}=\frac{1}{1-2D}{V}_i=B{V}_i$$

(9)

where B is the boost factor, $B=\frac{1}{1-2D}\ge 1$.

The output voltage and current on the AC side can be written as follows:

$$\begin{array}{l}{v}_o=\sqrt{2}{V}_o\sin (\mathsf{\omega }t)\\ i_o=\sqrt{2}{I}_o\sin (\mathsf{\omega }t+{\mathsf{\phi }}_L)\end{array}$$

(10)

where ω is the fundamental angular frequency, φ_L is the power factor angle, and V_o and I_o are the rms output voltage and current, respectively.

The expression of the output instantaneous power on the AC side is

$$p_o=v_o{i}_o=V_o{I}_o\cos {\mathsf{\phi }}_L-V_o{I}_o\cos (2\mathsf{\omega }t+{\mathsf{\phi }}_L)$$

(11)

The relationship between the output voltage and the DC bus voltage V_PN can be expressed as

$$\frac{v_o}{V_{PN}}=M\sin \mathsf{\omega }t$$

(12)

From Equations (10) and (12), the peak output voltage of the single-phase inverter is given by

$$\sqrt{2}{V}_o=M{V}_{PN}=MB{V}_i=G{V}_i$$

(13)

where M is the modulation index, and G is the boost coefficient of the quasi-Z-source inverter.

When the circuit is in the shoot-through state, the DC bus voltage is zero; when the circuit is in the non-shoot-through state, the power is transferred from the DC side to the AC side. If the intermediate losses are neglected, Equation (14) can be written as

$$V_{PN}\times i_{PN}\times (1-D)=p_o$$

(14)

The DC bus current expression can be obtained using Equations (12) and (14)

$$i_{PN}=\frac{M{I}_o}{1-2D}\left[\cos {\mathsf{\phi }}_L-\cos (2\mathsf{\omega }t+{\mathsf{\phi }}_L)\right]=I_{PN}+{\tilde{i}}_{PN-2\mathsf{\omega }}$$

(15)

where I_PN is the DC component, and ${\tilde{i}}_{PN-2\mathsf{\omega }}$ is the 2ω component of the DC bus current. The inductor currents i_L1 and i_L2 and capacitor voltages v_C1 and v_C2 in the impedance network are directly influenced via i_PN, so that

$$\begin{array}{l}{i}_{L1}=I_{L1}+{\tilde{i}}_{L1-2\mathsf{\omega }}\hspace{1em}{i}_{L2}=I_{L2}+{\tilde{i}}_{L2-2\mathsf{\omega }}\\ v_{C1}=V_{C1}+{\tilde{v}}_{C1-2\mathsf{\omega }}\hspace{1em}{v}_{C2}=V_{C2}+{\tilde{v}}_{C2-2\mathsf{\omega }}\end{array}$$

(16)

where ${\tilde{i}}_{L1-2\mathsf{\omega }}\hspace{1em}, {\tilde{i}}_{L2-2\mathsf{\omega }}, {\tilde{v}}_{C1-2\mathsf{\omega }}, {\tilde{v}}_{C2-2\mathsf{\omega }}$ are the 2ω components of the corresponding currents and voltages, respectively.

When the DC input voltage is constant, the power supply and capacitors charge the inductors in the shoot-through state, and there exists a 2ω component relationship.

$$\left\{\begin{array}{l}{L}_1\frac{\mathrm{d}{\tilde{i}}_{L1-2\mathsf{\omega }}}{dt}={\tilde{v}}_{C1-2\mathsf{\omega }}\\ L_2\frac{\mathrm{d}{\tilde{i}}_{L2-2\mathsf{\omega }}}{dt}={\tilde{v}}_{C2-2\mathsf{\omega }} \\ C_1\frac{\mathrm{d}{\tilde{v}}_{C1-2\mathsf{\omega }}}{dt}=-{\tilde{i}}_{L1-2\mathsf{\omega }}\\ C_2\frac{\mathrm{d}{\tilde{v}}_{C2-2\mathsf{\omega }}}{dt}=-{\tilde{i}}_{L2-2\mathsf{\omega }}\end{array}\right.$$

(17)

In the non-shoot-through state, the power supply and the inductors charge the capacitors with the following 2ω component relationship.

$$\left\{\begin{array}{l}{L}_1\frac{\mathrm{d}{\tilde{i}}_{L1-2\mathsf{\omega }}}{dt}=-{\tilde{v}}_{C1-2\mathsf{\omega }}\\ L_2\frac{\mathrm{d}{\tilde{i}}_{L2-2\mathsf{\omega }}}{dt}=-{\tilde{v}}_{C2-2\mathsf{\omega }}\\ C_1\frac{\mathrm{d}{\tilde{v}}_{C1-2\mathsf{\omega }}}{dt}={\tilde{i}}_{L1-2\mathsf{\omega }}-{\tilde{i}}_{PN-2\mathsf{\omega }}\\ C_2\frac{\mathrm{d}{\tilde{v}}_{C2-2\mathsf{\omega }}}{dt}={\tilde{i}}_{L2-2\mathsf{\omega }}-{\tilde{i}}_{PN-2\mathsf{\omega }}\end{array}\right.$$

(18)

The impedance network is a symmetrical structure, (i.e., L₁ = L₂ = L, C₁ = C₂ = C). From Equations (17) and (18), one can write

$$\left\{\begin{array}{l}L\frac{\mathrm{d}{\tilde{i}}_{L1-2\mathsf{\omega }}}{dt}=(2D-1){\tilde{v}}_{C1-2\mathsf{\omega }}\\ C\frac{\mathrm{d}{\tilde{v}}_{C1-2\mathsf{\omega }}}{dt}=(1-2D){\tilde{i}}_{L1-2\mathsf{\omega }}-(1-D){\tilde{i}}_{PN-2\mathsf{\omega }}\end{array}\right.$$

(19)

${\tilde{i}}_{L1-2\mathsf{\omega }},{\tilde{i}}_{L2-2\mathsf{\omega }}$ are in the same phase with ${\tilde{i}}_{PN-2\mathsf{\omega }}$, while ${\tilde{v}}_{C1-2\mathsf{\omega }},{\tilde{v}}_{C2-2\mathsf{\omega }}$ are at a phase lag of 90 degrees with ${\tilde{i}}_{PN-2\mathsf{\omega }}$; thus, it follows that

$$\begin{array}{l}{\tilde{i}}_{L1-2\mathsf{\omega }}\hspace{1em}={\tilde{i}}_{L2-2\mathsf{\omega }}={\widehat{i}}_{L1-2\mathsf{\omega }}\cos (2\mathsf{\omega }t+{\mathsf{\phi }}_L)\hspace{1em} \\ {\tilde{v}}_{C1-2\mathsf{\omega }}={\tilde{v}}_{C2-2\mathsf{\omega }}={\widehat{v}}_{C1-2\mathsf{\omega }}\sin (2\mathsf{\omega }t+{\mathsf{\phi }}_L)\end{array}$$

(20)

where ${\widehat{i}}_{L1-2\mathsf{\omega }}$ and ${\widehat{v}}_{C1-2\mathsf{\omega }}$ are the peak values of 2ω ripple in the current of inductor L₁ and the voltage of capacitor C₁, respectively.

From Equations (19) and (20), the inductance and capacitance 2ω ripple expression in the impedance network can be presented by

$$\begin{array}{l}\hspace{1em} {\tilde{i}}_{L1-2\mathsf{\omega }}\hspace{1em}={\tilde{i}}_{L2-2\mathsf{\omega }}=\frac{M{I}_o(1-2D)}{4LC{\mathsf{\omega }}^2-{(1-2D)}^2}\cos (2\mathsf{\omega }t+{\mathsf{\phi }}_L)\hspace{1em} \\ {\tilde{v}}_{C1-2\mathsf{\omega }}={\tilde{v}}_{C2-2\mathsf{\omega }}=\frac{2\mathsf{\omega }LM{I}_o}{4LC{\mathsf{\omega }}^2-{(1-2D)}^2}\sin (2\mathsf{\omega }t+{\mathsf{\phi }}_L)\end{array}$$

(21)

The expression for the inductor current and capacitor voltage 2ω ripple of a conventional QZSI impedance network can be found in Equation (21). If the 2ω pulsating power in Equation (21) is made to be zero, ${\tilde{i}}_{L1-2\mathsf{\omega }} ={\tilde{i}}_{L2-2\mathsf{\omega }}=0$ and ${\tilde{v}}_{C1-2\mathsf{\omega }}={\tilde{v}}_{C2-2\mathsf{\omega }}=0$ can be realized, which constitutes the active decoupling method for the integrated third bridge leg.

2.2. Circuit Topology of the Proposed Inverter

The circuit topology of the single-phase three-leg QZSI is shown in Figure 4.

The circuit is designed to be integrated with an additional third bridge leg, which is based on a conventional single-phase QZSI. Through injecting harmonic voltage into the third leg of the bridge, the output 2ω ripple power is reduced to zero (i.e., ${\tilde{p}}_{o-2\mathsf{\omega }}=0$), thus reducing the 2ω ripple in the impedance network of inductors and capacitors to a very small value. Notably, the impedance network is still designed with symmetrical parameters, where L₁ = L₂ and C₁ = C₂.

2.3. Operating Principle of the Proposed Inverter

The single-phase three-leg QZSI has two operating states: the shoot-through state and the non-shoot-through state. In the non-shoot-through state, the upper and lower switches in the same bridge leg of the inverter conduct in a complementary manner.

Using S_T indicates the shoot-through state, while S (S_A, S_B, S_E) indicates the non-shoot-through state, where S_A, S_B, and S_E can take the value of 0 or 1, the value of 0 indicates that the switch below the corresponding bridge leg is turned on, and the value of 1 indicates that the switch above the corresponding bridge leg is turned on. The topology operating states and points A, B, and E voltage are shown in

Table 1. Operating states and voltage at points A, B and E.

State	vA	vB	vE
ST	0	0	0
S (000)	0	0	0
S (001)	0	0	VPN
S (010)	0	VPN	0
S (011)	0	VPN	VPN
S (100)	VPN	0	0
S (101)	VPN	0	VPN
S (110)	VPN	VPN	0
S (111)	VPN	VPN	VPN

.

Based on Table 1, it can be observed that the voltages at points A, B, and E, which are denoted as v_A, v_B, and v_E, respectively, only have two possible values: V_PN and 0. Using the Fourier transform, v_A, v_B, and v_E can be expressed as follows

$$\left\{\begin{array}{l}{v}_A=V_{dcA}+{\displaystyle \sum _{n=1}^{\infty }{A}_{\mathrm{n}}}\sin \left(n\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{An}}\right)\\ v_B=V_{dcB}+{\displaystyle \sum _{n=1}^{\infty }{B}_{\mathrm{n}}}\sin \left(n\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{Bn}}\right)\\ v_E=V_{dc2}+{\displaystyle \sum _{n=1}^{\infty }{V}_{\mathrm{n}}}\sin \left(n\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{Vn}}\right)\end{array}\right.$$

(22)

where V_dcA represents the DC component of the voltage at point A, while A_n represents the amplitude of the nth harmonic component of the voltage at point A. V_dcB represents the DC component of the voltage at point B, and B_n represents the amplitude of the nth harmonic component of the voltage at point B. V_dc2 represents the DC component of the voltage at point E, and V_n represents the amplitude of the nth harmonic component of the voltage at point E.

The expression of the fundamental frequency component of the output voltage is shown in Equation (10), and if the filter inductor voltage drop values are neglected, the following can be obtained

$$v_o=v_A-v_B$$

(23)

The following Equation (24) is given by Equations (10), (22), and (23).

$$\left\{\begin{array}{l}{V}_{dcA}=V_{dcB}\\ A_1-B_1=\sqrt{2}{V}_o\\ {\mathsf{\phi }}_{A1}={\mathsf{\phi }}_{B1}=0\\ {\displaystyle \sum _{n=2}^{\infty }{A}_{\mathrm{n}}}\sin \left(n\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{An}}\right)={\displaystyle \sum _{n=2}^{\infty }{B}_{\mathrm{n}}}\sin \left(n\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{Bn}}\right)\end{array}\right.$$

(24)

It can be seen that the addition of the third bridge leg does not affect the inverter output. To simplify the analysis, the following relationship is taken.

$$\left\{\begin{array}{l}{V}_{dcA}=V_{dcB}=V_{dc1}\\ {\displaystyle \sum _{n=2}^{\infty }{A}_{\mathrm{n}}}\sin \left(n\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{An}}\right)={\displaystyle \sum _{n=2}^{\infty }{B}_{\mathrm{n}}}\sin \left(n\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{Bn}}\right)=0\end{array}\right.$$

(25)

V_dc1 represents the DC component of the voltage at point A and point B.

The output filter capacitor voltage and inductor current can be written as follows

$$\left\{\begin{array}{l}{v}_{o1}=v_{AE}=-V_{dc}+A_1\sin \mathsf{\omega }t-Q_E\\ v_{o2}=v_{BE}=-V_{dc}+B_1\sin \mathsf{\omega }t-Q_E\\ i_{o1}=\mathsf{\omega }{C}_f{A}_1\cos \mathsf{\omega }t-n\mathsf{\omega }{C}_f{Q}_E\\ i_{o2}=\mathsf{\omega }{C}_f{B}_1\cos \mathsf{\omega }t-n\mathsf{\omega }{C}_f{Q}_E\end{array}\right.$$

(26)

where v_o1 and v_o2 represent the voltages across the output filter capacitors C_f1 and C_f2, respectively, while i_o1 and i_o2 represent the currents through the output filter inductors L_f1 and L_f2, respectively. C_f denotes the output filter capacitor, C_f1 = C_f2 = C_f, V_dc = V_dc2 − V_dc1, and

$$Q_E={\displaystyle \sum _{n=1}^{\infty }{V}_{\mathrm{n}}}\sin \left(n\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{Vn}}\right).$$

The instantaneous power of the output filter capacitor is given by

$$\begin{array}{cc}{p}_{2C_f}& =v_{o1}{i}_{o1}+v_{o2}{i}_{o2}\\ & =\frac{1}{2}\mathsf{\omega }{C}_f{V}_o^2\sin 2\mathsf{\omega }t+2n\mathsf{\omega }{C}_f{Q}_E(Q_E+V_{dc})\\ & -\mathsf{\omega }{C}_f{V}_{dc}(A_1+B_1)\cos \mathsf{\omega }t\\ & -(-n{V}_{dc}+1)\mathsf{\omega }{C}_f{Q}_E(A_1+B_1)\sin \mathsf{\omega }t\end{array}$$

(27)

Substituting A₁ + B₂ = 0 into Equations (24) and (27), the following results can be obtained

$$A_1=\frac{\sqrt{2}}{2}{V}_o{B}_1=-\frac{\sqrt{2}}{2}{V}_o$$

(28)

$$p_{2C_f}=\frac{1}{2}\mathsf{\omega }{C}_f{V}_o^2\sin 2\mathsf{\omega }t+2n\mathsf{\omega }{C}_f{Q}_E(Q_E+V_{dc})$$

(29)

Using $p_{2C_f}$ buffer ${\tilde{p}}_{o-2\mathsf{\omega }}$, such that $p_{2C_f-2\mathsf{\omega }}+{\tilde{p}}_{o-2\mathsf{\omega }}=0$. To eliminate ${\tilde{p}}_{o-2\mathsf{\omega }}$, only the second harmonic is retained in Q_E; therefore, Q_E can be expressed as follows

$$Q_E=V_2\sin (2\mathsf{\omega }t+{\mathsf{\phi }}_{V2})$$

(30)

Equation (31) can be obtained from the above analysis

$$\begin{array}{cc}{p}_{2C_f}& =(\mathsf{\omega }{C}_f{V}_o^2/2)\sin (2\mathsf{\omega }t)+2\mathsf{\omega }{C}_f{V}_2^2\sin (4\mathsf{\omega }t+2{\mathsf{\phi }}_{\mathrm{V}2})\\ & +4\mathsf{\omega }{C}_f{V}_2{V}_{dc}\cos (2\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{V}2})\end{array}$$

(31)

Using the 2ω pulsating power to offset ${\tilde{p}}_{o-2\mathsf{\omega }}$, the amplitude and phase of the injected second harmonic voltage can be obtained

$$\left\{\begin{array}{l}{V}_2=\frac{\sqrt{(V_{\mathrm{o}}{I}_{\mathrm{o}}\cos {\mathsf{\phi }}_{\mathrm{L}}{)}^2+(V_{\mathrm{o}}{I}_{\mathrm{o}}\sin {\mathsf{\phi }}_{\mathrm{L}}+\mathsf{\omega }{C}_f{V}_{\mathrm{o}}^2/2{)}^2}}{4\mathsf{\omega }{C}_f\left|V_{dc}\right|}\\ {\mathsf{\phi }}_{V2}=\mathrm{arc}\tan \frac{V_{\mathrm{o}}{I}_{\mathrm{o}}\sin {\mathsf{\phi }}_{\mathrm{L}}+\mathsf{\omega }{C}_f{V}_{\mathrm{o}}^2/2}{V_{\mathrm{o}}{I}_{\mathrm{o}}\cos {\mathsf{\phi }}_{\mathrm{L}}}\end{array}\right.$$

(32)

Although the 2ω pulsating power is buffered when injecting the second harmonic voltage in the third bridge leg, a new 4ω pulsating power is generated. If the third bridge leg simultaneously injects a fourth harmonic voltage, the following results can be obtained

$$\begin{array}{cc}{p}_{2C_f}& =(\mathsf{\omega }{C}_f{V}_o^2/2)\sin (2\mathsf{\omega }t)+4\mathsf{\omega }{C}_f{V}_2{V}_{dc}\cos (2\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{V}2})\\ & +2\mathsf{\omega }{C}_f{V}_2^2\sin (4\mathsf{\omega }t+2{\mathsf{\phi }}_{\mathrm{V}2})+8\mathsf{\omega }{C}_f{V}_4{V}_{dc}\cos (4\mathsf{\omega }t+{\mathsf{\phi }}_{V4})\\ & -2\mathsf{\omega }{C}_f{V}_2{V}_4\sin (2\mathsf{\omega }t+{\mathsf{\phi }}_{V4}-{\mathsf{\phi }}_{V2})\\ & +6\mathsf{\omega }{C}_f{V}_2{V}_4\sin (6\mathsf{\omega }t+{\mathsf{\phi }}_{V2}+{\mathsf{\phi }}_{V4})\\ & +4\mathsf{\omega }{C}_f{V}_4^2\sin (8\mathsf{\omega }t+2{\mathsf{\phi }}_{V4})\end{array}$$

(33)

Through setting $p_{2C_f-4\mathsf{\omega }}=0$ in Equation (33), Equation (34) can be obtained as follows

$$V_2^2\sin (4\mathsf{\omega }t+2{\mathsf{\phi }}_{\mathrm{V}2})+8\mathsf{\omega }{C}_f{V}_4{V}_{dc}\cos (4\mathsf{\omega }t+{\mathsf{\phi }}_{V4})=0$$

(34)

Based on Equation (34), the amplitude and phase of the injected fourth harmonic voltage can be obtained as follows

$$\left\{\begin{array}{l}{V}_4=\frac{V_2{}^2}{4V_{dc}} \\ {\mathsf{\phi }}_{V4}=2{\mathsf{\phi }}_{V2}-90°\end{array}\right.$$

(35)

It can be observed that injecting low-frequency harmonic voltages into the third bridge leg can eliminate the ripple power at the pre-determined frequency; however, at the same time, new frequency-dependent ripple power is generated. If a third harmonic voltage is injected simultaneously, the following results can be obtained

$$\begin{array}{cc}{p}_{2C_f}& =(\mathsf{\omega }{C}_f{V}_o^2/2)\sin (2\mathsf{\omega }t)+4\mathsf{\omega }{C}_f{V}_2{V}_{dc}\cos (2\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{V}2})\\ & +2\mathsf{\omega }{C}_f{V}_2^2\sin (4\mathsf{\omega }t+2{\mathsf{\phi }}_{\mathrm{V}2})+8\mathsf{\omega }{C}_f{D}_4{V}_{dc}\cos (4\mathsf{\omega }t+{\mathsf{\phi }}_{V4})\\ & +3\mathsf{\omega }{C}_f{V}_3^2\sin (6\mathsf{\omega }t+2{\mathsf{\phi }}_{V3})+6\mathsf{\omega }{C}_f{V}_2{D}_4\sin (6\mathsf{\omega }t+{\mathsf{\phi }}_{V2}+{\mathsf{\phi }}_{V4})\\ & +\mathsf{\omega }{C}_f{V}_2{V}_3\sin (\mathsf{\omega }t+{\mathsf{\phi }}_{V3}-{\mathsf{\phi }}_{V2})-2\mathsf{\omega }{C}_f{V}_2{V}_4\sin (2\mathsf{\omega }t+{\mathsf{\phi }}_{V4}-{\mathsf{\phi }}_{V2})\\ & +6\mathsf{\omega }{C}_f{D}_3{V}_{dc}\cos (3\mathsf{\omega }t+{\mathsf{\phi }}_{V3})+5\mathsf{\omega }{C}_f{V}_2{V}_3\sin (5\mathsf{\omega }t+{\mathsf{\phi }}_{V2}+{\mathsf{\phi }}_{V3})\\ & +7\mathsf{\omega }{C}_f{V}_3{V}_4\sin (7\mathsf{\omega }t+{\mathsf{\phi }}_{V3}+{\mathsf{\phi }}_{V4})+4\mathsf{\omega }{C}_f{V}_4^2\sin (8\mathsf{\omega }t+2{\mathsf{\phi }}_{V4})\end{array}$$

(36)

It can be deduced from Equation (36) that, in this case, the ripple power at 6th harmonic frequency can be eliminated; however, at the same time, new ripple powers at the first, second, third, fifth, seventh, and eighth harmonic are generated.

Table 2. Relationship between input current harmonic content and injected harmonic voltages.

Injected Harmonic Voltage Frequency	Input Current nth Harmonic Amplitude/Input Current DC Component
	n = 1	n = 2	n = 3	n = 4	n = 5	n = 6	n = 7	n = 8
2	0	0	0	27.92%	0	0	0	0
2, 4	0	2.35%	0	0	0	7.06%	0	0.40%
2, 3, 4	0.48%	2.35%	101.94%	0	28.67%	0	3.39%	0.40%

presents the correlation between the input current harmonic content and the frequency of the injected harmonic voltage in the additional bridge leg, with parameters set to f = 50 Hz, P = 300 W, V_i = 144 V, V_dc = 150 V, C_f = 52 μf, V_o = 110 V, and φ_L = 0. Analysis of Table 2 indicates that the harmonic content of the input current is relatively insignificant in comparison to the DC component when the additional bridge leg injects second and fourth harmonic voltages simultaneously. However, injecting second, third, and fourth harmonic voltages actually increases the ripple content of the input current. These observations reveal that injecting specific combinations of harmonic voltages can impact the harmonic content of the input current, highlighting the importance of carefully selecting the appropriate harmonic injection strategy to minimize undesirable effects on the system.

The expressions for the voltages at points A, B, and E when the additional bridge leg injects second-frequency and fourth-frequency harmonic voltages are as follows

$$\left\{\begin{array}{l}{v}_{\mathrm{A}}=V_{\mathrm{dc}1}+\frac{\sqrt{2}{V}_{\mathrm{o}}}{2}\sin (\mathsf{\omega }t)\\ v_{\mathrm{B}}=V_{\mathrm{dc}1}-\frac{\sqrt{2}{V}_{\mathrm{o}}}{2}\sin (\mathsf{\omega }t)\\ v_E=V_{\mathrm{dc}2}+V_2\sin (2\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{V}2})+V_4\sin (4\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{V}4})\end{array}\right.$$

(37)

The following relationships need to be satisfied for the shoot-through modulation signals V_com1 and V_com2.

$$\left\{\begin{array}{l}{V}_{com2}\ge V_{\mathrm{dc}1}\ge \frac{\sqrt{2}{V}_{\mathrm{o}}}{2}+V_{com1}\\ V_{com2}\ge V_{\mathrm{dc}2}\ge \left|V_2\right|+\left|V_4\right|+V_{com1}\end{array}\right.$$

(38)

Based on the above equation, when v_A, v_B, and v_E satisfy Equations (37) and (38), the inverter can simultaneously achieve boosting, inversion, and low-frequency ripple suppression of input current.

3. The Control Strategy of the Proposed Inverter

Figure 5 illustrates the control strategy employed for the single-phase three-bridge-leg of QSZI. The shoot-through state modulation is achieved using open-loop simple boost control, while constant output voltage control is employed for the two bridge-leg of H-Bridge. For the additional third bridge-leg, a control method is employed that injects specific frequency harmonic voltage and suppresses newly generated low-frequency components of the input current. The controllers utilize a quasi-PR (QPR) control strategy. The transfer function of the QPR control incorporates the transfer function of the sinusoidal signal, which is represented as ω/s² + ω². This process enables accurate tracking of the sinusoidal signal without any static errors.

Figure 6 illustrates a comparison of the Bode diagrams for the PI, PR, and QPR controllers. It is evident that the QPR controller exhibits superior bandwidth and enhanced stability, even in the presence of output target frequency perturbations, as compared to the PI and PR controller.

The amplitude–frequency characteristics of the QPR controller clearly indicate that the gain approaches zero at frequencies other than the resonant frequency point. This characteristic empowers the QPR controller with the ability to effectively suppress harmonics at specific frequencies. Figure 7 presents the structural diagram of QPR2, which is designed based on this principle.

The modulation waveforms of the system are shown in Figure 8, where the A and B bridge legs, as well as the E bridge leg, adopt independent simple Sinusoidal Pulse Width Modulation (SPWM) strategies. The modulation waveforms of the three bridge legs are represented by u_rA, u_rB, and u_rE, with a triangular waveform u_c as the carrier signal. When u_r ≥ u_c, the switches of the upper leg of the corresponding bridge leg are turned on, while the switches of the lower leg are turned off. When u_r ≤ u_c, the switches of the upper leg of the corresponding bridge leg are turned off, and the switches of the lower leg are turned on. When u_c ≥ V_com1 or u_c ≤ V_com2, the bridge leg is in a shoot-through state.

4. Parameter Design of the System

4.1. Parameter Design of Inductance and Capacitance in Impedance Network

The implementation of the active filtering technique effectively minimizes ripple power in the output power, resulting in the complete suppression of 2ω ripple on the DC side. Therefore, the inductors and capacitors in the impedance network do not need to buffer the 2ω ripple according to Equation (21), but only need to suppress the switching frequency ripple. When the inductances L₁ and L₂, as well as the capacitance C₁ and C₂ in the impedance network, satisfy the following relationship, they can suppress the switching frequency current ripple and voltage ripple, respectively.

$$\begin{array}{l}{L}_1=L_2\ge \frac{D(1-D)V_i}{2W_1{f}_s(1-2D)I_L}\\ C_1=C_2\ge \frac{I_L(1-D)V_i}{2W_2{f}_s}\end{array}$$

(39)

where W₁ denotes the percentage of current ripple at the frequency of the inductive switch, W₂ represents the percentage of voltage ripple at the frequency of the capacitive switch, W₁ is usually selected as 20%, and W₂ is selected as 1%. D denotes the duty cycle of the shoot-through, and f_s represents the switching frequency.

4.2. Parameter Design for Modulation of the Third Bridge Leg

The selection of parameters V_dc and C_f in Equation (32) is directly correlated with crucial circuit parameters, such as the input voltage level and the voltage stress on switches, which impact the overall performance of the circuit. Therefore, a more comprehensive and in-depth analysis is required to thoroughly understand the interdependence of these parameters.

Based on Equation (33), the relationship between the values of the DC bias voltages V_dc and V₂ can be obtained when S = 300 VA, C_f = 52 μf, and φ_L= 0, as shown in Figure 9. From Figure 9, it can be inferred that the value of V₂ decreases as the value of V_dc increases. Hence, it is crucial to avoid selecting an excessively small value for V_dc to prevent V₂ from becoming excessively large. Furthermore, the values of V_dc and V₂ are closely related to the magnitude of V_PN; the DC bus voltage, which is dependent on the input voltage; and the shoot-through duty cycle. As a result, the value of V_dc should also not be excessively large.

Based on the analysis, it is concluded that selecting V_dc within the range of 100 V to 200 V is more reasonable. The minimum value of V_PN is related to other parameters, as shown in

Table 3. Relationship between V_PNmin and other parameters in two schemes.

Vdc1 ≤ Vdc2			Vdc1 ≥ Vdc2
Vdc2 (V)	Vdc (V)	VPNmin (V)	Vdc1 (V)	Vdc (V)	VPNmin (V)
285.8	100	340.0	259.2	100	340.0
295.8	110	344.1	263.7	110	344.1
305.8	120	349.5	269.3	120	349.5
315.8	130	355.6	275.7	130	355.6
325.8	140	362.5	282.7	140	362.5
335.8	150	369.8	290.2	150	369.8
345.8	160	377.4	298.0	160	377.4
355.8	170	385.4	306.1	170	385.4
365.8	180	393.7	314.4	180	393.7
375.8	190	402.1	322.9	190	402.1
385.8	200	410.7	331.6	200	410.7

. It is worth noting that V_PNmin remains constant for both schemes. According to Equation (31), when the second harmonic power in the output power is cancelled out due to the second harmonic power in the p_2cf, Equation (40) can be obtained.

$$-V_o{I}_o\sin (2\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{L}})+(\mathsf{\omega }{C}_f{V}_o^2/2)\sin (2\mathsf{\omega }t)+4\mathsf{\omega }{C}_f{V}_2{V}_{dc}\cos (2\mathsf{\omega }t+{\mathsf{\phi }}_{\mathrm{V}2})=0$$

(40)

Through analysis, when V_dc1 is greater than V_dc2, the following situations occur:

When $\left|V_o{I}_o\sin {\mathsf{\phi }}_{\mathrm{L}}\right|\ge \left|\mathsf{\omega }{C}_f{V}_o^2/2\right|,\tan {\mathsf{\phi }}_{\mathrm{V}2}\le 0,\sin {\mathsf{\phi }}_{\mathrm{V}2}\ge 0,$ φ_V2 is located in the second quadrant. When $\left|V_o{I}_o\sin {\mathsf{\phi }}_{\mathrm{L}}\right|\le \left|\mathsf{\omega }{C}_f{V}_o^2/2\right|,\tan {\mathsf{\phi }}_{\mathrm{V}2}\ge 0,\sin {\mathsf{\phi }}_{\mathrm{V}2}\le 0,$ φ_V2 is located in the third quadrant.

When V_dc1 is less than V_dc2, φ_V2 is always located in the first or fourth quadrant. Therefore, it can be seen that selecting the second scheme where V_dc1 ≤ V_dc2 is more in line with the actual situation and easier to implement. Therefore, V_dc1 is chosen to be less than or equal to V_dc2, and the value of V_dc is set to 150 V.

In comparison to the conventional two-leg inverter, the three-leg inverter topology necessitates a higher DC bias value, resulting in a corresponding requirement for a higher DC bus voltage. As shown in Equations (37) and (38), the DC bus voltage needs to satisfy the following expression

$$V_{PN}\ge Max\left\{V_{dc1}+\frac{\sqrt{2}{V}_{\mathrm{o}}}{2}+V_{com1},V_{dc2}+\left|V_2\right|+\left|V_4\right|+V_{com1}\right\}$$

(41)

Since V_dc1 ≤ V_dc2, V_dc = 150 V is chosen, and one can simply write

$$V_{PN\min }=V_{dc1}+V_{dc}+\left|V_2\right|+\left|V_4\right|+V_{com1}$$

(42)

The correlation between the minimum DC bus voltage, V_PNmin, and capacitance, C_f, is presented in Figure 10 for the specific case of S = 300 VA, V_dc = 150 V, and φ_L = 0. Furthermore, Figure 10 depicts the relationship between V_PNmin and the power factor angle, φ_L, in the case of S = 300 VA, C_f = 52 uF, and V_dc = 150 V.

The selection of the injected secondary harmonic voltage V₂ should be 20 to 30% of V_dc when V_dc is chosen as 150 V. Otherwise, it will affect the boosting capability of the quasi-Z-source inverter, thus affecting the value of the DC bus voltage. From Equation (42), the relationship between the injected secondary voltage amplitude V₂ and the filter capacitor C_f can be obtained. Based on the range of values for the injected secondary voltage amplitude, the range of C_f can be determined to be 36 to 56 μF.

The results of this investigation highlight that the selection of capacitance C_f is intimately tied to both the voltage stress experienced by the switches and the overall capacity of the system. Hence, a comprehensive evaluation of these factors is crucial in determining the optimal value for capacitance C_f. If the capacitance is too large, it will significantly increase the size of the inverter and the current flowing through the capacitor, which reduces the power density of the inverter and increases the current stress on the power switching devices. Similarly, if the capacitance is too small, the demand for the minimum DC bus voltage is too high, and the voltage stress on the power switching devices increases, which limits the selection of the switching devices.

Taking into account the above analysis, a relatively appropriate range of values can be obtained, and selecting values within this range is acceptable. Finally, a capacitance value of 52 μF was selected.

5. Simulation Results

This section presents the simulation results of the proposed converter and verifies the superiority of the proposed scheme through comparing it with the conventional single-phase QZSI through simulation. A simulation model of the three-bridge-leg QZSI with input ripple suppression is developed using PSIM software (Professional Version 2022.2.0.17), and the system parameters are shown in

Table 4. System parameters.

Parameters	Values	Parameters	Values
Input voltage Vi	144 V	Output voltage Vo	110 V
Output voltage frequency f	50 Hz	Rated power P	300 W
Switching frequency fs	40 kHz	DC bus voltage VPN	576 V
Inductors L1, L2	6 mH	Output-filtering inductors Lf1, Lf2	2 mH
Capacitors C1, C2	30 μF	Output-filtering capacitors Cf1, Cf2	52 μF
Shoot-through duty cycle D	0.375	Modulation index M	0.27

.

5.1. Simulation of the System under Full Load

Figure 11 shows the waveform of circuit simulation under full load (300 W) condition with the third leg disabled, using only the passive filtering technique. The average DC-side current is theoretically calculated as 2.08 A; the voltages across capacitor C₁ and C₂ are 360 V and 216 V, respectively; and the DC bus voltage V_PN is 576 V. According to Figure 11a, it can be observed that the inductor current ripple ΔI is 1.89 A, which is 90.87% of the theoretical value. Figure 11b,c show the voltage ripples across capacitor C₁ and C₂ are 34.74 V and 35.57 V, respectively. Figure 11d shows the DC bus voltage ripple ΔV_PN is 70.75 V, which accounts for 12.28% of the theoretical value. Figure 11e is an enlarged view of the DC bus voltage V_PN, and Figure 11f is a further enlarged view of Figure 11e. When V_PN is 0, it is in a shoot-through state, and the shoot-through state duty cycle can be calculated as 0.376 from Figure 11f, which is consistent with the set value.

The Fast Fourier Transform (FFT) of the output voltage in this case is shown in Figure 12, with a Total Harmonic Distortion (THD) of 0.47%.

With the third leg enabled, the waveforms of the circuit are shown in Figure 13. Figure 11a shows that the current ripple ΔI of the inductor L₁ is 0.513 A, and Figure 13b,c show the ripples of the voltage across capacitors C₁ and C₂ ΔV are 3.3 V and 3.4 V respectively, accounting for only 0.92% and 1.57% of their theoretical values. Figure 13d shows that the ripple of the DC bus voltage ΔV_PN is 6.54 V, which is only 1.14% of its theoretical value.

The FFT analysis of the output voltage is shown in Figure 14, and the total harmonic distortion (THD) of the output voltage is only 0.04%, thus being reduced to a value close to zero. It can be seen that the engagement of the third bridge leg did not affect the output performance of the inverter.

Figure 15 shows the comparison of low-frequency current ripple in the input current before and after enabling the third bridge leg under full load conditions. It can be seen that the low-frequency current ripple in the input current is significantly reduced after enabling the third bridge leg. Specifically, the second harmonic ripple is reduced from 18.2% to 4.5%, and the fourth harmonic ripple is reduced from 16.5% to 2.1%.

5.2. Simulation of the System under Underload

Under the underload (225 W) condition, Figure 16 illustrates the circuit simulation waveform when the third bridge leg is disabled. It can be observed that the inductor current i_L1, voltage across capacitors v_C1 and v_C2, and DC bus voltage V_PN contain a high level of low frequency ripple, which can cause distortions in the inverter output voltage and current waveforms, leading to a shorter system lifespan.

The FFT of the output voltage in this case is shown in Figure 17, with a THD of 0.38%.

With the third leg enabled, the waveforms of the circuit are shown in Figure 18. From Figure 18a–c, it can be observed that the inductor current i_L1, capacitor voltages v_C1, and v_C2 contain only a small amount of low-frequency ripple. This result shows that the suppression method proposed in this paper still has a good suppression effect on the input current on the DC side under the condition of underload. The injected second-frequency harmonic and fourth-frequency harmonic voltage waveforms from the third bridge leg are shown in Figure 18d,e.

In this case, the FFT analysis of the output voltage is shown in Figure 19, and the THD of the output voltage is only 0.07%.

Figure 20 shows the comparison of low-frequency current ripple in the input current before and after enabling the third bridge leg under the condition of underload. It can be seen that the low-frequency current ripple in the input current is significantly reduced after enabling the third bridge leg. Specifically, the second harmonic ripple is reduced from 16.2% to 7.6%, and the fourth harmonic ripple is reduced from 16.3% to 4.1%.

5.3. Dynamic Simulation of the System

To assess the performance of the circuit under load disturbance conditions, the circuit is simulated from full load to under load with a transition time of 0.5 s. The simulation waveform is depicted in Figure 21. From the simulation waveforms, the following observations can be made:

(1)

When transitioning from full load to under load at 0.5 s, the inductor current i_L1 of the impedance network stabilizes quickly and maintains good low-frequency ripple suppression capability.

(2)

The output voltage v_o waveform performs as expected and fluctuates within 1 V, even during the disturbance. The voltage THD remains less than 1% throughout the process, while the output current io smoothly decreases and changes due to the increase in load.

(3)

The DC bus voltage V_PN remains stable after a short disturbance.

(4)

As the output pulsating power decreases after the load changes, the power required to buffer the third bridge leg decreases. Consequently, the amplitude of the second and fourth harmonic voltages V₂ and V₄ injected using the third bridge leg decreases, and the amplitude of the filter capacitor voltages v_o1 and v_o2 also decreases.

A comprehensive analysis indicates that the system exhibits good dynamic tracking performance when transitioning from full load to under load.

6. Conclusions

This paper proposes a single-phase quasi-Z-source inverter (QZSI) with an integrated active filter to buffer the output 2ω power through injecting a low-frequency harmonic voltage into the third bridge leg. This method minimizes the 2ω ripple on the DC side and substantially reduces the required inductance and capacitance values of the impedance network. Moreover, the paper presents a comprehensive analysis of the working principle and control methodology of the proposed circuit topology, as well as guidelines for designing its key parameters. When the third bridge leg is activated in the inverter, the simulation results show that the output voltage and current THD are less than 1%, indicating excellent output performance. Under full load condition, the input-side inductor current ripples ΔI from 1.89 A with passive filtering to 0.513 A, representing a reduction of 72.86%, and the DC bus voltage ripples ΔV_PN from 70.75 V to 6.54 V, representing a reduction of 90.76%. The second harmonic ripple of the input current is reduced from 18.2% to 4.5%, and the fourth harmonic ripple is reduced from 16.5% to 2.1%. Additionally, the closed-loop control ensures the good dynamic tracking performance of the inverter, while stable control can be achieved in a short time when the load undergoes disturbances, meeting the expected results. As a result, the proposed method only necessitates the inductor and capacitor of the impedance network to handle the switching frequency ripple. This situation significantly reduces the size of the inverter and improves the overall system efficiency. The simulation results validate the accuracy and practicality of the proposed circuit topology. In order to further reduce the volume of the inverter and make it more applicable to relevant fields, the integration of inductors in circuits will be studied in future research.