Global Simulation Model Design of Input-Serial, Output-Parallel Solid-State Transformer for Smart Grid Applications

Abstract

This paper provides an overview of an early attempt at developing a simulation model on a solid-state transformer (SST) based on input-serial and output-parallel (ISOP) topology. The proposed SST is designed as a base for a smart grid (SG). The paper provides a theoretical review of the power converters under consideration, as well as their control techniques. Further, the paper presents a simulation model of the proposed concept with a PLECS circuit simulator. The proposed simulation model examines bidirectional energy flow control between the medium-voltage AC grid and DC smart grid, while evaluating power flow efficiency and qualitative indicators of the AC grid. After the completion of design verification and electrical properties analysis by the PLECS simulation models, the synthesis offers recommendations on the optimal layout of the proposed SST topology for smart grid application.

1. Introduction

The idea of solid-state transformers (SSTs) has evolved in recent years in a variety of disciplines, including smart grids. It is a promised crucial element for future smart grids [1]. SSTs are expected to replace conventional low-frequency transformers in the smart grid because they provide efficient and more controlled bidirectional power flow control options, as well as the ability to implement functions such as reactive power compensation, short-circuit current limitation, power factor correction, harmonics compensation, voltage drop compensation, and voltage drop compensation to the distribution network as input and output frequency variability [2]. Future smart grid design and research are focused on improving the reliability, efficiency (loss reduction in smart grids), and quality of distributed power, such as short outages or prevention of voltage fluctuations [1,2]. However, SST has several drawbacks that have not yet resulted in its replacement of conventional transformers. The expense of SST in comparison to a traditional low-frequency transformer is one of the most significant drawbacks. To manage the power flow in SG, the SST requires high-voltage, high-power semiconductor switching devices. When compared to a standard transformer, it has lower efficiency and increased complexity and produces more electromagnetic interference. The efficiency can further be balanced by lower losses in the superior network, thanks to the automatic compensation of reactive energy and an overall neutral power factor.

However, due to the drawbacks of commercial transformers and the inherent benefits of SST, research in this field is presently primarily focused on the implementation and usage of SST in smart grids [3].

The growing prevalence of renewable energy sources (such as solar panels and wind turbines), energy storage devices (such as batteries and electric vehicles), and high-current loads (such as electric vehicle chargers) make power distribution networks operational [4].

The residential smart grid concept proposed in this article is based on a three-tier SST topology. The three-level SST topology is the most commonly chosen topology in research due to the intelligent properties and control strategies offered [4]. This research also proposes the HIL simulation model of proposed SST architecture. The PLECS simulator is being used to model the circuit description of the planned SST’s individual stages.

2. Materials and Methods

Currently, the most widespread is the use of a low-voltage AC supply (LVAC) for powering appliances in residential networks, although a large proportion of the devices currently in use does not require AC power to function. Most commercial and consumer devices today have a DC intermediate circuit (consumer and office electronics, switching power supplies and chargers) or can work directly on both AC and DC networks (lighting and heating technology, universal electric motors). From the point of view of energy within the microgrid, the use of a low-voltage DC supply (LVDC) to directly power consumer devices appears to be a beneficial solution. In the case of DC sources (photovoltaics, battery storage), working directly into the DC network, the min. one DC/AC transformation stage and the energy efficiency of the system as a whole increase.

The common block diagram of a SG is illustrated in Figure 1. In this paper, it is assumed that the proposed concept will supply a group of local smart homes that are connected to a micro-grid. The LVDC bus is a base for the micro-grid. In addition, the MVDC (medium-voltage DC) bus can be used to connect renewable energy sources, an energy storage system, or a DC high-voltage EV charger to the proposed concept of SG with SST [5]. This approach is attractive because it allows more precise and effective power flow control.

There are several SST topologies classified as one-tier, two-tier, and three-tier. In many SST topologies, DC or AC inputs can be converted to DC or AC outputs by changing some or all of the switches [6].

The three-stage topology is the most popular in research compared to other topologies because it offers effective power control properties [7]. In addition to reducing volume and weight, this SST can also improve the performance of distribution and transmission grids [8]. Additionally, the three-layer SST design provides on-demand reactive power support for grid, power quality, current limiting, storage management, and dual DC buses [7].

2.1. Medium-Voltage (MV) Stage of SST

Generally, the medium-voltage (MV) distribution network is the main power source for SGs. Standardized voltages used in medium-voltage distribution networks are often 10 kV or higher [9], so a multi-level topology for the first stage (medium-voltage side) of the SST is preferred when using ordinary silicon-based semiconductors [10,11,12].

For SST applications, many multilevel converter topologies have been proposed. Furthermore, given the needed number of levels, even at the lowest voltages, the selected design must deal with several critical issues, such as capacitor voltage balance and sophisticated control techniques.

Table 1. Potential medium-voltage-stage topologies and control algorithms for SST in SG [8,10,11,12].

Topology	Advantages	Disadvantages
Cascade H-Bridge	Simple control strategy and simple voltage balance control Modularity	Unachievable MVDC link
H-bridge NPC	Lower number of semiconductor switches	Complex control strategy with voltage balance control Limited modularity
Multilevel Active NPC	Modularity	Complex control strategy with voltage balance control High amount of clamping diodes
Modular Multilevel Converter	Modularity	Complex control strategy with voltage balance control
Control algorithms
Phase-Shifted PWM	Simple control: carrier pairs are assigned to individual cell	Higher losses
Level-Shifted PWM	Improved harmonic cancellation

summarizes possible SST MV-stage topologies in SG [8].

2.2. Isolated Stage of Solid-State Transformer

The low-voltage DC link is the base of a local residence’s microgrid. The microgrid voltage is set to 600 V [13]. For stepping down the MVDC bus voltage to a reliable voltage level, an isolation stage is implemented [7].

Table 2. Potential second-stage topologies and control algorithms for SST in SG [8,14,15].

Topology	Advantages	Disadvantages
Cascade H-Bridge	Simple control strategy and simple voltage balance control Modularity	Unachievable MVDC link
Single-phase Dual Active Bridge Converter	Smaller number of passive components Higher efficiency	High RMS DC capacitor currents
Three-phase Dual Active Bridge Converter	Lower RMS current Lower ratings of component	Multiple switches and inductors High losses
Bidirectional Isolated Current Doubler Topology	Higher currents Small conduction losses Smaller number of switches	Requires more inductors
Bidirectional Isolated Push–Pull Topology	High currents Smaller inductor Smaller number of switches	Complex HF transformer
Control algorithms
Phase-Shift Modulation	Simple algorithm	High losses at low power
Trapezoidal Modulation	Higher-voltage spectrum	Discontinued operation without load
Triangular Modulation	Lower switching losses	Higher RMS currents

summarize the possible topologies for the isolation stage of SST in SG applications [8].

This stage is considered one of the most difficult because it requires a lot of power to balance the high current on the low-voltage side and the high voltage on the medium-voltage side. There are two ways to meet the requirements. One is the use of HV-rated semiconductor devices, and the other is a modular approach, in which many modules are cascaded together to share all power, voltage, and current [14,15].

The modular approach has an advantage over the first option in that it emits less electromagnetic interference and allows for the use of LV-rating power devices, which increases the fault tolerance in this stage [14].

2.3. SST System Control Strategy

The control strategy of SST in SG is a complex task. The main task for the control strategy is to maintain a power balance within the SG [16]. Additionally, the control strategy should maintain MVDC, LVDC buss voltages and currents, battery management, power factor correction for MVAC and LVAC grids, control of renewable energy generators (photovoltaic panels, wind turbines, hydro turbines, etc.), operating the microgrid in the islanding mode, optimum battery management and the seamless transfer between the two operational modes, etc. [7,8,14,15,16].

There are three categories: centralized, decentralized, and hierarchical control. In centralized control strategy, the control circuit controls the three-stage SST as one converter. This central controller is connected to the microgrid via a communication link; thus, the controller relies on the data flow from the communication channel, which reduces the overall system reliability. This control approach is rarely implemented for SST-based SGs [7].

In decentralized control strategy, the converter control circuits are separated from each other, thus increasing the system reliability. To fulfill the control needs of microgrids, centralized and decentralized techniques have been used. However, given the difficult control requirements imposed on microgrids, more advanced regulating must be used [17]. Hierarchical control combines the benefits of centralized and decentralized control, allowing for more complex control objectives to be realized.

Table 3. SST’s system control strategies for microgrids [16].

Control Strategy Type	Control Purpose	Control Algorithms
Decentralized	Voltage regulation of MVDC bus	Voltage and current dq controller with PWM
	Bidirectional power flow and power factor correction at MVAC grid
	Voltage regulation of LVDC bus	PSM
	Voltage regulation of LVAC grid	D-q controller with SPWM
	Capacitor voltage balancing	PI controllers
Centralized	Complex power management	Predictive control algorithm
	Regulation of DC voltages	Phase-shift method, PWM
	Bidirectional power flow
	Voltage regulation on isolation stage	Fuzzy logic
Hierarchical	Primary control layer: decentralized control of each stage of SST	Droop control
	Secondary control layer: voltage control and management of DC links	Voltage compensation with PI controller
	Tertiary control layer: BMS (battery management system), microgrid’s power and fault management	Higher-level control

summarizes the control strategies for SST-based microgrids. In this paper, a decentralized control strategy was selected with a global power flow control.

3. Design of Proposed SST Concept

According to research in the previous section, the proposed design is based on a bidirectional input-serial output-parallel (ISOP) topology. Figure 1 represents the proposed approach of a SG based on a ISOP SST.

This paper focus on the SST part of the SG. The SST is connected to a MVAC distribution grid with a voltage level of 22 kV (Figure 2). The LVDC voltage is set to 600 V [13] for the micro-grid. The proposed concept is designed to the power level of 1 MW. This power level was determined for inspecting the highest power demand in a local group of smart residences. The control strategy is based on the hierarchical control. Each stage of the SST is controlled individually (primary layer), and the power flow is set by a higher control layer.

3.1. Design of Medium-Voltage Stage

According to previous research, a three-phase, modular, multilevel cascaded full-bridge (MMCHB) topology was selected as a MV stage of the proposed SST. This section focuses on the design of one module of this converter. Figure 3 illustrates the schematic of the MV stage. The most significant advantages of a MMCHB are modularity and simple control. The disadvantage of this converter is the additional voltage balancing control for each filter capacitor on the DC side. Yet, in comparison with a modular multilevel converter (MMC), the MMCHB divides the MVDC voltage among each module, so the topology does not require high-voltage capacitors on the MVDC side. In addition, MMCHB topologies provide lower voltage requirements for the isolation stage on the MVDC side, thus lower voltage requirements for semiconductor switches.

The required number of modules in a MMCHB depends on the total output DC voltage (Vmvdc) and the non-destructive rate of the blocking voltage of the selected semiconductor switches. The minimum value of the output DC voltage of a MMCHB can by calculated by (1).

$$V_{mvdc\_min}=V_{mvac(l-l)}·\sqrt{2}$$

(1)

It is necessary to compensate the voltage drops across filters to ensure the proper operation of the MMCHB converter [18]. This can be achieved by calculating the DC output voltage (V_mvdc) with an added tolerance. In this paper, a 10% voltage tolerance is selected, and Equation (2) calculates with this voltage tolerance the minimum output DC voltage of the MMCVHB.

$$V_{mvdc}=V_{mvdc\_min}·1.1$$

(2)

A high-voltage Silicon (SI)-based IGBT transistor with a blocking voltage (V_{BR_max}) of 4.5 kV is used as the semiconductor switches for the proposed MMCHB converter.

The minimal number of modules for the converter is determined with the following Equation (3).

$$N\_sm\ge \frac{V_{mvdc}·y}{V_{BR\_max}}$$

(3)

where y refers to a safety factor that assumes the additional voltage across the IGBT impacted by leakage inductances [19]. In this paper, a safety factor of 1.2 is selected. Equation (4) determines an output DC voltage in one module of the converter.

$$V_{mvdc\_sm\_max}=\frac{V_{mvdc}}{N_{sm}}$$

(4)

For analysis of the current behavior, assume a connection of two full-bridge modules, creating a five-level MMCHB converter; see Figure 4. The current through semiconductor switches in any module of MMCBH can be described as a time-dependent binary switching function, s(t) ∈ {1, 0}, assuming that the switches are ideal, and the input AC current describes a sinusoidal time waveform due to filter circuits. Under these assumptions and this analysis of the MMCHB converter, it is possible to identify the conductivity of each switching transistor.

$$i_{C1}=[s_1\left(t\right)-s_2\left(t\right)]·i_0\left(t\right)$$

(5)

$$i_{C2}=[s_3\left(t\right)-s_4\left(t\right)]·i_0\left(t\right)$$

(6)

The output DC currents (i_C1 and i_C2) are described in (5) and (6). The total current i₀(t) is obtained by the superposition of the time-varying partial switching currents ic_1-2 (t) from each module of the MMCHB converter [20].

In order to control the two-way power flow of a MMCHB converter, a direct vector control strategy was selected and proposed in this paper. The task of the control circuit is to generate the required amount of active power into the MVAC grid, as well as the DC bus, depending on the direction of the energy flow [21].

At the same time, the control circuit maintains the average value of the MVDC voltage of the DC filter capacitors at a defined constant level. Figure 5 shows the control circuit, which consists of an outer and an inner loop. The outer loop consists of a voltage regulator that compares the reference value with the measured average value of the voltage on the capacitors and provides a reference value for the inner current loop through a discrete PI regulator with an anti-wind-up. The inner current loops are implemented in separate current i_d and i_q controllers. The transformation functions from “abc” to “α-β”, “q-d”, and vice versa are synchronized with the AC network via a three-phase, decoupled, double synchronous reference frame (DSRF)-type phase-locked loop (PLL) [21].

The decoupled double synchronous reference frame PLL makes use of two synchronous reference frames that rotate at positive and negative synchronous velocities. This permits the influence of the negative sequence component on the dq-signals to be decoupled. This is especially important when synchronizing to non-ideal grids, such as those with unbalanced voltage characteristics. Because the double-frequency ripple induced by the unbalanced grid situation is avoided, a greater control bandwidth may be set in comparison to the basic PLL, such as the synchronously rotating reference (SFR) PLL.

The reference value of the d-axis component comes from the voltage regulator, while the reference value of the q-axis component is directly calculated from the required reactive power. The outputs of the discrete current regulators in the d-q system are back-transformed into the α-β system and further transformed into the three-phase system. Subsequently, the back-transformed quantities are divided by the sum of the voltages of the capacitors of one phase. The resulting values are further used as reference indexes for the voltage balance block on the output capacitors.

To guarantee a homogeneous distribution of the required power from the MVAC grid among all the capacitors of the MMCHB converter, it is necessary to adjust the modulation indexes of individual modules so that they differ from the preset value provided by the external control loop. The voltage balancing of the DC filter capacitors is implemented in two steps [20]. In the first step, the controller individually maintains the voltage value on the 16 cells (modules) in each branch at average value, while in the next step, the controller ensures that the mean voltage value on all capacitors in 1 branch is equal to the mean voltage value of all legs.

The switching signals of full-bridge converters in each module are generated as a result of comparing the modulation index with a triangular reference signal with a frequency of 10 kHz. For each leg, the triangular carrier signal, for modules 1 to 16, is phase-shifted by 22.5°. In this way, a 17-level output voltage can be achieved, which significantly reduces the amount of harmonic distortion generated by the MMCHB converter to the MVAC distribution grid.

3.2. Design of Isolated Stage

According to previous research on isolated stages, the dual active bridge (DAB) converter was selected. The advantages of DAB are high efficiency, high power density, the possibility of bidirectional power flow control, soft switching at zero voltage (ZVS), and lower stress on semiconductor switches [22,23]. Figure 6 shows the DAB topology, which consists of two bridge converters and a high-frequency transformer (HFT).

The input of the isolated stage is connected to the output of MVDC busses of the MMCHB converter. The output of the isolated stage forms a common LVDC bus with a required value of 600 V. The LVDC bus represents the base for the microgrid for local smart residences. Output inverters (1 or 3 phase), electric energy storage (BSS, EV), or renewable sources (PV, WG) can then be connected to this network as needed.

The HFT serves to accumulate the energy in the leakage inductances, and the air gap of the DAB primary side is connected to the MVDC bus of one module of the MMCHB converter. The DAB secondary sides are connected in parallel between all modules and phases.

The transmitted power can be defined by (13), where d is the ratio of the phase shift of the primary and secondary parts, n is the turns ratio of the HFT, T is the period, and L_LK is the stray inductance of the HFT.

$$P=V_{out}{·I}_{out}=\frac{(1-|d\left|\right)·d·T·V_{in}·V_{out}}{n·L_{Lk}}$$

(7)

Equation (7) represents the dependence of the transmitted power as a function of the phase shift between the primary and secondary sides, a function of the switching frequency, and the leakage inductance. According to (7), it is possible to derive the desired value of the leakage inductance as follows:

$$L_{Lk}=\frac{(1-|d\left|\right)d{V}_{in}{V}_{out}}{2f_{s}n{P}_{max}}$$

(8)

The phase-shift method was chosen to generate the control PWM signal. The value of the phase-shift ratio “d” between the primary and secondary sides will not only determine the magnitude, but also the direction of the power flow.

Changing the control pulses of the secondary side by a positive value of “d” will ensure the power flow from the primary to the secondary side, while in this mode, the control pulses for the switches of the primary side S1,4 and the secondary side S5,8 are taken into account [24,25].

Similarly, with a negative value of ‘d’, the power flow is supplied from the secondary to the primary side. The control system is shown in Figure 7 and consists of an outer and an inner loop for both power flow directions. The outer loop consists of a voltage discrete PI type regulator and the inner loop consists of a current discrete PI regulator. The output of the current regulators represents the modulation index for the phase-shift PWM generator. Subsequently, for the control of the modular DAB, the PWM signals are interleaved with each other.

3.3. Filter Design

Higher harmonics, which are generated by the switching of high-power semiconductor converters, are a major factor causing negative issues for connected sensitive loads within the common grid. A suitably designed filter reduces the higher harmonics of the current flow while power semiconductor switches operate in high-frequency switching mode. For higher-power applications, in addition to the appropriate choice of filter type, the price and overall total harmonic distortion (THD) are also important factors during the design [26,27]. For these facts, L, LC, or LCL filters are usually connected between the AC grid and the power semiconductor converters; see Figure 8. The LCL-type filter has a higher damping quality of higher harmonics and better dynamic characteristics compared to the LC-type filter [27].

However, the LCL filter type causes stability problems due to its unwanted natural resonance behavior, which is caused by the impedance of the grid and the impedance of the filter capacitor at certain frequencies (natural resonance of the LC elements). Further, reactive power requirements can cause unwanted resonance between the capacitor and the AC grid.

For this reason, it is necessary to minimize the resonance. This can be achieved with active or passive damping techniques. In this paper, a passive damping was selected. The passive damping is achieved by connecting a series resistance to the filter capacitor [27].

The first step in the design of the LCL-type filter is to determine the values of the inductances of coil L₁ on the AC grid side and L₂ on the converter side. These coils serve to dampen the ripple of the output current. According to the standard IEEE Std 1515-2000, the ripple of the output current is specified to a value of 20% of the nominal value of the output current (see relation (9)) [28].

$${∆I}_{L_{max}}=\frac{0.02·P}{3·V_{mvac\_RMS}}$$

(9)

where P represents the active power of the converter, and V_{mvac_RMS} represents the RMS value of the input voltage of the AC grid. The total inductance L_tot of the LCL filter is determined by Equation (10), where N is the number of modules per leg, and f_sw represents the switching frequency.

$$L_{tot}=\frac{V_{mvdc}}{N·f_{sw}·{∆I}_{L_{max}}}$$

(10)

The determination of L₁ and L₂ is shown in Equations (11) and (12), where L_g represents the inductance of the MVAC grid.

$$L_{1f\_mvac}=\frac{L_{tot}}{2}$$

(11)

$$L_{2f\_mvac}=L_{1f\_mvac}-L_{g\_mvac}$$

(12)

The design of the filter capacitor for one phase depends on the reactive power attenuation requirement. It is common practice that the value of the reactive power (Q) absorbed by the filter capacitor is limited to 5% of the nominal power. The value of the filter capacitance C_{f_mvac} can be determined by Equation (13).

$$C_{f\_mvac}=\frac{0.05·Q}{3·U_{mvac\_ef}^2·2·\pi ·f_g}$$

(13)

The resonant frequency of the LCL-type filter must be higher than the grid frequency (f_g) and, at the same time, must have at least half the value of the switching frequency f_sw. The resonant frequency (f_res) of the LCL-type filter is determined by (14). This equation is derived from Thomson’s relation of the LCL circuit.

$$f_{res}=\frac{1}{2·\pi }·\sqrt{\frac{L_1+L_2}{L_g·L_2·C_f}}$$

(14)

$${\omega }_{res}=2·\pi ·f_{res}$$

(15)

The value of the damping resistor can be determined by (16), where ω_res represents the angular resonant frequency of the LCL filter (15). The disadvantage of the passive damping technique is the increase in the losses by the added damping resistor, which reduces the overall efficiency of the converter [27].

$$R_{sd}=\frac{1}{3·{\omega }_{res}·C_f}$$

(16)

When designing a filter capacitor for DC busses, the nominal power (P), the grid frequency (f_g), the DC voltage ripple (Δu), and the DC voltage per module (V_{mvdc_sm}) are considered [27]. The minimum capacitance of the DC filter is determined in (17), while we considered the value of a voltage ripple of 10% of V_{mvdc_sm}.

$$C_{f-min}=\frac{\frac{P}{3 · N\_sm}}{2·\pi ·f_g·∆u·V_{mvdc\_sm}^2}$$

(17)

4. Global Simulation Model Design for HIL Analyses

In this part of the paper, the simulation model implementation of the proposed SST concept as a base for smart grids is described. Next, the simulation analysis of two possible operational scenarios are performed.

Figure 9 shows the principal block diagram of the SST concept and the circuit schematic of one SST module. The simulation model is designed in the PLECS circuit simulation environment. Figure 10 shows one module of the proposed concept in the PLECS circuit simulator. From Equation (3), the number of modules per phase is 16, thus the total number of modules is 48.

The model of the one SST module from Figure 9 or Figure 10 consists of three full-bridge connections. The first full-bridge (FB) with switches S_1–4 represents one module of the MMCHB converter and also the MV-side input of one SST module. The second FB with switches S_5–8 represents the high-voltage primary side of a DAB converter. Between the first and second full-bridges, an intermediate MVDC bus is located per every module. This MVDC bus is design to a maximum voltage level (V_{MVDC_sm_max}) of 3.7 kV, according to Equation (4). The third FB with switches S_9–12 represents the low-voltage secondary side of the DAB converter and also the LV-side output of one SST module. The inputs (MV-side connections) of all modules are connected in series within one phase. The outputs (LV-side connections) are connected in parallel within the three phases, thus creating a LVDC-bus as a base for smart grids. The specifications of the simulation model are recorded in

Table 4. Specifications for MV stage of proposed SST.

Parameter	Value
Pnom	1 MW
VMVAC(RMS)	22 kV
VMVAC(l-l)	38.105 kV
Itotal(RMS)	45.45 A
fsw(MMCHB)	10 kHz
VMVAC(p-p)	53,889 kV
VMVDC_max	59,278 kV
VMVDC_sm_max	3.7 kV
Lg_AC	5 μH
L1f_AC	55,578 mH
L2f_AC	55,578 mH
Cf_AC	109,611 pF
CMVDC_sm	24,207 μF

and

Table 5. Specifications for isolated stage of proposed SST.

Parameter	Value
Pnom_sm	20,833 kW
Ism_max	5.63 A
VMVDC_sm_max	3.7 kV
fsw(MMCH)	25 kHz
LLK	86.4 μH
CDAB_MVDC_sm	94.5 pF
CDAB_LVDC_sm	35,957 μF

.

Figure 11 shows the control circuit for the DAB converter, and Figure 12 shows the control circuit for the one-phase, five-level MMCHB converter. The control circuits were designed according to the previous research described within this paper. As a merit of the performance evaluation, the power factor (PF), system efficiency, and total harmonic distortion (THDi) have been analyzed during various operational scenarios.

During development of the simulation model, the focus of the control strategy and the implementation of the proposed SST concept described earlier in this paper are considered. Therefore, linearized IGBT and MOSFET models and a magnetic model of a high-frequency transformer were utilized within the simulation model [13]. This approach reduces the requirements for the computation time, while it enables HIL tests, as well. The proposed concept consists of 384 IGBT and 192 MOSFET transistor switches.

5. Results

This section deals with the evaluation of the simulation results. The simulation model was evaluated for two operational scenarios. In the first scenario, which is shown in Figure 13, the maximum limit of the transmitted power is set to 1 MW, and the power flow direction is set from the MVAC grid to the LVDC bus.

Figure 14, Figure 15 and Figure 16 show the main parameters of the investigated ET concept, i.e., Figure 14 shows the voltages, currents and the active and reactive power of the MVAC grid (U_MVAC, I_MVAC, P_MVAC, Q_MVAC). Figure 15 shows the voltages and currents of the MVDC and buss in all modules (U_MVDC, I_MVDC), and Figure 16 shows the voltage, current, and power of the common LVDC bus (U_LVDC, I_LVDC, P_LVDC). Furthermore, an evaluation of the power factor (PF), total system efficiency (${\mathrm{ɳ}}_{total}$), and total harmonic distortion of current (THD_i) was taken into account in this paper; see (18–20).

$$PF=\frac{P_{out}}{U_{out}·I_{out}}$$

(18)

$${\mathsf{ɳ}}_{total}=\frac{P_{out}}{P_{in}}·100\%$$

(19)

$${THD}_i=\frac{\sum _{i=n}^{\infty }{I}_{out i}}{I_{out 1}}$$

(20)

Table 6. Qualitative parameters of proposed concept for first operational scenario.

Parameter	Value
VLVDC	600.12 V
ΔVLVDC	0.38 V
ILVDC_sm	1667.09 A
ΔILVDC_sm	0.105 A
VMVDC_sm	3367.92 V
ΔVMVDC_sm	0.782 V
IMVDC_sm	5.631 A
ΔIMVDC_sm	0.612 A
VMVAC(RMS)	22 kV
PF	0.999
$\mathsf{ɳ}$celk	91.68%
THDi	1.779%

lists a summary of the qualitative parameters of the proposed concept in the steady state for the first operational scenario. Based on this simulation result, the concept shows a total efficiency of 91.68% and the THD_i of 1.779%. The voltage ripple on the LVDC side reached a level of 0.38 V and a current ripple of 0.105 A. The low voltage and current ripple at the LVDC bus are achieved from the ISOP topology of SST.

For the second scenario, which is shown in Figure 17, the maximum limit of the transmitted power is set to 1 MW, and the power flow direction is set from the LVDC bus to the MVAC grid. Figure 18, Figure 19 and Figure 20 show time-waveforms of the main parameters of the investigated SST concept.

Table 7. Qualitative parameters of proposed concept for second operational scenario.

Parameter	Value
VLVDC	600 V
ΔVLVDC	0.43 V
ILVDC_sm	1633.7 A
ΔILVDC_sm	0.755 A
VMVDC_sm	3369.68 V
ΔVMVDC_sm	4.026 V
IMVDC_sm	6.626 A
ΔIMVDC_sm	1.461 A
VMVAC(RMS)	22 kV
PF	0.999
$\mathsf{ɳ}$tot	92.351%
THDi	1.869%

lists a summary of the qualitative parameters of the proposed concept in the steady state for the second scenario. In this paper, the LVDC bus model was represented as a voltage source. Based on this simulation result, the concept shows a total efficiency of 92.351% and a THD_i of 1.869%. The voltage ripple on the LVDC side reached a level of 0.43 V and a current ripple of 0.755 A. The low voltage and current ripple at the LVDC bus are achieved from the ISOP topology of SST.

The total system efficiency of the presented model reached an average value of 92.02% in the steady state, the average THDi value is 1.82%, and the power factor value is close to 1 in both operational scenarios. The V_{MVDC_sm_max} value is 3368.64 V on average for both operational scenarios, which is below the calculated value from (4). This 10% safety tolerance is implemented to ensure the unwanted high-voltage fluctuations that can destroy the semiconductor switches.

6. Conclusions

In this paper, a review of possible topologies and control algorithms of SST in SG was described. Based on previous research, a possible concept of SST for SG application was determined, designed, and verified with a simulation model. The proposed concept is based on ISOP topology. The concept consists of two stages. The MV stage is based on an MMCHB converter, and the isolation stage consists of modular DAB converters. The MVDC busses of the MMCHB converter are connected to the HV sides of each DAB module. The LV sides of DAB modules are connected in parrel, forming the base of the micro-grid for a local group of smart residences. For verification of the designed concept, a simulation model was implemented in the PLECS circuit simulator. During the verification, both power flow directions of the proposed concept were evaluated. The advantage of utilizing a piecewise linear simulator (such as the PLECS circuit simulator) is the capability to simulate and study the behavior of complex converter systems (such as SSTs) as a real-time system within a reasonable simulation time. The possible disadvantage of the proposed solution in comparison with the listed topological solutions is a higher number of semiconductor switches, HVTs, and filter capacitors in MVDC buses, which leads to additional complex balancing algorithms. Another disadvantage of ISOP topology lies in cases when a short-circuit failure of one module occurs. This scenario leads to higher stress levels in the other modules and could be analyzed in the future to improve the design of the proposed SST solution.

This work presented an implementation of a decentralized control strategy with a global power flow control. In future work, this approach can be used as a base for a more complex and reliable hierarchical control strategy. Although the proposed concept of an SST-based smart grid gained low voltage and current ripples and good efficiency in simulation results, there is room for further development and additional improvements. One of the areas of investigation is the known relevant behavior of the SST-based smart grid and its control strategies in various operating situations, or the investigation of critical operating condition occurrences.