Overview of Signal Processing Problems in Power Electronic Control Circuits ^†

Abstract

This paper examines various aspects related to digital signal processing in digital control circuits used in power electronics. The discussion focuses on several common issues, including the sampling rate of signals (including phenomena such as aliasing and synchronization), coherent sampling, jitter of sampling pulses, sequential versus simultaneous sampling in multichannel systems, signal resolution (including signal-to-noise ratio, noise-shaping circuits, and changes in sampling speed), interpolation and decimation, and the conversion of analog circuits into digital form. One of the key contributions of this paper is the introduction of a new formula for calculating the resultant signal-to-noise ratio for three-stage digital control circuits. By carefully considering and correcting for sources of error, it is possible to increase the signal-to-noise ratio and minimize distortion components. This, in turn, leads to improved output/input current and voltage parameters, which can have a positive impact on the overall quality of energy processing in power electronic circuits.

1. Introduction

In the past, the conversion of electricity from one form to another was mainly reserved for industrial installations. Currently, with the increasing dependence of modern civilization on electricity, electricity conversion is very widespread and concerns us all. Power electronics devices that convert electricity from one form to another are everywhere these days. Starting with mobile phone chargers, power supplies for computers, electric drive systems, electric cars, electric car charging stations, and photovoltaics, we could go on for so long. Therefore, it can be said that power electronics are now very important for the current civilization. Consequently, the number of publications devoted to power electronics is enormous (e.g., [1,2,3,4,5,6,7,8,9,10]), and similarly, many publications describe problems of digital signal processing (e.g., [11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27]). Only a few publications describe digital signal processing in the context of power electronics [28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47].

In the paper, there is a review of the impact of selected aspects of signal processing on energy conversion by power electronic circuits. This paper is a revised and extended version of the author’s conference paper [26].

Power electronics and digital signal processing are two closely related fields, yet only a few publications describe digital signal processing in the context of power electronics. In this paper, selected aspects associated with the design and applications of digital signal processing in power electronic control circuits are discussed. Control of power electronic circuits requires great care and attention from the circuit designer, as errors in the control system can lead to a complete failure of the system.

Unfortunately, many poorly designed digital control circuits have been reported in the literature, where interference and a high noise level occur, despite not being predicted in simulations. To avoid such problems, the following aspects of digital control circuit design are presented: signal sampling rate, synchronization, signal resolution, changing of sampling speed, and conversion of analog circuits to digital form.

Understanding these aspects can greatly influence the parameters of input/output voltages and currents, leading to highly reliable power electronic circuits.

An example of such a system includes a 12-bit analog-to-digital (A/D) converter, a floating-point digital signal processor (DSP), an 8-bit pulse width modulation (PWM) output, and a sampling speed that is only slightly faster than twice the maximum signal frequency.

Despite the prevalence of fully digital control circuits, many papers still present analog control algorithms that are then implemented digitally, often overlooking key aspects associated with the transformation and implementation of digital circuits. To prevent such issues, the author has identified and presented several crucial aspects of digital control circuit design:

(a)

Signal sampling rate: This includes considerations such as aliasing, sequential vs. simultaneous sampling in multichannel systems, and the jitter of sampling pulses.

(b)

Synchronization: This involves coherent sampling.

(c)

Signal resolution: This includes the signal-to-noise ratio and the noise-shaping circuit.

(d)

Changing sampling speed: This includes interpolation and decimation.

(e)

Conversion of analog circuits to digital form.

All of these aspects can significantly affect the parameters of input/output voltages and currents in digital control circuits.

2. Power Electronic Circuit

Power electronic systems are widely used for the control and conversion of electric power. A typical block diagram of such a system is shown in Figure 1. It consists of a power electronic circuit, which includes electronic switches such as IGBTs, MOSFETs, capacitors, magnetic components, and a digital controller. The control algorithm is implemented in the digital controller, which is responsible for controlling the operation of the power electronic circuit [28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47].

The digital controller uses digital signal processing techniques to process the input signals, generate control signals, and control the output of the power electronic circuit according to the desired performance criteria. This allows for precise control of the power electronic circuit and efficient conversion of electric power for various applications such as motor drives, renewable energy systems, and power supplies.

The use of digital controllers in power electronic systems has greatly improved the performance, reliability, and flexibility of these systems, enabling advanced control strategies and enhanced functionalities.

Figure 2 shows an instance of a power electronic circuit that utilizes an open-loop multirate digital control circuit. This type of circuit is commonly used in control systems for DC/DC, DC/AC, AC/DC, and AC/AC converters, as well as active power filters, among other applications [37,42]. An open-loop system was chosen due to its ease of analysis.

It is important to note that the closed-loop circuit should also be considered, where feedback from the output is used to adjust the system’s parameters. This feedback loop can greatly improve the system’s stability and accuracy. However, closed-loop systems are often more complicated to design and analyze than their open-loop counterparts.

In this circuit (depicted in Figure 2), the analog input signal x(t) is first converted to a digital signal x(n) by an analog-to-digital (A/D) converter, which operates at a sampling ratio of f_s1 and has a bit resolution of b₁. The digital signal is then processed by a digital control algorithm implemented on a digital signal processor (DSP), which has a bit resolution of b₂ and operates at a sampling ratio of f_s2. Finally, the output control signal y(n) is transferred to a digital pulse width modulator (PWM) with a bit resolution of b₃ and a sampling ratio of f_s3. The PWM controls the output power switches S₁ and S₂, which operate at a switching frequency of f_c. The digital PWM, along with an analog output filter L_C, C_C, functions as a power digital-to-analog (D/A) converter that converts energy from a DC source to the output.

Nowadays, there are numerous options for A/D converters and DSPs that allow for the selection of circuits with adequate parameters, including b₁, b₂, f_s1, and f_s2. However, the last stage, which involves the digital PWM (Figure 3), can still be a bottleneck for the entire system, particularly for high resolutions such as those required for a high-quality power audio amplifier (e.g., f_s3 = 44.1 kHz and b₃ = 16 bit). The clock frequency of PWM counters can be calculated as follows:

$$f_h=f_{s3}{2}^{b_3}\approx 2.89\mathrm{GHz}$$

(1)

The required clock frequency is too high for typical digital circuits, necessitating a reduction in the resolution of the digital PWM, which results in a decline in the signal-to-noise ratio. This paper proposes a solution to this problem.

Microcontroller manufacturers noticed this problem and began to equip microcontrollers with high-resolution PWM (HRPWM). For example, the TMS320F28379D microcontroller uses an HRPWM chip with a resolution of 150 ps to 350 ps [48]. Which theoretically corresponds to a clock frequency of 2.9 GHz to 6.7 GHz. However, this is not such a precise resolution, because it is obtained partly in an analog way.

3. Selected Signal Parameters

From the point of view of the operation of the entire power electronic circuit, it is important to obtain the required parameters of input and output voltages and currents. The quality of the output voltage and current of the power electronic circuit is a critical concern, and the following signal parameters should be taken into account: the signal sampling ratios (f_s1, f_s2, and f_s3), signal resolutions (b₁, b₂, and b₃), transistor switching frequency (f_c), total harmonic distortion ratio (THD), output signal-to-noise ratio (SNR), and output signal-to-noise and distortion ratio (SINAD) [37,49,50,51,52,53]. The required SINAD value of the output current or voltage of a power electronic circuit depends on the application. For instance, a SINAD value of 30 dB may be sufficient for a battery charger, while a high-quality class-D audio amplifier may require a SINAD value of over 100 dB. As such, the parameters of digital control systems for power electronic circuits can vary greatly.

Figure 4 shows the amplitude spectrum of an example sinusoidal signal with a fundamental frequency of f₁. As you can see in the figure, the signal contains harmonics and noise. In order to determine the parameters of such a signal, the following parameters are considered: SNR, SINAD, signal dynamic range (DR), signal headroom, and THD should also be added.

3.1. SINAD

The previous paragraphs have discussed only linear circuits, but in practice, it is always possible to encounter nonlinearity; hence, it is crucial to take into account the influence of harmonics on signal dynamics. The parameter which completely describes the space between the signal and interference is the signal-to-noise and distortion ratio (SINAD) [37,49,50,51,52,53]. SINAD is the ratio of the wanted signal (the fundamental) to the sum of all distortion and noise products after the DC term is removed. SINAD is a measure of the quality of a signal, defined as follows:

$$SINAD=10\log \left(\frac{P_x}{P_d+P_n}\right)=10\log \left(\frac{P_x}{P_n+{\displaystyle \sum _{k=2}^K{P}_{dk}}}\right)$$

(2)

where P_x, P_n, and P_d—averages of the resultant power values of the signal, noise, and distortion components, respectively.

3.2. SNR

The signal-to-noise ratio (SNR) is defined as the ratio of the power of a signal (meaningful input) to the power of background noise:

$$SNR=10\mathrm{l}\mathrm{o}\mathrm{g}\left(\frac{P_x}{P_n}\right)$$

(3)

where P_x and P_n—averages of the resultant power values of the signal and noise.

3.3. DR

The dynamic range of a signal processing system can be defined as the ratio of the maximum signal level sustainable without overflow (or other distortion) to the minimum signal level:

$$DR=20\log \left(\frac{\left|X_{max}\right|}{\left|X_{min}\right|}\right)$$

(4)

where |X_max|—maximum amplitude of the signal (in digital systems, typically the most significant bit, MSB, is used) and |X_min|—minimum amplitude of the signal (the least significant bit, LSB, in digital systems).

3.4. THD

This is another parameter characterizing the quality of the signal: total harmonic distortion (THD). It determines the ratio of the effective harmonic value to the effective value of the signal:

$$THD=\frac{\sqrt{U_2^2+U_3^2+U_4^2+\dots }}{U_1}$$

(5)

where U₁—amplitude of the fundamental component and U₂, U₃, and U₄ …—amplitudes of the harmonics.

4. Signal Sampling

In a control system that uses uniform sampling, a continuous analog signal is sampled at discrete intervals of T_s = 1/f_s. It is crucial to carefully choose the sampling frequency f_s to ensure an accurate representation of the original analog signal. The sampling frequency should be at least twice the highest frequency f_b of the analog signal [54,55,56,57,58]. Increasing the number of samples taken (i.e., higher sampling rates) results in a more accurate digital representation, while reducing the number of samples (i.e., lower sampling rates) can lead to critical information loss.

In classical systems, for an analog signal band of 0…f_b, the Nyquist frequency (f_s/2) is only slightly higher than f_b. In sampled data systems, the input signal’s spectrum is folded around a frequency that is one-half that of the sampling clock. Figure 5 shows the spectrum of a sampling process with aliasing phenomena. An ideal input low-pass anti-aliasing filter (Figure 2) should pass all signals in the band of interest and block all signals outside of that band. The quality of the input anti-aliasing low-pass filter is a significant factor that contributes to the quality of a digital signal. The attenuation in the stop-band (for frequency f > f_b) of the input anti-aliasing filter depends on the required SNR:

$$SNR=10\log \left(\frac{P_x}{P_a}\right)$$

(6)

where P_x—power of the signal and P_a—power of aliasing components.

4.1. Oversampling

In the past, digital systems operated by sampling analog signals at frequencies close to the maximum signal frequency. This meant that the analog input and output filters needed to meet very high requirements. However, with the advancement of technology, digital systems are becoming faster and faster, making it easy and cost-effective to increase the sampling rate [12,13,14,21,22,37]. This, in turn, reduces the requirements for the analog input and output filters. Oversampling is a technique used to achieve this. In oversampling, the signal with a frequency band of 0 … f_b is sampled at a frequency much higher than 2f_b. The oversampling ratio (R) is calculated using the following equation:

$$R=\frac{f_s}{2f_b}$$

(7)

In oversampling, the sampling frequency (f_s) is chosen to be much higher than twice the bandwidth of the signal (2f_b), resulting in a higher oversampling ratio (R). This allows for more samples to be taken within the bandwidth of interest, resulting in a higher-resolution representation of the signal.

The utilization of oversampling in a system, as demonstrated in Figure 6, can result in analog filter characteristics that are softer, thereby lowering the complexity and cost associated with such filters. This reduction in filter requirements, in turn, can lead to an improvement in the performance of the control system and a decrease in overall system cost. The use of oversampling also has the potential to increase the resolution of the digital system, which can enable more accurate signal control and measurement.

By increasing the oversampling ratio, the requirements for the analog input and output filters can be reduced. This is because the higher sampling rate captures more information about the signal, including higher-frequency components that may have been filtered out in lower oversampling ratios. This can result in improved signal-to-noise ratio and dynamic range in the digital system, without the need for complex and expensive analog filters.

Oversampling is a technique commonly used in modern digital systems, such as audio and video processing, data communication, and sensor applications, to achieve higher accuracy and performance while reducing the requirements on analog components.

4.2. Simultaneous Sampling

In systems, it is often necessary to covert several analog signals. For example, if current and voltage are being converted, it should be performed at the same sampling time. Therefore, in multichannel systems, it is very important that the input signals are simultaneously sampled to reduce amplitude and phase errors. In analog input design, the A/D converters have two very common architectures: one using multiplexed (sequential) and the other using simultaneous sampling solutions [37,49,50]. Figure 7 shows two examples of systems for measuring current and voltage, one with simultaneous sampling (Figure 7a) and the other with sequential sampling (Figure 7b).

Multiplexed architectures use one A/D converter for many channels. A sampling illustration of two analog signals is depicted in Figure 8. The main disadvantage of a sequential-sampling A/D converter is the time delay between different channel samples.

The maximum error value of the amplitude of a sinusoidal signal can be calculated by the following formula [37]:

$$\mathsf{\Delta }{U}_{max}{=2A_F\mathit{sin}\left(-\pi f{t}_c\right)}_{}$$

(8)

where f—sinusoidal signal frequency, t_c—the time delay between sample impulses, and A_F—amplitude of the sinusoidal signal.

The best solution is to use a simultaneous sampling A/D converter, in which samples are taken at the same moment in time. The benefits of simultaneous sampling compared to sequential sampling include less jitter, higher bandwidth, less channel-to-channel crosstalk, and less settling time. However, if simultaneous sampling is not possible to implement, the sequential sampling A/D converter with time alignment has to be implemented instead.

For a b-bit system with sequential sampling, assume that the signal error should be less than half LSB [37].

$$\left|\Delta U_{\mathit{max}}\right|\le 0.5\frac{A_F}{2^{b-1}}$$

(9)

Assuming that t_c << 1⁄f, the time delay between sample impulses should be less than [6].

$$t_c\le \frac{1}{\pi f{2}^{b+1}}$$

(10)

For a b-bit system with sequential sampling, assume that the signal error should be less than half LSB [6].

The problem of the advantages of simultaneous sampling has also been noticed by leading manufacturers of microcontrollers. For example, the TMS320F283xx family of microcontrollers from Texas Instruments has been equipped with four A/D converters that allow simultaneous sampling of four analog signals [48]. Of course, it would be good if microcontrollers with six A/D converters were developed, allowing simultaneous measurement of three currents and three voltages in three-phase systems. However, even four converters allow the implementation of the three-phase active power filter (APF) control system [59].

4.3. Synchronization of the Sampling Process

The coherence of sampling (when f_s = kf, where k—integer) has a significant impact on the behavior of digital signal processing algorithms such as the discrete Fourier transform (DFT) [37,60,61,62]. An exemplary spectrum of a coherently sampling sinusoidal signal is depicted in Figure 9a. When sampling is not coherent, it can cause spectral leakage, resulting in unwanted phenomena as depicted in Figure 9b. Therefore, the author suggests that synchronization should be employed in systems connected to the power network.

Figure 9c shows a block diagram of a digital control circuit that employs synchronization, utilizing a phase-locked loop (PLL) to generate an output signal whose phase is linked to the phase of an input signal. The PLL produces signals with frequencies that are integer multiples of the power line voltage frequency. Additionally, the DSP clock is synchronized with the power line voltage in this circuit. By utilizing synchronization effectively, the system’s properties can be enhanced while avoiding unwanted components, such as beat frequencies.

It should be noted that such a system has indisputable advantages, but the behavior of such a system in transient states should also be considered. Typically, before the system is fully synchronized, slowly changing oscillations may occur. For example, for systems synchronized to the voltage frequency in the mains, you can consider abandoning such a system because, currently, the frequency of the mains voltage is very stable (about ±50 mHz) [59].

4.4. Hard Real-Time System

As previously stated, the control circuit of a power electronic system is most important and should be designed as a hard, real-time system. This means that the control system’s hardware, software, or a combination of both must have a hard deadline for completing a task or action [19,20,37]. Failure to meet this deadline would result in task failure and, in power electronic circuits, a high risk of damage to hardware components. Figure 2 shows a block diagram of an exemplary control circuit with one analog input and one analog output, while Figure 10 depicts a typical timing diagram for such a control circuit in power electronics. During the sampling period T_s, all operations such as calculation, conversion, and communication must be completed. If the control circuit is multirate, as in Figure 2, operations must be finished during the output circuit’s T_s3 period.

4.5. Jitter

Maintaining the stability and repeatability of sampling moments is crucial for ensuring high signal quality. Any variation in the sampling moments, also known as aperture uncertainty or jitter, can result in an error voltage proportional to the magnitude of the jitter and the input signal slew rate. In real A/D converters, sampling moments are often uncertain due to hardware errors and noise, and the issues of signal uncertainty due to sampling have been discussed by numerous authors [37,63,64,65,66,67].

The most common sources of sampling signal jitter are the following:

• Software triggering of the sampling pulse;
• Unwanted electromagnetic couplings created between the traces of a printed circuit board and another source of electromagnetic noise;
• Power supply noise in electronic devices and circuits;
• Digital circuit oscillator frequency drifts over time due to noise;
• Flicker noise;
• Thermal noise.

Only the largest sources of jitter are listed. Within these jitter sources, the software triggering of sampling pulses can generate the highest jitter value.

For a high-quality digital power amplifier, the required SINAD value may be more than 100 dB. In this case, the effect of the jitter can be critical to the circuit parameters.

Figure 11 illustrates a sampling pulse clock with a jitter, while Figure 10b shows how a sampling time jitter generates a signal error. The maximum voltage error for a sinusoidal signal with frequency f and amplitude A can be calculated.

$$\mathsf{\Delta }{U}_{max}={\left.\frac{\mathrm{d}u\left(t\right)}{\mathrm{d}t}\right|}_{max}=A2\pi f\mathsf{\Delta }t$$

(11)

Sampling pulse jitter adds noise to the signal, and the signal-to-noise ratio for a sinusoidal signal can be calculated by the formula:

$$SNR=20\log \left(\frac{A_{rms}}{\mathsf{\Delta }{U}_{rms}}\right)=-20\log \left(\mathsf{\Delta }{t}_{rms}2\pi f\right)$$

(12)

where Δt_rms—root means square of time jitter.

Example 1

The case demonstrates how signal quality can deteriorate due to jitter. If we assume a signal frequency of 3 kHz, a sampling frequency of 40 kHz, and a jitter root mean square of 0.20 μs, the signal-to-noise ratio calculated from Formula (12) with a Gaussian distribution of jitter is SNR = 48.47 dB. A simulation was conducted in Matlab to illustrate this problem, and the results are shown in Figure 12. The sinusoidal signal in the spectrum of Figure 12a was coherently sampled without jitter, and its SNR of 234.40 dB is limited only by the arithmetic accuracy of Matlab. Figure 12b displays the spectrum of the signal that was sampled with jitter. In this scenario, the simulated signal-to-noise ratio is SNR = 48.47 dB with a Gaussian distribution of jitter, which is nearly identical to the value calculated from Formula (12).

It is crucial to generate sampling pulses with great precision, which can only be accomplished using appropriately designed hardware. Attempting to directly generate pulses with software or hardware-software systems may result in high levels of jitter, leading to a notable degradation of the signal-to-noise ratio.

When using microcontrollers, an internal counter is often used to generate an interrupt. The A/D converter is triggered at the beginning of the interrupt handler. This type of solution is a source of jitter. To illustrate this phenomenon, measurements were made for two TMS320F28379D from Texas Instruments and STM32G491RE from STMicroelectronics microcontrollers. The results are shown in Figure 13 and Figure 14. For STM32G491RE, Δt is about 70 ns, and for TMS320F28379D, Δt is about 15 ns. To avoid this problem, microcontrollers should be programmed so that A/D converters are triggered only by hardware, as shown in Figure 15. The entire control algorithm is implemented in the interrupt procedure generated by the A/D converter, as shown in Figure 10. After the calculations are completed, the value of the output signal y(n) controlling the PWM modulator is modified.

5. Multirate Circuits

In classic digital circuits, one common sampling rate is used, while in multirate circuits, many signal sampling frequencies are used [12,14,21,22,37]. Figure 2 displays a block diagram of a digital multirate control circuit. In such systems, it is necessary to alter the sampling rate. The conversion factors involved are usually integers. A signal decimator reduces the sampling rate of a signal, while a signal interpolator increases it. These two circuits are the most prevalent multirate circuits used to adjust signal sampling rates. There are numerous publications that explain these multirate circuits, and the author recommends several books, including [12,13,14,15,16,17,18,19,20,21,22,37], to gain a deeper understanding.

5.1. Signal Decimation

If a reduction in the sampling frequency of the signal is required, it is necessary to use a decimator to reduce the sampling rate. A signal decimator shown in Figure 16a comprises a low-pass filter and a downsampler and is used to reduce the sampling rate of a signal. The low-pass filter reduces the signal bandwidth, while the downsampler reduces the sampling rate. To avoid aliasing components that deteriorate signal parameters, such as SNR, the signal’s bandwidth must first be reduced from f_s/2 to f_s/(2M) before its sampling rate is reduced. In Figure 16b, a multistage version of the signal decimator is shown. Compared to the single stage, this solution typically requires fewer arithmetic operations [37]. Figure 17 illustrates a signal decimation process for a single-stage version for M = 3.

Modern A/D converters often use the oversampling technique, providing a higher sample rate than what is required by the control algorithm. This can lead to issues with SNR deterioration due to the diffusion caused by aliasing components if signal decimation is used without checking for signal components at frequencies higher than f_s/2 (after decimation).

5.2. Signal Interpolation

To increase the sampling rate of a signal, an interpolator is required. Figure 18a shows a signal interpolator that consists of an upsampler and an anti-imaging low-pass filter for an integer-valued conversion factor R. The oversampling ratio, R, is the coefficient used in this process.

The upsampler inserts R-1 zero samples between existing samples. The low-pass filter, H(z), then eliminates the unwanted R-1 components of the upsampled signal, w(kT_s/R). In Figure 18b, a multistage version of the signal interpolator is shown. Just as with the decimator, compared to the single stage, this solution typically requires fewer arithmetic operations.

An illustration of the interpolating process for a single-stage interpolator for R = 3 is depicted in Figure 19. The unwanted images (out-of-band signal components) resulting from the interpolating process can cause interference and significantly decrease the signal-to-noise ratio of the input signal. Therefore, the anti-imaging filter must attenuate all unwanted components, and the stopband cut-off frequency must be carefully selected to limit aliasing in the input signal frequency range.

Example 2

The following example shows the spectra in Figure 20 of the sinusoidal signal (Figure 20a) interpolation process. The following parameters are used: sampling frequency f_s = 1000 Hz, sinusoidal signal frequency f = 200 Hz, and oversampling ratio R = 3. A 5th-order Chebyszew digital filter is used as a low-pass filter, for which the cut-off frequency is equal to 200 Hz. In the spectrum of the interpolator output upsampled signal (Figure 20b), there are visible two unwanted components (800 Hz and 1200 Hz), damped by the digital filter (Figure 20c).

6. Signal Quantization

In the process of signal amplitude quantization, the signal quality deteriorates, and quantization noise is added to the signal. The additive linear model of the quantization process is shown in Figure 21 [11,12,13,14,15,49,50]. As a result, the quality of the signal is worse. One of the parameters describing the quality of the signal is the signal-to-noise ratio.

$$SNR=10\log \left(\frac{P_x}{P_n}\right)=\mathrm{const}+6.02b$$

(13)

where P_x—power of the signal and P_n—power of noise, b—number of bits. Typically, the constants used in (13) equal the following:

$$\mathrm{const}=20\log \left(\frac{3}{2}\right)\approx 1.76$$

(14)

6.1. Signal Headroom

When implementing control circuits, a specific number of bits is selected to ensure optimal quality and signal-to-noise ratio. It is uncommon for the signal amplitude to reach the maximum allowable level; therefore, a margin is often left to account for potential increases in signal value [37,49,50]. Figure 22 demonstrates an example of this scenario, where amplitude A_F represents the maximum allowable level and amplitude A_x defines the nominal signal range. The signal-to-noise ratio is calculated using the following equation:

$$SNR=\mathrm{const}+6.02b+20\log \left(\frac{A_x}{A_F}\right)$$

(15)

6.2. Noise Shaping Circuit

During the A/D and D/A conversions, digital signal processing, especially the noise-shaping circuit (NSC), can be used to increase the SNR [68,69,70,71,72,73,74,75,76]. Spectra for different D/A conversion cases are shown in Figure 23, and identical solutions can also be used for the A/D conversion. A spectrum for a classic D/A conversion is shown in Figure 23a. The implementation of oversampling allows for a decrease in the noise power in the band of interest 0 … f_b (Figure 23b), according to the following relationship:

$$P_{nb}=P_n\frac{2f_b}{f_s}=\frac{P_n}{R}$$

(16)

Therefore, for the A/D and D/A conversions with oversampling, the expression for the signal-to-noise ratio may be modified to form [6,48]:

$$\begin{array}{c}SNR=\mathrm{const}+6.02b+10\log \left(\frac{P_x}{P_{nb}}\right)=1.76+6.02b+10\log \left(\frac{f_s}{{2f}_b}\right)\\ \hspace{1em}\hspace{1em}=1.76+6.02b+10\log \left(R\right)\end{array}$$

(17)

In addition, a low-pass filter can also be used to suppress the noise of off-band quantization noise (Figure 23c). A further reduction of quantization noise can be achieved by using a noise-shaping circuit (Figure 23d). Noise-shaping circuits with feedback were first presented by Cutler [73] in 1954, and a detailed analysis of them was provided by Spang and Schultheiss [74]. The NSC works by putting the quantization error in a feedback loop to move noise away from the band of interest and towards higher frequencies [68,69,70,71,72,73,74,75,76]. The block diagram of the output stage of the power electronic circuit with oversampling and noise-shaping circuits is shown in Figure 24. An example of a class D amplifier solution using NSC is shown in Figure 25. As can be seen, the use of oversampling and NSC allows, in the present case, to increase the SNR by about 26 dB.

6.3. Propagation of the Quantization Noise

The signal-to-noise ratio that results after passing through a circuit with varying signal resolutions in subsequent steps is a crucial concern. In the analysis of noise in analog systems, the Friis formula [72] is utilized, which is unconnected to signal strength. In the event of quantization noise, it relies on the number of bits and signal range. Figure 26 shows a traditional open-loop control system that consists of an A/D converter, DSP circuit, and output PWM modulator. Only quantization noise analysis is given attention, omitting the impact of the input anti-aliasing filter, output circuit, and other factors. To take noise and signal propagation into consideration, specific quantities are defined at each stage, such as k_xk, the signal power gain of the kth stage; k_nk, the noise power gain of the kth stage; A_Fk, the full-scale signal amplitude of the kth stage; and b_k, the signal resolution of the kth stage. Using this approach, circuits with digital circuits, such as digital filters and PID controllers, can be analyzed. The resulting signal-to-noise ratio can be evaluated for such circuits using the equation [37].

$$SNR=10\log \left(\frac{3}{2}\cdot \frac{k_{x1}{k}_{x2}{k}_{x3}{A}_x^2}{k_{n1}{k}_{n2}{k}_{n3}\frac{A_{F1}^2}{2^{2b1}}+k_{n2}{k}_{n3}\frac{A_{F2}^2}{2^{2b2}}+k_{n3}\frac{A_{F3}^2}{2^{2b3}}}\right)$$

(18)

Equation (18) makes it possible to calculate what will be the resultant SNR value of the digital control circuit under consideration, but it is also possible to examine the effect of changing the parameters of circuit elements based on the final value of SNR.

Example 3

For a circuit consisting of a 14-bit A/D converter, a 16-bit fixed-point digital signal processor, and an 11-bit pulse width modulator, assuming the remaining quantities are the following: A_x = 0.5, A_F1 = 1, b₁ = 14, k_x1 = 1, k_n1 = 1, A_F2 = 1, b₂ = 16, k_x2 = 0.7, k_n2 = 0.5, A_F3 = 1, b₃ = 11, k_x3 = 1, and k_n3 = 1, then the SNR value determined by Equation (18) is equal to 60.4 dB.

7. Conversion of Analog Circuits to Digital Form

Traditionally, analog control circuits were employed for power electronic devices, and hence, many digital control circuits in the literature [1,2,3,4,5,6,7,8,9] are still represented by analog transfer functions H(s) rather than digital transfer functions H(z). Figure 27 shows how a third-order analog circuit can be converted to a third-order digital circuit.

Various transforms can be used for this conversion, such as bilinear, matched bilinear, impulse invariant method, matched pole-zero method, backward integration, and forward integration [11,12,13,14,15,77,78,79,80,81,82,83,84,85,86,87,88,89,90]. The characteristics of the resulting digital circuit also depend on the chosen method. Among the methods mentioned above, the bilinear method is the most general and flexible transform. The bilinear transform employs a first-order approximation to map the analog transfer function to a digital one.

$$H_d\left(z\right)={\left.H_a\left(s\right)\right|}_{s=\frac{2}{T_s}\frac{z-1}{z+1}}=H_a\left(\frac{2}{T_s}\frac{z-1}{z+1}\right)$$

(19)

The bilinear transform introduces a nonlinear distortion between the analog frequency f_a and the digital frequency f_d, which is more pronounced for high frequencies near f_s/2, where the frequency response is compressed. The nonlinear mapping between the analog and digital frequencies can be expressed by the following:

$$f_d=\frac{1}{\pi T_s}\arctan \left(\pi f_a{T}_s\right)$$

(20)

Figure 26 shows an example of converting a third-order analog circuit to a digital one using the matched bilinear transform. The example considers a third-order filter with a cutoff frequency of f_g = 3 Hz and a transfer function:

$$H_a\left(s\right)=\frac{1718+0.2246s^2}{1718+331.6s+11.23s^2+s^3}$$

(21)

To convert the analog circuit to digital, a matched bilinear transformation was utilized. When f_s = 10 Hz, the resulting transfer function is obtained.

$$H_d\left(z\right)=\frac{0.161+0.4676z^{-1}+0.4676z^{-2}+0.161z^{-3}}{1-0.01052z^{-1}+0.5683z^{-2}-0.3005z^{-3}}$$

(22)

Figure 28 shows the frequency responses of the analog and digital circuits. Figure 24a compares the magnitude frequency response of the analog circuit and its digital equivalent, while Figure 28b shows phase responses. The frequency response of an analog circuit ranges from zero to infinity, while the frequency response of a digital circuit is limited from zero to f_s/2. Hence, the characteristics of analog and digital circuits differ, especially near f_s/2. As observed in the graph, the analog circuit has a distinct behavior from its digital counterpart. This discrepancy increases as the frequency approaches f_s/2. This may not be significant if the sampling frequency f_s and/or the power transistor switching frequency f_c are much higher than the frequency of the highest component of interest, f_b.

8. Conclusions

Assuming that digital control circuits consist of three stages, as shown in Figure 2, the most common sources of error can be listed:

• Quantization noise;
• Aliasing;
• Jitter;
• A/D and D/A converter noise;
• Computer arithmetic and round-off errors;
• Integral and differential nonlinearity of analog parts;
• Other error sources.

This paper has discussed the upper three sources of error in the above list. The sources of error in digital control circuits can significantly affect the quality of energy processing by power electronic circuits. Correcting these errors improves the distance between the signal and noise/distortion components, leading to improved output/input current and voltage parameters. It should be noted that often only by changing the algorithms without modifying the hardware can improvement be achieved.

In the process of converting an analog signal to a digital one, it is very important to select the sampling speed to avoid significant deterioration of signal parameters by the aliasing phenomenon. For systems with multiple analog inputs, it is important to use simultaneous sampling to sample signals at the same time. In addition, the stability of the sampling pulses used to eliminate the impact of jitter is also important.

The paper shows the problems that arise when varying the sampling rate of signals in multirate digital control circuits. In addition, methods of suppressing quantization noise are presented by using oversampling and noise-shaping circuits.

The paper also presents a new formula for calculating the resultant signal-to-noise ratio for a three-stage digital control circuit. This formula can help estimate quantization errors and choose appropriate components for designing power electronic control circuits.

The paper also addresses issues related to the conversion of analog circuits to digital circuits.

While the author hopes that this paper will be beneficial for digital control circuit designers, he acknowledges that this work only briefly touches on selected problems of digital signal processing in power electronic control circuits. For a more detailed analysis, interested readers are encouraged to explore the literature, including works such as [13,14,15,16,17,18,19,20,34,36,37,40,41].