1. Introduction
Compared with conventional two or three-level inverters [
1], multilevel inverters show greater advantages such as lower total harmonic distortion (THD), less voltage change rate (dv/dt) and reduced electromagnetic interference (EMI) [
2]. Therefore, they have been widely applied to various industry occasions such as photovoltaic (PV) generation systems [
3], electric vehicles [
4], active power filters and motor drives [
5].
The topology structure and modulation strategy are the two most important factors that influence the quality of the multilevel inverter. Traditional topologies of multilevel inverters include the cascaded H-bridge topology (CHB) [
6], neutral point clamped topology (NPC) [
7] and flying capacitor topology (FC) [
8]. The CHB topology employs a large number of independent sources while an FC inverter needs too many capacitors, which increases the volume of power devices. An NPC inverter has the disadvantage of voltage imbalance during operation. Therefore, additional equipment to control capacitor voltage is necessary.
Recently, a new branch of multilevel inverter topology called a switched capacitor structure has emerged. Researchers have paid great attention to designing SC inverters with less component count, reduced voltage stress, self-voltage balance ability and voltage-boosting ability. For instance, two step-up inverters with extension ability have been introduced in [
9,
10]. These two inverters both have a staircase structure to increase the level number and apply a backend H-bridge to determine the polarity of the output. Self-balance ability and low switch count are the main advantages of the inverters. However, power switches in the backend H-bridge have to withstand maximum output voltage, which significantly increases the voltage stress of the inverter. To reduce the voltage stress, SC inverters without H-bridges have been successively proposed in [
11,
12,
13,
14,
15,
16,
17,
18]. The topologies proposed in [
11,
12] are all seven-level SC inverters. Compared with [
9,
10], they have lower voltage stresses. However, they employ a large number of power devices. There are also SC inverters generating nine output levels [
13,
14,
15,
16]. The hybrid inverters proposed in [
13,
14] feature reduced switched counts and simplified control strategies since they only use four pairs of complementary signal power switches. However, their boosting factors are only two. The nine-level inverters with quadruple boost ability are proposed in [
15,
16]. They have high voltage-boosting ability and low voltage stress, whereas they utilize too many semiconductor switches, diodes and capacitors. To further increase the number of output levels and reduce the total harmonic distortion (THD), 13- and 17-level inverters have also been proposed by researchers. In [
17], Ye proposed a 13-level inverter with a reduced switch count and high boosting ability, and he further improved the topology in [
18]. The 17-level SC inverters are proposed in [
19,
20,
21], all of which show their pros and cons, respectively. The topologies presented in [
19,
20] both have the advantage of a low component count, but the capacitor voltage in [
19] cannot balance inherently and [
20] employs more than one DC source. The inverter proposed by Kaibalya Prasad Panda [
21] has a low capacitor count, single input source and self-voltage balance. Nevertheless, three power switches have to withstand peak output voltage.
On the other hand, the modulation method also significantly affects the power quality of the multilevel inverter. The modulation strategy of the multilevel inverter includes high-frequency modulation and fundamental frequency modulation (FFM). High-frequency modulation, which uses triangular carrier wave to determine the output, is employed more widely than FFM because it reduces the THD of the output and makes the filter design easier. However, the frequency of the triangular carrier signal in HFM is always much higher than the fundamental frequency. This leads to many switches, including those with high blocking voltage, operating at a high switching frequency. As a result, it will increase the switching loss of the inverter significantly. Taking [
18] as an example, the modulation strategy as well as the switching signal proposed in this paper is demonstrated in
Figure 1. It can be seen from the figure that all the switches except
Q1 operate at a high switching frequency, among which
S1,
S2 and
S3 have high blocking voltage (3
Vdc). If the frequency of the carrier signal increases, the switching loss of the inverter will increase significantly and may become unbearable.
To reduce the switching frequency and loss in an SC inverter under high-frequency modulation, this study proposes a novel hybrid modulation strategy and a generalized switched capacitor topology configuration suitable for using this modulation method. And it further gives a specialized 17-level switched capacitor demo topology based on the generalized configuration. The demo topology maintains the advantages of most SC inverters, such as self-voltage balance, high boosting gain and a single DC supply. The most prominent feature of the demo topology is that it reduces the switching loss significantly under the hybrid modulation because only switches with minimum blocking voltage work with high switching frequency and the switching frequency of other switches do not exceed seven times of the fundamental frequency. Therefore, it reaches a balance between the output THD and switching loss.
The rest of this paper is organized as follows:
Section 2 will give the proposed generalized SC configuration and the principle of the proposed hybrid modulation strategy.
Section 3 will introduce the demo topology and its working principle under the proposed modulation method.
Section 4 will analyze the voltage balance process and losses in detail. The comparative study will be included in
Section 5.
Section 6 gives the simulation under linear load change conditions. Experimental results of the proposed demo topology and modulation method will be shown in
Section 7. Finally,
Section 8 gives conclusions.
6. Simulation Results
To verify the feasibility of the proposed modulation and topology, a simulation model is set up in PSIM. The simulation parameters are listed in
Table 5.
Figure 12a demonstrates the waveform of output voltage and current (amplified 40 times) under RL-load. The inductor is set as 46 mH. The resistance firstly increases from 50 Ω to 200 Ω, then it keeps constant and finally decreases linearly from 200 Ω to 50 Ω. It can be observed from the Figure that the output voltage is a 17-level staircase AC waveform with the amplitude of 200 V. The output current is a near-sinusoidal waveform. When the load increases, the amplitude of output current decreases gradually and reaches the lowest value at 0.98 A. After that, the load resistance reduces, and the output current rises correspondingly.
Figure 12b shows the voltage of capacitors in the demo topology. It can be seen that the voltages of
Ca1 and
Ca2 are maintained around 25 V, the voltages of
Cb1 and
Cb2 are balanced at 50 V and the voltage of
Cc1 is balanced at 100 V. Therefore, under the proposed modulation, the capacitor voltages in the demo topology are self-balanced. Moreover, it can be observed that the voltage ripple increases when the load impedance reduces. The voltage ripples of
Cb1,
Cb2 and
Cc1 reach the maximum value when the resistance becomes 50 Ω. However, the voltage ripples of all the capacitors do not exceed 10% of their rated voltage, which means the selection of capacitor parameters all satisfy the 10% ripple requirement.