AC Grid–DC Microgrid Coupling with High-Performance Three-Phase Single-Stage Bidirectional Converters ^†

Abstract

This paper discusses bidirectional step-down topologies that enable the interface of the $400\mathrm{V}$ unipolar DC microgrid with the European low-voltage three-phase AC grid. The study compares three single-stage non-isolated topologies, namely, the seven-switch buck converter, Swiss converter, and Y-converter, based on semiconductor stresses and losses, magnetic component sizes and losses, and heat sink sizes. The analysis is conducted for a $10\mathrm{k}\mathrm{W}$ converter designed for small commercial or residential use. The results indicate that the Y-converter has superior overall performance compared to the other topologies, making it a potentially better candidate for this application. A $10\mathrm{k}\mathrm{W}$ prototype of the Y-converter is constructed. It is demonstrated to have a peak efficiency of $99.26\%$ and an efficiency of $97.47\%$ at the rated output power.

1. Introduction

The rapid increase in the demand for electric energy, particularly in the electric vehicle market, poses significant challenges. Meeting this growing demand requires a corresponding expansion in electric energy generation, which can lead to environmental issues if traditional energy sources are relied upon. Hence, renewable energy sources present an ideal solution for addressing the surging demand while generating zero-carbon emissions. Furthermore, recent advancements in control approaches for renewable energy sources, particularly solar and wind sources, have facilitated the seamless integration of these renewable sources into the preexisting power networks [1,2,3,4].

One of the most promising solutions is the utilization of microgrids. Microgrids offer a means to meet local energy demands by connecting distributed power sources to distribution networks, eliminating the need for extensive expansion of costly centralized utility grids. Consequently, DC microgrid technology has emerged as an attractive solution for modern electrical grid systems due to its inherent compatibility with renewable energy sources, electric loads, and energy storage systems [5,6]. Typically, DC microgrids are interconnected with low- or medium-voltage utility grids, as displayed in Figure 1, to serve as a backup in situations where the load demand exceeds the generated power within the microgrid or to feed surplus-generated power from the microgrid back to the utility grid [7,8,9].

Several studies discussed the selection of the DC microgrid optimum voltage level [7,9,10,11]. The findings of these studies have demonstrated that the 400 $\mathrm{V}$ DC system yields superior outcomes in terms of system efficiency and necessitates fewer power conversions for connecting multiple energy sources and loads. This voltage level is particularly advantageous for applications such as electric vehicle charging and distribution in residential or commercial buildings. When interconnecting a 400 $\mathrm{V}$ DC microgrid with the European low-voltage grid, which operates at a 400 $\mathrm{V}$ line-to-line voltage, the use of buck-type bidirectional power factor correction (PFC) converters is necessary [12].

Numerous topologies utilizing optimized modulation techniques have been proposed in the literature to attain an ultra-efficient power conversion in buck-type topologies. The first set of topologies is based on the conventional six-switch buck converter. In an effort to attain 99% efficiency, a design procedure for optimizing the six-switch buck converter is presented in [13]. Different optimized modulation techniques for this topology were explored in [14] to minimize switching losses and input capacitor voltage distortions. A further improvement to the six-switch buck converter is presented in [15,16], which is called the seven-switch buck converter. In the seven-switch converter, an additional freewheeling switch is employed to reduce conduction losses during the freewheeling mode. Bidirectional power capability for the above-mentioned topologies can be obtained using the anti-parallel configuration or using an inverting link [17,18]. A delta-type input current source converter with bidirectional capability is proposed in [19] to reduce the conduction losses of the six-switch converter.

The second set of topologies is based on employing an active third-harmonic current injection circuit such as the Swiss converter. The Swiss converter was presented in [20] and it demonstrated significant potential for achieving improved performance compared to the conventional six-switch converter. An ultra-high efficiency-interleaved Swiss converter with Silicon Carbide (SiC) devices is demonstrated in [21]. Modified modulation techniques for the Swiss converter are presented in [22,23] to improve grid current distortions. Moreover, an isolated Swiss converter is reported in [24], which employs full-bridge topology to the Swiss rectifier to attain both the soft switching and the high-frequency galvanic isolation. In addition to the Swiss converter, the hybrid active third-harmonic current injection converter was proposed and compared to the Swiss rectifier in [25], where the Swiss rectifier showed an overall better performance.

In addition to the conventional buck-type converters, the Y-converter, originally introduced in [26] for motor-drive applications, can be utilized to connect the AC grid with the DC microgrid. The Y-converter offers a bidirectional buck–boost capability and enables single-stage power conversion with a reduced number of semiconductor devices compared to traditional buck-type topologies. Consequently, the Y-converter emerges as a compelling choice for interfacing the AC grid with the DC microgrid.

In this paper, building upon [27], a comparative evaluation of bidirectional single-stage non-isolated buck-type topologies is conducted. The evaluated converters include the Y-converter, the seven-switch converter, and the Swiss converter. The operational principles of these topologies are discussed, followed by their evaluations based on various criteria: the number of semiconductors, semiconductor stresses and losses, magnetic element sizes and losses, and the size of the heat sink. This evaluation is carried out using an analytical power loss model and simulations. In comparison to [27], the magnetic element design and losses, along with the reverse recovery losses of the SiC MOSFETs, are included as part of the evaluation criteria. Additionally, a 10 kW prototype of the Y-converter is implemented to demonstrate its operation and high efficiency. The rest of this paper is structured as follows: The topology overview is discussed in Section 2. Analytical power loss models are presented in Section 3. A comparative evaluation of the topologies is presented in Section 4. The experimental results are presented in Section 5. Finally, a conclusion is provided in Section 6.

2. Topology Overview

In this section, a brief discussion is provided on the three topologies, along with an explanation of their operational principles and the driving pulse schemes employed by each converter.

2.1. Y-Converter

Figure 2a illustrates the Y-converter topology. In the standard representation, the Y-converter can be viewed as a conventional three-phase boost voltage source converter with an additional pre-stage to incorporate the buck feature. In the modular representation, the Y-converter is constructed by connecting three four-switch buck–boost DC-DC converters in a star configuration, all connected to a common point (m). For the sake of simplicity, the analysis in this paper will utilize the modular representation.

Since each module functions as a DC-DC converter, it is essential to ensure a positive input voltage at the AC input of the modules ($V_{\{a,b,c\}m}$ must be kept $\ge 0\mathrm{V}$). To achieve this, a suitable offset voltage must be established between the grid neutrals (n) and (m). Different pulse-width modulation (PWM) techniques can be employed based on the selected offset voltage [26,28]. The PWM technique considered in this paper is the discontinuous PWM (DPWM), which provides a time-varying offset voltage represented by:

$$v_{off}\left(t\right)=-min(v_a\left(t\right),v_b\left(t\right),v_c\left(t\right))$$

(1)

where $v_a$, $v_b$, and $v_c$ are the AC grid phase voltages.

The AC-side voltages ($v_{am}$, $v_{bm}$, and $v_{cm}$) of the three modules can be expressed as

$$\begin{array}{cc}\hfill v_{am}& ={\widehat{V}}_{m}cos\left(\omega t\right)+v_{off}\hfill \\ \hfill v_{bm}& ={\widehat{V}}_{m}cos\left(\omega t-\frac{2\pi }{3}\right)+v_{off}\hfill \\ \hfill v_{cm}& ={\widehat{V}}_{m}cos\left(\omega t+\frac{2\pi }{3}\right)+v_{off}\hfill \end{array}$$

(2)

where ${\widehat{V}}_m$ is the peak value of the phase voltages.

In DPWM, the module with the most-negative grid voltage is clamped to point m. This clamping mode has the advantage of eliminating both semiconductor switching losses and inductor core losses for the clamped module, resulting in a significant reduction in overall losses. During the remaining part of the fundamental cycle, one half-bridge (either the buck or boost) is subjected to pulse width modulation, while the other half-bridge is clamped. The choice of modulation depends on whether the AC-side module voltage is higher or lower than the DC-side voltage. The Y-converter modulation and the duty cycles of the switches are depicted in Figure 3a.

2.2. Seven-Switch Buck Converter

The seven-switch buck converter comprises three main parts: a three-phase bridge, a freewheeling switch, and an inverting link. In this paper, the three-phase bridge is created using a series combination of SiC MOSFETs and SiC diodes that enable current flow in one direction and voltage blocking in both directions.

The converter operation is analyzed using space vector PWM (SVPWM) [16] and involves six active space vectors and a zero (null) space vector. The zero-space vector is achieved by activating only the freewheeling switch, whereas in the traditional six-switch topology, the entire leg is turned on. During the freewheeling state, the seven-switch converter has the advantage of the DC link current flowing through a single semiconductor device $S_{fw}$, resulting in significantly reduced conduction losses compared to the four devices in the six-switch converter.

To enable bidirectional power capability, the inverting link is utilized to reverse the polarity of the DC-side voltage. In the rectification mode, the inverting link switches, such as $S_{i+}$ and $S_{i-}$, are turned off, allowing power transfer from the AC side to the DC side through $D_{i+}$ and $D_{i-}$. In the inversion mode, both $S_{i+}$ and $S_{i-}$ are turned on, creating a negative DC link that facilitates power transfer from the DC side to the AC side. The seven-switch buck converter modulation and the duty cycles of the switches are presented in Figure 3b.

2.3. Swiss Converter

The Swiss converter is composed of three primary stages: an active three-phase bridge, a third harmonic injection network, and two buck DC-DC converters. The three-phase bridge functions as an uncontrolled rectifier bridge, driven to operate in a typical manner.

The third harmonic injection network includes three four-quadrant switches and is controlled to actively inject current solely into the phase with the lowest instantaneous voltage. Switching losses in both the active bridge and the injection network are neglected since they operate at the grid frequency and twice the grid frequency, respectively. When combined, the active bridge and the injection network form a three-phase unfolder. This three-phase AC unfolder converts the three-phase voltages into two DC voltages, namely $v_{py}$ and $v_{yn}$, which are utilized by the two buck DC-DC converters. This configuration enables the control of grid currents and the DC-side voltage by solely manipulating the duty cycle of the buck converters.

The duty cycles $d_{p+}$ of switch $S_{p+}$ and $d_{n-}$ of switch $S_{n-}$ are controlled in both the inverter and rectifier modes so that the AC-side current becomes sinusoidal. $d_{p+}$ and $d_{n-}$ can be calculated as follows:

$$\begin{array}{cc}\hfill d_{p+}& =\frac{2}{3}\frac{V_{dc}}{{\widehat{V}}_m^2}max(v_a,v_b,v_c)\hfill \\ \hfill d_{n-}& =\frac{2}{3}\frac{V_{dc}}{{\widehat{V}}_m^2}|min(v_a,v_b,v_c)|\hfill \end{array}$$

(3)

where $V_{dc}$ is the DC link voltage. The Swiss converter modulation and the duty cycles of the switches are presented in Figure 3c.

3. Analytical Power Loss Model

To assess and compare the three topologies, an analytical model is developed to calculate power losses. The model takes into account various types of power losses, including conduction losses in semiconductors, switching losses in semiconductors, copper losses, and core losses in inductors.

Table 1. Three-phase PFC rectifier parameters.

	Parameter	Symbol	Value
Converter parameters 1	Nominal power	P	10	$\mathrm{k}\mathrm{W}$
	AC line voltage	Vac	400	$\mathrm{V}$
	Line frequency	f	50	$\mathrm{Hz}$
	Switching frequency	$f_{sw}$	62.5	$\mathrm{k}\mathrm{Hz}$
	Output voltage	Vdc	400	$\mathrm{V}$
SiC MOSFET	Part number	IMZ120R030M1H
	Voltage	VDS	1200	$\mathrm{V}$
	Current	$I_D$	56	$\mathrm{A}$
SiC Diode	Part number	C4D20120D
	Voltage	VRRM	1200	$\mathrm{V}$
	Current	$I_F$	66	$\mathrm{A}$
Input Filter	Inductor	$L_f$	50	$\mu \mathrm{H}$
	Capacitor	$C_f$	11.3	$\mu \mathrm{F}$

¹ The converter parameters are utilized in both the evaluation of the converters and the experimental prototype.

summarizes the converter parameters and the specific semiconductors used. The model is based on the following assumptions:

• The inductances in all converters are assumed to be constant for the whole operating power range;
• The comparison is held at a fixed junction temperature for all devices ($T_j$ = 25 °C);
• The reverse recovery losses of the SiC Schottky diode are neglected as a zero-reverse recovery current diode is utilized;
• The input filter ($L_f,C_f$) is fixed for all topologies; the EMI filter is not considered.

3.1. Semiconductor Conduction Losses

The conduction losses of power MOSFETs are calculated as follows:

$$P_{cond,sw}=I_{DS,RMS}^2{R}_{DS,on}$$

(4)

where $I_{DS,RMS}$ is the RMS value of the MOSFET current, and these RMS values for the three topologies are summarized in Figure 4. $R_{DS,on}$ is the on-state resistance of the power MOSFET and it is assumed to vary with the junction temperature $T_j$ according to the following equation:

$$R_{DS,on}\left(m\mathrm{\Omega }\right)=a_0+a_1{T}_j+a_2{T}_j^2$$

(5)

The used fitting parameters for IMZ120R030M1H are:

$$\begin{array}{c}\hfill a_0=29.78\mathrm{m}\mathrm{\Omega },a_1=-0.01556\mathrm{m}\mathrm{\Omega }/°\mathrm{C},a_2=0.0009778\times {10}^{-4}\mathrm{m}\mathrm{\Omega }/{°\mathrm{C}}^2\end{array}$$

(6)

For the SiC diodes in the seven-switch converter, the conduction losses are calculated as follows:

$$P_{cond,D}=I_{D,rms}^2{R}_{D,on}+I_{D,av}{V}_{D,on}$$

(7)

where $I_{D,rms}$ and $I_{D,av}$ are the RMS and the average values of the diode current, respectively. These values are summarized in Figure 4. $R_{D,on}$ and $V_{D,on}$ are the on-state resistance and the on-state voltage of the power diode and they are assumed to vary with the junction temperature $T_j$, according to the following equations:

$$\begin{array}{c}{R}_{D\mathrm{on}}\left(m\mathrm{\Omega }\right)=b_0+b_1{T}_j\\ V_{D\mathrm{on}}\left(\mathrm{V}\right)=c_0+c_1{T}_j\end{array}$$

(8)

The used fitting parameters for C4D20120D are:

$$\begin{array}{c}\hfill b_0=20\mathrm{m}\mathrm{\Omega },b_1=0.266\mathrm{m}\mathrm{\Omega }/C,c_0=0.98\mathrm{V},c_1=-1.71\times {10}^{-3}\mathrm{V}/C\end{array}$$

(9)

3.2. Semiconductors Switching Losses

The calculation of switching losses relies on the utilization of switching energy loss $E_{sw}$ versus drain-source current $I_{DS}$ curves of the SiC MOSFETs. These curves can be obtained from the manufacturer’s datasheet or through the implementation of a calorimetric switching loss measurement setup, as suggested in [29]. In this paper, two distinct polynomial fittings are employed to determine the turn-on energy loss $E_{sw,on}$ and the turn-off energy loss $E_{sw,off}$ individually. This separation allows for easy integration of soft switching into the power loss model whenever it occurs. The polynomial fitting equations for $E_{sw,on}$ and $E_{sw,off}$ are chosen to be fourth-order polynomials in order to minimize the root mean square error between the actual data and the fitted polynomials. The polynomial fitting equations can be expressed as:

$$E_{sw,\mathrm{on}}\left(\mathrm{m}\mathrm{J}\right)=V_{DS}(P_{1\mathrm{on}}{I}_{DS\mathrm{on}}^4+P_{2\mathrm{on}}{I}_{DS\mathrm{on}}^3+P_{3\mathrm{on}}{I}_{DS\mathrm{on}}^2+P_{4\mathrm{on}}{I}_{DS\mathrm{on}})$$

(10)

$$E_{sw,\mathrm{off}}\left(\mathrm{m}\mathrm{J}\right)=V_{DS}(P_{1\mathrm{off}}{I}_{DS\mathrm{off}}^4+P_{2\mathrm{off}}{I}_{DS\mathrm{off}}^3+P_{3\mathrm{off}}{I}_{DS\mathrm{off}}^2+P_{4\mathrm{off}}{I}_{DS\mathrm{off}})$$

(11)

where $I_{DS,on}$ and $I_{DS,off}$ represent the instantaneous values of the MOSFET turn-on and turn-off currents, respectively, and $V_{DS}$ represents the instantaneous value of the MOSFET voltage. It is assumed that $V_{DS}$ remains constant during the turn-on and turn-off at every instant. The fitting parameters for IMZ120R030M1H are as follows:

$$\begin{array}{cccc}\hfill P_{1\mathrm{on}}& =-7.2730\times {10}^{-10}{\mathrm{A}}^{-3}.\mathrm{m}\mathrm{s};\hfill & \hfill P_{1\mathrm{off}}& =-5.4688\times {10}^{-10}{\mathrm{A}}^{-3}.\mathrm{m}\mathrm{s}\hfill \\ \hfill P_{2\mathrm{on}}& =+7.0371\times {10}^{-8}{\mathrm{A}}^{-2}.\mathrm{m}\mathrm{s};\hfill & \hfill P_{2\mathrm{off}}& =+5.2350\times {10}^{-8}{\mathrm{A}}^{-2}.\mathrm{m}\mathrm{s}\hfill \\ \hfill P_{3\mathrm{on}}& =-2.1250\times {10}^{-6}{\mathrm{A}}^{-1}.\mathrm{m}\mathrm{s};\hfill & \hfill P_{3\mathrm{off}}& =-1.4412\times {10}^{-6}{\mathrm{A}}^{-1}.\mathrm{m}\mathrm{s}\hfill \\ \hfill P_{4\mathrm{on}}& =+3.6750\times {10}^{-5}\mathrm{m}\mathrm{s};\hfill & \hfill P_{4\mathrm{off}}& =+1.5450\times {10}^{-5}\mathrm{m}\mathrm{s}\hfill \end{array}$$

(12)

Given the switch voltage and current at the turn-on and turn-off instances, the switching energy is calculated using (10) and (11), then the switching losses are calculated.

In addition to the switching losses during the first quadrant operation of SiC MOSFETs, the power loss model includes switching losses during the third quadrant operation, i.e., the synchronous rectification mode. We assume that the turn-on switching losses in the synchronous rectifier mode are negligible, while at turn-off, power loss occurs due to the reverse recovery of the integral body diode. The switching energy losses due to reverse recovery ($E_{s{w}_{rr}}$) can be represented as functions of $I_{ds}$ and $V_{sw}$ [30] based on the following polynomial fitting:

The fitting parameters for IMZ120R030M1H are as follows:

$$E_{s{w}_{rr}}\left(\mathrm{m}\mathrm{J}\right)=V_{DS}(P_{1_{rr}}{I}_{s{w}_{o}ff}^2+P_{2_{rr}}{I}_{s{w}_{o}ff}+P_{3_{rr}})$$

(13)

$$\begin{array}{cc}\hfill P_{1_{rr}}& =+1.4037\times {10}^{-8}{\mathrm{A}}^{-1}.\mathrm{m}\mathrm{s}\hfill \\ \hfill P_{2_{rr}}& =+1.1225\times {10}^{-5}\mathrm{m}\mathrm{s}\hfill \\ \hfill P_{3_{rr}}& =+2.8075\times {10}^{-6}\mathrm{A}.\mathrm{m}\mathrm{s}\hfill \end{array}$$

(14)

3.3. Inductor Losses

The power inductor L is designed to provide the same inductor current ripple percentage at the rated power for all topologies ($\Delta I_{Lp}=20\%$). It can be calculated for the Y-converter as follows [28]:

$$L=\frac{V_{dc}}{8\sqrt{2}\Delta I_{Lp}{I}_{\phi }{f}_{sw}}$$

(15)

For the Swiss and seven-switch converters [13,20]:

$$L=\frac{V_{dc}}{2\Delta I_{Lp}{I}_{dc}{f}_{sw}}\left(1-\frac{\sqrt{3}}{2M}\right)$$

(16)

where M is the modulation index and can be expressed as follows:

$$M=\sqrt{2}\frac{\widehat{I_{\phi }}}{I_{dc}}=\frac{2}{3}\frac{V_{dc}}{V_m}$$

(17)

where $I_{dc}$ is the DC-side current and $\widehat{I_{\phi }}$ is the RMS value of the AC-side phase current.

At the given M $(\approx 0.8165)$, previous equations result in almost the same value of L$(\approx 190\mu H)$ for the investigated topologies.

The power loss of L is divided into copper losses and core losses. For the copper losses, due to employing Litz wires to implement the inductor, skin effects and high-frequency losses can be neglected. Therefore, the copper losses are limited to the DC copper losses, which can be calculated as follows:

$$P_{cu}=I_{Lrms}^2{R}_{LDC}$$

(18)

where $R_{LDC}$ is the DC resistance of L.

The core loss is calculated based on the curve-fitting equations provided by the manufacturer [31]. The provided fitting equations represent experimentally measured magnetic property curves using closed-form equations. These equations facilitate the seamless integration of these magnetic properties into the power loss model. Starting from the maximum and minimum currents of the inductor at different instances, $I_{Lmax,i}$, $I_{Lmin,i}$, the corresponding values of magnetic flux intensity (H) and magnetic flux density (B) can be calculated as follows:

$$H=\frac{0.4\pi N{I}_L}{100\mathrm{MPL}}$$

(19)

$$B={\left[\frac{a+bH+c{H}^2}{1+dH+e{H}^2}\right]}^x$$

(20)

where N is the number of turns, MPL is the magnetic path length in meters (m), H is in Oersted (Oe), and B is in Tesla (T). a, b, c, d, e, and x are the fitting parameters of the B-H curves provided by the manufacturer. The values of these fitting parameters are summarized in

Table 2. Inductor parameters.

	Parameter	Symbol	Value
Inductor Parameters	Part number	KoolMu 0079908A7
	Magnetic path length	MPL	19.6	$\mathrm{cm}$
	Core volume	$V_c$	43.4	${\mathrm{cm}}^3$
	Number of turns	N	80	Turns
	Inductor DC resistance	$R_{LDC}$	20.3	$\mathrm{m}\mathrm{\Omega }$
Fitting Parameters	Flux density B Equation (20)	a	3.763 $\times {10}^{-2}$ $\mathrm{T}$
		b	1.712 $\times {10}^{-2}$ $\mathrm{T}$/Oe
		c	5.155 $\times {10}^{-4}$ $\mathrm{T}$/Oe2
		d	9.190 $\times {10}^{-2}$ Oe−1
		e	4.909 $\times {10}^{-4}$ Oe−2
		x	1.812
	Core losses ${\mathbf{P}}_{\mathbf{core}}$ Equation (21)	$a_{Loss}$	52.36 $\mathrm{J}$/($\mathrm{T}$.$\mathrm{m}$3)
		$b_{Loss}$	1.988
		$c_{Loss}$	1.541

.

The core losses at a specific instant can be given by:

$$P_{core}=V_c\times a_{Loss}\times (B_{max}-B_{min}{)}^{b_{Loss}}(\frac{f_{sw}}{1000}{)}^{c_{Loss}}$$

(21)

where $V_c$ is the magnetic core volume in $m^3$. $a_{Loss}$, $b_{Loss}$, and $c_{Loss}$ are the fitting parameters for the core loss curves provided by the manufacturer. The inductor parameters along with the core loss fitting parameters are summarized in Table 2.

4. Comparative Analysis

4.1. Semiconductors Stresses

4.1.1. Voltage Stresses

In the three topologies, the maximum voltage stress on semiconductor devices is represented by three distinct values: the peak line-to-line grid voltage ($566\mathrm{V}$), the DC microgrid voltage ($400\mathrm{V}$), and the voltage at the natural commutation points of the line-to-line grid voltage ($537\mathrm{V}$). The $537\mathrm{V}$ peak voltage applies to the AC-side SiC MOSFETs ($S_{\{a,b,c\}1}$ and $S_{\{a,b,c\}2}$) in the Y-converter, the three-phase bridge devices ($S_{1:6}$ and $D_{1:6}$) in the seven-switch converter, and the three-phase bridge devices ($S_{1:6}$) in the Swiss converter. The $400\mathrm{V}$ peak voltage is applicable to the remaining devices in the Y-converter and the seven-switch converter, while the $537\mathrm{V}$ peak voltage applies to the remaining devices in the Swiss converter. The voltage stresses of the three topologies are summarized in Figure 5.

4.1.2. Current Stresses

The formulas for the current stresses of the semiconductor devices in the three topologies are summarized in Figure 4. Additionally, The current stresses at $10\mathrm{k}\mathrm{W}$ are summarized in Figure 5.

In order to provide deeper insight into the current stresses of the investigated topologies, the summation of the squared RMS currents of semiconductor devices in the investigated topologies are depicted in Figure 6. According to the obtained outcomes, the Y-converter exhibits the lowest summation across the entire power range. This implies that the Y-converter necessitates semiconductor devices with a lower current rating in comparison to the seven-switch and Swiss converters. Furthermore, if the same SiC devices are employed for all three topologies, the Y-converter will incur the least conduction losses at any given power level.

4.2. Semiconductors Losses

4.2.1. Conduction Losses

The conduction losses of the topologies are illustrated in Figure 7a. The Y-converter exhibits the lowest conduction losses throughout the entire operating range. This is primarily due to its minimal number of series switches in the current path for rectification and inversion. On the other hand, the seven-switch converter experiences the highest conduction losses. This can be attributed to the presence of SiC diodes and the excessive current stresses on the inverting link devices.

4.2.2. Switching Losses

The switching losses of the topologies are depicted in Figure 7b. In the Y-converter, the use of DPWM leads to a significant reduction in switching losses. Additionally, only a single leg in each module undergoes commutation at any given time, further contributing to lower losses. In the Swiss converter, although the switching losses are confined to the fast switches ($S_{p+}$ and $S_{n-}$ in the rectification mode and $S_{y+}$ and $S_{y-}$ in the inversion mode), they are considerably high due to their operation under high currents. Given the semiconductor conduction and switching losses of the studied topologies, the total semiconductor losses are plotted in Figure 7c.

4.3. Inductor Losses

The inductor losses of the topologies are plotted in Figure 7d. Although the core losses in the Y-converter are reduced by employing DPWM, the Y-converter demonstrates the highest core losses among the studied topologies. The inductors in the Swiss converter and the seven-switch converters yield the same losses and sizes. The copper losses in the Y-converter are reduced as the total current is shared between the three phases, unlike the other topologies, where the total output current flows through the inductors.

5. Experimental Results

To demonstrate the operation and high efficiency of the Y-converter, a $10\mathrm{k}\mathrm{W}$ prototype of the Y-converter was implemented. The experimental setup is displayed in Figure 8. The experimental results are categorized as follows: key waveforms of the Y-converter, along with the measured THD of the AC side currents, and the measured efficiency of the converter, with its corresponding calculated power loss breakdown.

5.1. Key Waveforms and AC Current THDs

The selected key waveforms of the Y-converter are the AC-side voltage $V_{am}$, the grid voltage $V_{an}$, the inductor current $I_{La}$, and the grid current $I_a$. Experimental results under full loads for both rectification and inversion modes are displayed in Figure 9 and Figure 10, respectively. The results show that the clamping mode is verified where $V_{am}=0\mathrm{V}$, and $I_{La}$ is shown to be ripple-free during clamping while preserving the sinusoidal shapes of both $I_{La}$ and $I_a$. The THDs of $I_a$ at different output power levels are presented in Figure 11 with 3.8% at the converter’s rated output power.

5.2. Measured Efficiency and Power Loss Breakdown

The efficiency of the prototype is measured using the Dewesoft SIRIUS XHS high-speed data acquisition (DAQ) system. The efficiency curve is plotted in Figure 11, which shows that the converter has a peak efficiency of 99.26% at nearly 40% of the rated power and 97.49% efficiency at the rated power.

Based on the previously discussed power loss model and the measured temperatures of the semiconductor devices during experimental tests, the calculated power loss breakdown for a half load and full load are displayed in Figure 12. At a half load, the semiconductor losses represent almost $60\%$ of the total losses with a roughly equalized distribution between conduction losses and switching losses. At a full load, the conduction loss contribution to the total losses is estimated to be $51\%$, which explicitly means that using another SiC device with a lower $R_{DS,on}$ can lead to better efficiency at a full load. The “other losses”, represented in the loss breakdown figure, is a generic term that represents the losses that are not included in the calculations, such as PCB losses, capacitor losses, etc., along with the mismatch between the calculated losses and the actual losses.

6. Discussion and Conclusions

This paper evaluates bidirectional step-down converters that enable the connection between the $400\mathrm{V}$ unipolar DC microgrid and the European low-voltage three-phase AC grid. The study compares three single-stage non-isolated topologies—the seven-switch buck converter, Swiss converter, and Y-converter—based on various factors, such as semiconductor stresses and losses, magnetic component sizes and losses, and heat sink sizes. The analysis is centered on a $10\mathrm{k}\mathrm{W}$ converter that is suitable for residential or commercial use. The results indicate that the Y-converter has the lowest number of semiconductor devices, semiconductor device stresses, total losses, and heat sink sizes. The only drawback is that the total inductor size in the Y-converter is larger than those of the other studied topologies. Based on the findings, the Y-converter performs better overall than the other topologies, making it a potentially more suitable option for this application. A $10\mathrm{k}\mathrm{W}$ Y-converter prototype is implemented and shown to have a peak efficiency of $99.26\%$ and an efficiency of $97.47\%$ at the rated output power. For future research, multi-objective optimization could be adopted for designing passive elements and selecting semiconductor devices. Subsequently, the topologies could be evaluated accordingly. This approach would offer a more comprehensive perspective on comparisons across various converter parameters, such as switching frequencies, inductor current ripples, and semiconductor device ratings. Additionally, investigating control strategies for each topology and evaluating their impacts on performances, losses, and efficiency could provide insight into the influence of these strategies on the converter’s behavior. This analysis would help identify opportunities for optimization.