A Bidirectional Grid-Tied ZVS Three-Phase Converter Based on DPWM and Digital Control

Abstract

In this paper, a bidirectional grid-tied ZVS three-phase converter is proposed. The circuit operation principle in both the rectifier and inverter modes was analyzed. The proposed topology could achieve zero-voltage switching in the six main switches and the auxiliary switch both in the rectifier mode and inverter mode. In addition, the reverse recovery current of body diodes in the main switches was also suppressed. Furthermore, in order to realize the ZVS control scheme under the grid-tied bidirectional power flow condition and reduce the number of switchings, a modified carrier-based discontinuous PWM was proposed to fit the bidirectional switching sequence. Finally, a 3 kW prototype was constructed. Some simulation and experimental results are presented to verify the validity of the proposed circuit topology and PWM control scheme.

1. Introduction

In order to overcome the intermittency and instability of renewable energy, energy conversion plays an important role in the grid-tied and/or storage energy system.

In such a system, the bidirectional power flow converter highly affects the efficiency of the whole system. The three-phase, six-switch converter is the best choice and is widely used for bidirectional power flow control in many application fields, including motor drive, energy storage systems, uninterruptible power systems and renewable energy [1]. It has several advantages, such as lower current stress, high efficiency and a small input filter. However, the conventional hard switching scheme causes a significant switching loss [2]. In addition, due to the reverse recovery process, the body diodes of all switches will suffer higher loss and EMI problems. As a result, many techniques have been developed to make the converter operate in the soft-switching condition to reduce the switching loss and improve the conversion efficiency.

In recent years, numerous ZVS techniques have been extensively studied in AC/DC and DC/AC converters. The more common method is to add an auxiliary resonant circuit in these converters. According to the locations of the auxiliary circuit, the ZVS techniques can be divided into two categories, i.e., AC-side or DC-side auxiliary circuits [3]. The auxiliary circuit on the AC side is mainly connected in parallel with the AC side of the converter, and thus, the auxiliary circuit has lower voltage stress. However, the system needs three auxiliary circuits for three phases, making it require more space and components. For the DC-side auxiliary circuit, the auxiliary circuit is placed between the DC bus and the main switches, and only one set of auxiliary circuits is needed. However, different auxiliary circuit structures will result in varying voltage stresses on the main switches that are approximately 1 to 3 times the DC link voltage in the rectifiers [4,5,6,7,8] and inverters [2,9,10,11,12,13,14,15,16,17,18,19,20,21]. Active clamping ZVS rectifiers [7,8] and ZVS inverters [2,17,18,19,20,21] with low voltage stress (about 1.01~1.1 times the DC link voltage) were proposed. Nevertheless, extra components, including an active switch, resonant inductor, and clamping capacitor, are required to compose a DC-side auxiliary circuit to achieve zero-voltage switching. Therefore, the ZVS converters without an auxiliary circuit were proposed [1,22,23,24,25]. The advantage of these ZVS converters is not requiring additional components. However, those converters based on critical conduction mode endure high current stress on the main six switches, requiring a third-order LCL filter or even three-phase output current ripple cancellation [25] to eliminate the current ripples. In addition, a bidirectional power flow ZVS operation mechanism in inverter and rectifier modes needs to be carefully considered.

Although the active clamping ZVS method has less current stress on the main switches and only a low-order filter is required, it still suffers from high current stress on the auxiliary switch. In addition, the controls of the six-switch converter for the rectifier mode [7,8] and inverter mode [2,17] are different, and it is not easy to use the same control method to accomplish zero-voltage switching in the bidirectional power flow system. Therefore, in order to realize the bidirectional power flow and maintain fixed switching frequency, the current study combined the active clamping ZVS converter topologies with DPWM and the carrier-based method to reduce the number of switchings and control complexity with the same circuit parameters in both rectifier and inverter modes. The proposed topology can also achieve zero-voltage switching in the six three-phase switches and the auxiliary switch, both in the rectifier mode and inverter mode operations, and only one auxiliary switch is adopted. The reverse recovery currents of body diodes in the main switches were also suppressed. In order to gain a deeper understanding of the development of ZVS techniques, the comparisons of the different ZVS methods in the literature for the ZVS three-phase six-switch converters are summarized in

Table 1. Comparisons of different ZVS methods in the three-phase converters.

Structure	Extra Elements (Structure)	Switching Frequency (fs)	Switch Voltage Stress on Main and Auxiliary Switches	Switch Current Stress on Main/Auxiliary Switches	Filter Design	Bidirectional Operation
[7] Rectifier	LC + switch (3ϕ/3w)	Fixed	Vdc + Vcc ≈ Vdc	Low/Low	LC	None
[8] Rectifier	LC + switch (3ϕ/3w)	Fixed	Vdc	Low/High	LC	None
[2] Inverter	LC + switch (3ϕ/3w)	Fixed	Vdc	Low/High	LC	None
[17] Inverter	LC + switch (3ϕ/3w)	Fixed	Vdc + Vcc ≈ Vdc	Low/Low	LC	None
[19] BTB	LC + switch (3ϕ/4w)	Fixed	Vdc + Vcc ≈ Vdc	Low/Low	LC	None
[20] Inverter	LC + switch (3ϕ/3w)	Fixed	Vdc + Vcc ≈ Vdc	Low/Low	LC	None
[21] Inverter	LC + switch (3ϕ/4w)	Fixed	Vdc + Vcc ≈ Vdc	Low/Low	LC	None
[22] Inverter	None (3ϕ/3w)	Variable	Vdc	High/X	LCL	None
[1] Converter	None (3ϕ/3w)	Variable	Vdc	High/X	LCL	√
[23] Inverter	None (3ϕ/3 or 4w)	Variable	Vdc	High/X	LCL	None
[24] Inverter	None (3ϕ/3w)	Variable (quasi-constant)	Vdc	High/X	LCL	None (inverter full ZVS range)
[25] Inverter	3 passive filters (current ripple cancellation) (3ϕ/3w)	Variable	Vdc	High/X	Transformer, L and C	None
Proposed converter	LC + switch + D (3ϕ/3w)	Fixed	Vdc + Vcc ≈ Vdc	Low/High	LC	√

.

The remainder of this paper is organized as follows. In Section 2, the proposed bidirectional ZVS three-phase converter topology and the modified carrier-based DPWM control scheme are introduced. Based on the topology and DPWM control scheme, the circuit operation principles in the rectifier mode and inverter mode are analyzed in detail, respectively. Some simulation and experimental results are given to verify the validity of the proposed circuit topology and control scheme in Section 3 and Section 4. Finally, some conclusions are offered in Section 5.

2. Proposed Bidirectional ZVS Three-Phase Converter

A bidirectional three-phase AC/DC converter is commonly used as an interface between the AC grid and distributed energy resources (DERs) and/or energy storage systems to facilitate bidirectional power flow and maintain proper AC shaping and DC voltage regulation. As a result, the performance of grid-tied bidirectional three-phase AC/DC converters has received significant attention in renewable energy systems, particularly concerning efficiency.

2.1. Proposed Circuit Topology and PWM Strategy

The proposed bidirectional grid-tied ZVS three-phase converter is shown in Figure 1, which is composed of a standard six-switch converter with an LC filter on the AC side and a bidirectional auxiliary resonant circuit on the DC side. In order to achieve bidirectional power flow, the voltage-oriented control (VOC) method is used to control the converter. In order to achieve soft switching, the proposed pulse-width modulation strategy ZVS DPWM shown in Figure 2 is used, where the control signals can be divided into 12 sectors during each line cycle. The positive/negative slope of the sawtooth carrier is decided using the DPWM and operation mode to generate the switching sequence and the selected zero vectors both in the rectifier mode and inverter mode, as shown in Figure 2a. While the converter is operated in the rectifier (inverter) mode and the controlled DPWM signals reach the maximum value, the slope of the sawtooth carrier is positive (negative). In contrast, when the DPWM signals reach the minimum value, the slope of the sawtooth carrier is negative (positive). While the DPWM control signal is a generalized DPWM (GDPWM) method, DPWM1 [26] was adopted in this study. By adding the zero-sequence signal to the three original modulation waves V*_a, V*_b and V*_c, the GDPWM waves V**_a, V**_b and V**_c are generated. Assuming |V*_a| ≥ |V*_b| and |V*_c|, then the zero sequence signal is v₀ = (sign(V*_a))(V_dc/2) − V*_a.

Within the proposed carrier-based control strategy, the choice of zero vectors, namely, V₀ and V₇, is depicted in Figure 2b. The control signal for the auxiliary switch S₇ is then computed to achieve ZVS in both the main S₁–S₆ switches and the auxiliary S₇ switch during both rectifier and inverter operational modes.

• Rectifier Mode

In the rectifier mode, the switching scheme of the carrier is illustrated in Figure 2. When the control signal is clamped at +V_dc/2, the falling sawtooth waveform is employed for that interval, whereas when the voltage clamp is set at −V_dc/2, the rising sawtooth waveform is used for that interval. Combining this with DPWM1, the switching sequence shown in

Table 2. Switching sequence operated in the rectifier mode.

Sector	Vector
1	111 → 110 → 100 → 111
2	000 → 100 → 110 → 000
3	000 → 010 → 110 → 000
4	111 → 110 → 010 → 111
5	111 → 011 → 010 → 111
6	000 → 010 → 011 → 000
7	000 → 001 → 011 → 000
8	111 → 011 → 001 → 111
9	111 → 101 → 001 → 111
10	000 → 001 → 101 → 000
11	000 → 100 → 101 → 000
12	111 → 101 → 100 → 111

is generated. Taking interval 01 as an example for analysis, the modulation sequence of the switches is 111 → 110 → 100 → 111.

B.

Inverter Mode

For the inverter mode, the switching scheme of the carrier is depicted in Figure 2. When the voltage clamp is set at +V_dc/2, the rising sawtooth waveform is utilized for that interval, while when the voltage clamp is positioned at −V_dc/2, the falling sawtooth waveform is employed for that interval. As a result, the sawtooth waveform undergoes a transition every 60 degrees. Combining this with DPWM1, the switching sequence illustrated in

Table 3. Switching sequence operated in the inverter mode.

Sector	Vector
1	111 → 100 → 110 → 111
2	000 → 110 → 100 → 000
3	000 → 110 → 010 → 000
4	111 → 010 → 110 → 111
5	111 → 010 → 011 → 111
6	000 → 011 → 010 → 000
7	000 → 011 → 001 → 000
8	111 → 001 → 011 → 111
9	111 → 001 → 101 → 111
10	000 → 101 → 001 → 000
11	000 → 101 → 100 → 000
12	111 → 100 → 101 → 111

is generated. Taking interval 01 as an example for analysis, the modulation sequence of the switches is 111 → 100 → 110 → 111.

By employing the proposed DPWM strategy and the zero-vector selection illustrated in Figure 2, it becomes feasible to derive a twelve-sector switch modulation sequence within a line cycle. Take sector 1 as an example, and assume the three-phase current i_a > 0 > i_b > i_c. For a convenient explanation of how the proposed modulation scheme works, the theoretical key waveforms during the sector 1 operation in both rectifier and inverter modes are illustrated in Figure 3 and the following assumptions are made to simplify the operation principle analysis of the bidirectional grid-tied ZVS three-phase converter.

(1)

The main switches S₁–S₆ and auxiliary switch S₇ are considered ideal switches with their anti-paralleled diodes (body diodes). The body diodes of switches S₁~S₇ are named D₁~D₇, respectively.

(2)

All of the parasitic capacitances C_r1–C_r7 are in parallel with the switches S₁–S₇, respectively. Suppose C_r1 = C_r2 = ⋯ = C_r6.

(3)

The clamping capacitor C_c possesses a substantial capacitance, resulting in a minor voltage ripple across it. As a consequence, the voltage v_Cc can be treated akin to a voltage source.

(4)

The operational frequency of the converter is significantly higher than the resonant frequency of the LC filter on the AC side.

(5)

The current i_sx, where x belongs to the set {1, 2, …, 7}, characterizes the switch current incorporating the parasitic capacitor current. Meanwhile, the current i_cex, with x also within the set {1, 2, …, 7}, represents the switch current after eliminating the parasitic capacitor contribution. The voltage v_cex, x∈{1, 2, …, 7}, represents the switch voltage. v_cr denotes the resonant capacitor voltage.

2.2. Rectifier Mode Operation

In order to understand the proposed control strategy in this topology operated in rectified mode, the steady-state key waveforms in sector 1 are shown in Figure 3a. The vector sequence during this sector is 111-110-100-111, as shown in Figure 4a. The corresponding operation state is explained as follows, and the equivalent circuit in each state is illustrated in Figure 5a.

State 1 (t₀~t₁): The circuit state is operated in vector V₁(100). D₁, D₄, D₆, D_rec and S₇ are in the conducting state; D_inv is turned off; and the resonant inductor L_r is magnetized by clamping capacitor C_c, which can be expressed by (1). The energy flows from the AC side to the DC side.

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{v_{Cc}}{L_r}$$

(1)

State 2 (t₁~t₂): At instant t₁, S₇ is turned off, and L_r resonates with C_r2, C_r3, C_r5 and C_r7. C_r2, C_r3 and C_r5 are discharged and C_r7 is charged. The energy flows from the AC side to the DC side. The state equations for L_r, C_r and C_C can be expressed as shown in (2) and (3).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=-\frac{{(v}_{dc}-v_{Cr}\left(t\right))}{L_r}$$

(2)

$$-3C_r\frac{d{v}_{C_r}\left(t\right)}{dt}+C_{r7}\frac{d{(v}_{Cc}+V_{dc}-v_{Cr}\left(t\right))}{dt}=i_{Lr}\left(t\right)-i_a(t)$$

(3)

State 3 (t₂~t₃): In this stage, the circuit state becomes vector V₇(111). The voltages on C_r2, C_r3 and C_r5 drop to zero, and the body diodes on the six main switches are conducting at t₂. Then, S₃ and S₅ are turned on via ZVS at instant t₂. The diode reverse recovery current in S₂ is suppressed by L_r. The voltage on C_r7 oscillates to be V_o + v_Cc. The energy flows from the AC side to the DC side. The state equations for L_r and V_dc can be expressed as shown in (4).

$$\frac{\mathrm{d}{i}_{Lr}\left(t\right)}{dt}=-\frac{V_{dc}}{L_r}$$

(4)

State 4 (t₃~t₄): The circuit is still operated in vector V₇(111) and the body diode of switch S₆ is conducting. The AC-side circuit becomes a loop. The diode reverse recovery current in S₄ is suppressed by L_r. The current of L_r is charged by V_dc. The state equations for the L_r can be expressed as shown in (5).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=-\frac{V_{dc}}{L_r}$$

(5)

State 5 (t₄~t₅): The circuit is still operated in vector V₇(111) but the body diode of S₆ is turned off. L_r resonates with C_r2, C_r4, C_r6 and C_r7. The capacitors C_r2, C_r4 and C_r6 are charged and C_r7 is discharged. The voltage of switch S₇ is decreased to zero at time t₅. The diode reverse recovery current in S₆ is suppressed by L_r, and the energy of the inductor L_r is restored to the AC side. The diode states in the auxiliary circuit are changed. D_inv is conducting and D_rec is turned off. The state equations for L_r and C_r can be expressed as shown in (6) and (7).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=-\frac{(V_{dc}-v_{Cr}\left(t\right)-v_{Cc})}{L_r}$$

(6)

$$3C_r\frac{d{v}_{Cr}\left(t\right)}{dt}-C_{r7}\frac{d{(V}_{dc}-v_{Cr}\left(t\right))}{dt}={-i}_{Lr}\left(t\right)$$

(7)

State 6 (t₅~t₆): The circuit state is still operated in vector V₇(111). S₇ is turned on via ZVS at instant t₅. Both D_inv and D_rec are turned off. The capacitor C_c is charged by L_r, which can be described by (8).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{V_{Cc}}{L_r}$$

(8)

State 7 (t₆~t₇): The circuit state becomes vector V₂(110). The phase current i_c is discharging C_r6 and C_r5. The D_rec is conducting and D_inv is turned off. The energy flows from the AC side to the DC side. The state equation relationships between L_r, C_r and C_c can be expressed by (9) and (10).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{V_{Cc}}{L_r}$$

(9)

$$i_c\left(t\right)=-C_{r6}\frac{d{v}_{C_{r6}}\left(t\right)}{dt}+C_{r5}\frac{d{v}_{C_{r5}}\left(t\right)}{dt}$$

(10)

State 8 (t₇~t₈): The circuit remains in operation within vector V₂(110). The body diode of switch S₆ is in a conductive state. Power continues to transfer from the AC side to the DC side. C_c is charged by L_r, which can be expressed by (11).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{v_{Cc}}{L_r}$$

(11)

State 9 (t₈~t₉): The circuit state changes from vector V₂(110) to vector V₁(100). The phase current i_b is charging C_r3 and discharging C_r4. The energy flows from the AC side to the DC side. The state equations for L_r and C_r can be expressed as shown in (12) and (13).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{v_{Cc}}{L_r}$$

(12)

$$i_b\left(t\right)=-C_{r4}\frac{d{v}_{Cr4}\left(t\right)}{dt}+C_{r3}\frac{d{v}_{Cr3}\left(t\right)}{dt}$$

(13)

2.3. Inverter Mode Operation

In order to understand the proposed control strategy in the proposed topology operated in inverter mode, the steady-state key waveforms in sector 1 are shown in Figure 3b. The vector sequence during this sector is 111-100-110-111, as shown in Figure 4b. The corresponding operation state is explained as follows, and the equivalent circuit in each state is illustrated in Figure 5b.

State 1 (t₀~t₁): The circuit functions while in vector state 111, where switch S₁, auxiliary switch S₇, and anti-parallel diodes D₃ and D₅ are on. The inverter operates under a zero-vector condition. The resonant inductor L_r is charged through the clamping voltage v_Cc. D_inv and D_rec are turned off. The corresponding equivalent circuit is depicted in Figure 5b, and the relationship between L_r and C_c is described by (14).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{v_{Cc}}{L_r}$$

(14)

State 2 (t₁~t₂): The resonant inductor L_r exhibits resonance, along with C_r2, C_r4, C_r6 and C_r7. During this state, switches S₃ and S₅ are turned off. Excess energy flows back to the distributed energy storage system or capacitor via D_rec. Figure 5b illustrates the corresponding equivalent circuit, and the relationships between C_c, C_r and L_r can be expressed as shown in (15) and (16).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{{(v}_{Cr}\left(t\right)-V_{dc})}{L_r}$$

(15)

$$-3C_r\frac{d{v}_{Cr}\left(t\right)}{dt}+C_{r7}\frac{d\left(V_{dc}-v_{Cr}\left(t\right)-v_{Cc}\right)}{dt}=i_{Lr}(t)$$

(16)

State 3 (t₂~t₃): During this state, the circuit functions in vector state 100. The voltages across C_r2, C_r4 and C_r6 are discharged to zero, while the voltage across C_r7 is elevated to V_DC. The anti-paralleled diodes D₂, D₃, D₄, D₅ and D₆ are on. Under ZVS conditions, at time instant t₂, the switches S₄ and S₆ are turned on, while the resonant inductor L_r mitigates the reverse recovery current in the anti-parallel diode D₃. D_inv is still turned off and D_rec is still turned on. Excess energy still flows back to the distributed energy storage system or capacitor via D_rec. Energy recycling is achieved. Figure 5b illustrates the corresponding equivalent circuit, and the relationship between i_Lr and v_Cc is expressed by (17).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=-\frac{V_{dc}}{L_r}$$

(17)

State 4 (t₃~t₄): The main switches S₁, S₄ and S₆ are held in the on state, while the resonant inductor L_r mitigates the reverse recovery current in the anti-parallel diodes D₂ and D₅. D_inv is turned on and D_rec is turned off. The power flow is transferred from the DC side to the AC side. The corresponding equivalent circuit is depicted in Figure 5b, and the relationship between i_Lr and v_Cc is formulated in (18).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=-\frac{{(V}_{dc}-v_{Cc})}{L_r}$$

(18)

State 5 (t₄~t₅): Resonance is established in the resonant inductor L_r in conjunction with C_r2, C_r3, C_r5 and C_r7. The anti-paralleled diode D₇ prepares to turn on at t₅. During this state, C_r2, C_r3 and C_r5 are charged and C_r7 is discharged. D_inv is in the on state and D_rec is in the off state. The power continues to transfer from the DC side to the AC side. The corresponding equivalent circuit is depicted in Figure 5b, and the relationships between i_Lr, v_cr and v_Cc is described in (19) and (20).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{V_{Cc}-V_{dc}+v_{Cr}\left(t\right)}{L_r}$$

(19)

$$3C_r\frac{d{v}_{Cr}\left(t\right)}{dt}+i_a\left(t\right)=C_{r7}\frac{d\left(V_{dc}-v_{Cr}\left(t\right)\right)}{dt}-i_{Lr}(t)$$

(20)

State 6 (t₅~t₆): At this time, the circuit remains functional in vector state 100, with the main switches S₁, S₄ and S₆ in the on state. The auxiliary switch S₇ is turned on under the ZVS condition. The voltage across the clamping capacitor v_Cc is charged through the resonant inductor current i_Lr. D_inv is conducting, D_rec is non-conducting and power is directed from the DC side to the AC side. The equivalent circuit is depicted in Figure 5b, and the relationship between i_Lr and v_Cc is expressed in (21).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{v_{Cc}}{L_r}$$

(21)

State 7 (t₆~t₇): At this time, the circuit functions in vector state 100. The current in phase i_b results in the discharge of voltage across v_Cr3 while simultaneously charging the voltage across v_Cr4. D_inv is conducting, while D_rec remains non-conductive, allowing power to transition from the DC side to the AC side. The equivalent circuit is illustrated in Figure 5b, and the relationships between v_Cr3, v_Cr4 and i_Lr are shown in (22) and (23).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{v_{Cc}}{L_r}$$

(22)

$$i_b\left(t\right)=-C_{r3}\frac{d{v}_{Cr3}\left(t\right)}{dt}+C_{r4}\frac{d{v}_{Cr4}\left(t\right)}{dt}$$

(23)

State 8 (t₇~t₈): During this state, the circuit operates in vector state 110. The main switches S₁ and S₆, alongside the auxiliary switch S₇ and the anti-parallel diode D₃, are concurrently conducting. D_inv is in the on state and D_rec is in the off state. Power continues to transfer from the DC side to the AC side. The corresponding equivalent circuit is displayed in Figure 5b, and the relationship between i_Lr and v_Cc is shown in (24).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{v_{Cc}}{L_r}$$

(24)

State 9 (t₈~t₉): During this state, the circuit remains in operation within vector state 110. The phase current i_c leads to the depletion of voltage across v_Cr5, while simultaneously charging the voltage across v_Cr6. D_inv is in the on state and D_rec is in the off state, allowing power transfer from the DC side to the AC side. The depicted equivalent circuit is illustrated in Figure 5b. Subsequent to this state, the circuit’s operation reverts to the initial stage, commencing a new cycle. The relationships between the voltage and current across the inductor and capacitor are shown in (25) and (26).

$$\frac{d{i}_{Lr}\left(t\right)}{dt}=\frac{v_{Cc}}{L_r}$$

(25)

$$i_c\left(t\right)=-C_{r5}\frac{d{V}_{Cr5}\left(t\right)}{dt}+C_{r6}\frac{d{v}_{Cr6}\left(t\right)}{dt}$$

(26)

2.4. Control Scheme

In order to control the bidirectional grid-tied three-phase converter via ZVS with the proposed modulation scheme, the control block shown in Figure 6 is used. Based on the voltage-oriented control scheme, the AC grid voltages, the DC DERs/load voltage, and AC-side currents are sensed and fed into the A/D converters, and then the phase lock loop (PLL) is utilized to synchronize the AC grid voltage. Thus, the control signals in the abc nature reference frame are transformed into the d-q synchronous reference frame. To achieve the bidirectional power flow control, the d-axis current command is utilized to judge the power flow direction (PFD) and generate the corresponding DPWM modulation control scheme and main and auxiliary switch control signals to achieve zero-voltage switching, both in the rectifier and inverter operations. Meanwhile, the reverse recovery currents of body diodes in the main switches are also suppressed.

2.5. Circuit Design

To achieve zero-voltage switching in a bidirectional grid-tied three-phase converter, the state-plane trajectory is considered to design the inductor and capacitor of the proposed circuit.

Considering the system operated at the state 2 (t₁~t₂) in sector 1 under the rectifier mode and according to Equations (2) and (3), one can obtain

$$\left\{\begin{array}{c}{v}_{Cr}(t)=V_{dc}+V_{Cc}\cos \omega t-Z(i_{Lr.\max }-i_a)\sin \omega t\\ i_{Lr}(t)=i_a+\frac{1}{Z}{V}_{Cc}\sin \omega t+(i_{Lr.\max }-i_a)\cos \omega t\end{array}\right.$$

(27)

where Z is the characteristic impedance, which is defined as

$$Z=\sqrt{L_r/(3C_r+C_{r7})}$$

(28)

While all the sectors 1–12 are considered in the rectifier mode operated in state 2 (t₁~t₂), the generalized circuit expression can be derived:

$$\{\begin{array}{c}{L}_r\frac{d{i}_{Lr}(t)}{dt}=-V_{dc}+v_{Cr}(t)\\ -C_r\frac{d{v}_{Cr}(t)}{dt}=i_{Lr}(t)-\max (\left|i_a\right|,\left|i_b\right|,\left|i_c\right|)\end{array}$$

(29)

Then, the generalized solution for the ZVS rectifier resonant circuit can be expressed as follows

$$\{\begin{array}{ll}{v}_{Cr}(t)=& V_{dc}+V_{Cc}\cos \omega t-Z(i_{Lr.\max }-\max (\left|i_a\right|,\left|i_b\right|,\left|i_c\right|))\sin \omega t\\ i_{Lr}(t)=& \max (\left|i_a\right|,\left|i_b\right|,\left|i_c\right|)+\frac{1}{Z}{V}_{Cc}\sin \omega t\\ & +(i_{Lr.\max }-\max (\left|i_a\right|,\left|i_b\right|,\left|i_c\right|))\cos \omega t\end{array}$$

(30)

According to (30), the ZVS rectifier resonant circle can be illustrated in Figure 7a, where R_REC is the radius of the ZVS rectifier resonant circle.

$$R_{REC}=\sqrt{V_{Cc}{}^2+{(Z(i_{Lr.\max }-\max (\left|i_a\right|,\left|i_b\right|,\left|i_c\right|)))}^2}$$

(31)

Similarly, considering the system operated under the inverter mode at the state 2 (t₁~t₂) for sectors 1–12, the generalized circuit expression also can be derived as follows:

$$\{\begin{array}{c}{v}_{Cr}(t)=V_{dc}-V_{Cc}+V_{Cc}\cos \omega t-Z{i}_{Lr.\max }\sin \omega t\\ i_{Lr}(t)=\frac{1}{Z}{V}_{Cc}\sin \omega t+i_{Lr.\max }\cos \omega t\end{array}$$

(32)

According to (32), the ZVS inverter resonant circle can be illustrated in Figure 7b, where R_INV is the radius of the ZVS inverter resonant circle.

$$R_{INV}=\sqrt{V_{Cc}{}^2+{(Z{i}_{Lr.\max })}^2}$$

(33)

In order to achieve the zero-voltage switching function, the radii of the ZVS rectifier and ZVS inverter must be greater than V_dc and V_dc–V_Cc, respectively. Therefore, the following equations must be satisfied.

In the ZVS rectifier:

$$\sqrt{V_{Cc}{}^2+{(Z(i_{{}_{Lr,\max }}-\max (\left|i_a(t)\right|,\left|i_b(t)\right|,\left|i_c(t)\right|)))}^2}>V_{dc}$$

(34)

In the ZVS inverter:

$$\sqrt{V_{Cc}{}^2+{(Z{i}_{Lr,\max })}^2}>V_{dc}-V_{Cc}$$

(35)

For a convenient design, (34) and (35) can be simplified as follows:

In the ZVS rectifier:

$$Z^2>\frac{V_{dc}^2-V_{Cc}^2}{{(i_{Lr,\max }-\max (\left|i_a(t)\right|,\left|i_b(t)\right|,\left|i_c(t)\right|))}^2}\approx \frac{V_{dc}^2-V_{Cc}^2}{\Delta i_{Lr,REC}^2}$$

(36)

In the ZVS inverter:

$$Z^2>\frac{{(V_{dc}-V_{cc})}^2-V_{Cc}^2}{{(i_{Lr,\max })}^2}\approx \frac{{(V_{dc}-V_{cc})}^2-V_{Cc}^2}{\Delta i_{Lr,INV}^2}$$

(37)

where Δi_Lr,REC and Δi_Lr,INV are half of the peak-to-peak inductor current ripples.

Hence, to accomplish the ZVS bidirectional converter, one can choose a proper capacitor C_C and then the resonant inductor L_r must satisfy both (36) and (37) to achieve V_cr = 0, as shown in Figure 7, before the switches are turned on.

2.6. Controller Design

In order to achieve bidirectional power flow control with ZVS, a dynamic model is needed. Because the auxiliary circuit is operated during the original switching time of the main six switches, there is no influence on the control of the original six-switch converter. Therefore, the dynamic model of the proposed converter in the d-q frame is

$$v_d=R{i}_d+L\frac{d{i}_d}{dt}-\omega L{i}_q+S_d{v}_{dc}$$

(38)

$$v_q=R{i}_q+L\frac{d{i}_q}{dt}+\omega L{i}_d+S_q{v}_{dc}$$

(39)

$$C_{dc}\frac{d{v}_{dc}}{dt}=\left(i_d{S}_d+S_q{i}_q\right)-i_{dc}$$

(40)

where R is the equivalent series resistance on the grid side. $v_d$ and $v_q$ are the d-axis and q-axis grid voltages in the synchronous frame, respectively. The $i_d$ and $i_q$ are the d-axis and q-axis grid currents in the synchronous frame, respectively. S_d and S_q are the state-averaged control signals in the d-q frame.

Since the DC output power is only contributed to by the $i_d$ current and the $i_q$ current is negligible, (40) can be rewritten as

$$C_{dc}\frac{d{v}_{dc}}{dt}=\left[K_P^v\left(v_{dc}^{*}-v_{dc}\right)+\int K_I^v\left(v_{dc}^{*}-v_{dc}\right)dt\right]S_d-\frac{v_{dc}}{R_L}$$

(41)

where $R_L$ is the DC side load. $K_P^v$ and $K_I^v$ are the DC bus voltage proportional–integral (PI) compensators. Differentiating (41) with respect to time yields

$$C_{dc}\ddot{v_{dc}}=\left[K_P^v\left(\dot{v_{dc}^{*}}-\dot{v_{dc}}\right)+K_I^v\left(v_{dc}^{*}-v_{dc}\right)\right]S_d-\frac{\dot{v_{dc}}}{R_L}$$

(42)

Applying the Laplace transform to (42), the outer voltage loop transfer function gives

$$\frac{v_{dc}}{v_{dc}^{*}}=\frac{\left(K_P^{v}s+K_I^v\right)\frac{S_d}{C_{dc}}}{s^2+\frac{\left(K_P^v{S}_d+\frac{1}{R_L}\right)}{C_{dc}}s+\frac{K_I^v{S}_d}{C_{dc}}}$$

(43)

Therefore, the PI compensator $K_P^v$ and $K_I^v$ of the outer voltage control loop can be designed according to (43).

Next, consider the inner current control loop. In (38) and (39), the decoupled terms $\omega L{i}_d$ and $\omega L{i}_q$ can be directly added into the d-q control frame, and thus, $S_d$ and $S_q$ have no coupled terms. Therefore, $S_d$ and $S_q$ can be expressed as

$$S_d=K_{Pd}^i\left(i_d^{*}-i_d\right)+\int K_{Id}^i\left(i_d^{*}-i_d\right)dt$$

(44)

$$S_q=K_{Pq}^i\left(i_q^{*}-i_q\right)+\int K_{Iq}^i\left(i_q^{*}-i_q\right)dt$$

(45)

where $K_{Pd}^i$, $K_{Id}^i$ and $K_{Pq}^i$, $K_{Iq}^i$ are the d-axis and q-axis PI compensators of the inner current control loop, respectively. Assume the amplitude of the input voltage is constant. Differentiating (38) and (39) with respect to time yields

$$0=R\dot{i_d}+L\ddot{i_d}+\left[K_{Pd}^i\left(\dot{i_d^{*}}-\dot{i_d}\right)+K_{Id}^i\left(i_d^{*}-i_d\right)\right]v_{dc}$$

(46)

$$0=R\dot{i_q}+L\ddot{i_q}+\left[K_{Pq}^i\left(\dot{i_q^{*}}-\dot{i_q}\right)+K_{Iq}^i\left(i_q^{*}-i_q\right)\right]v_{dc}$$

(47)

Applying the Laplace transform to (46) and (47), the inner current-loop transfer functions for d-axis and q-axis gives

$$\frac{i_d}{i_d^{*}}=-\frac{\left(s{K}_{Pd}^i+K_{Id}^i\right)\frac{v_{dc}}{L}}{s^2+\frac{\left(R-K_{Pd}^i{v}_{dc}\right)}{L}s-\frac{{K_{Id}^{i}v}_{dc}}{L}}$$

(48)

$$\frac{i_q}{i_q^{*}}=-\frac{\left(s{K}_{Pq}^i+K_{Iq}^i\right)\frac{v_{dc}}{L}}{s^2+\frac{\left(R-K_{Pq}^i{v}_{dc}\right)}{L}s-\frac{{K_{Iq}^{i}v}_{dc}}{L}}$$

(49)

The PI compensator of the inner current control loop can be derived by the linear time-invariant dynamic model (48) and (49). It is also important to note that the bandwidth of the inner current loop must be broader than that of the outer voltage loop.

3. Simulation Results

In order to verify the validity of the proposed circuit topology and corresponding modulation strategy, the simulation software Power SIM Version 9.1.1.400 was adopted and the simulation was conducted using the system parameters listed in

Table 4. Simulation and experimental parameters of the proposed bidirectional ZVS three-phase converter.

Parameters	Value	Unit
AC grid line voltage (rms)	220	V
DC link voltage, Vdc	450	V
Switching frequency, fs	18	kHz
Three-phase inductors, La,b,c	2	mH
Three-phase capacitors Cga,b,c	22	μF
DC-link capacitor, Cdc	2200	μF
Parasitic capacitance, Cr	2	nF
Resonant inductor, Lr	40	μH
Clamping capacitor, Cc	100	μF
Power rating, Prate	3	kW

according to the circuit design in Section 2.5. The parameters that were designed and selected could cause both the main and auxiliary switches to achieve soft switching, and the body diode reverse recovery current suppressed by inductor L_r. In this implementation, the IGBT FUJI 2MBI100VA-120-50 was utilized as the power switch. Therefore, a simulated parasitic capacitor C_r = 2 nF, resonant inductor L_r = 40 uH and clamping capacitor C_c = 100 μF were selected.

First, consider the proposed bidirectional grid-tied ZVS three-phase converter that was operated in the rectifier mode. The simulation waveforms of the switch voltage and current for the main switches S₃ and S₄ are shown in Figure 8a and Figure 8b, respectively. As can be observed from Figure 8a,b, S₃ was turned on under the ZVS condition, and the diode reverse recovery current in S₄ could be suppressed when S₄ was turned off. Figure 8c shows the voltage and current waveforms of auxiliary switch S₇, and one can find that S₇ was turned on under the ZVS condition. The voltage of the clamping capacitor v_Cc and the current of the resonant inductor i_Lr are shown in Figure 8d. As can be seen from Figure 8d, v_Cc was much smaller than V_dc such that the voltage stress on the main and auxiliary switches was v_cc + V_dc ≈ V_dc. Figure 8e,f show the voltage and current waveforms of diodes D_inv and D_rec, respectively. It follows from Figure 8e,f that the diode voltage stress v_Cc was much smaller than V_dc.

Next, consider the proposed bidirectional grid-tied ZVS three-phase converter that was operated in the inverter mode. The simulation waveforms of switch voltage and current for the main switches S₄ and S₃ are shown in Figure 9a and Figure 9b, respectively. As can be observed from Figure 9a,b, S₄ was turned on under the ZVS condition, and the diode reverse recovery current in S₃ could be suppressed when S₃ was turned off. Figure 9c shows the voltage and current waveforms of auxiliary switch S₇, and it can be seen from Figure 9c that S₇ was turned on under the ZVS condition. The voltage of the clamping capacitor v_Cc and the current of the resonant inductor i_Lr are shown in Figure 9d. It follows from Figure 9d that v_Cc was much smaller than V_dc such that the voltage stress on the main and auxiliary switches was v_cc + V_dc ≈ V_dc. The voltage and current waveforms of diodes D_inv and D_rec are shown in Figure 9e and Figure 9f, respectively. As can be observed from Figure 9e,f, the diode voltage stress was v_Cc, which was the same as that in the rectifier mode and was much smaller than V_dc.

In order to gain further insight into the operation of zero-voltage switching and the suppression of the reverse-recovery current in the proposed bidirectional grid-tied ZVS three-phase converter, the simulation process was carried out when the system was operated in both rectifier and inverter modes. The simulated ZVS process of switch S₃ in the rectifier mode is shown in Figure 10. It should be noted that the switch current i_sx, x∈{1, 2, …, 7}, was defined as i_sx = i_cex + i_crx, which includes the parasitic capacitor current i_crx, but the switch current i_cex did not include the parasitic capacitor current i_crx. The plots of i_s3 versus v_ce3, i_ce3 versus v_ce3 and i_cr3 versus v_ce3 are shown in Figure 10a, Figure 10b and Figure 10c, respectively. Figure 10d shows the overlap plot of Figure 10a–c. As can be observed from Figure 10, the ZVS on was indeed achieved in the main switch S₃ in the rectifier mode. The simulated reverse-recovery-current suppression of switch S₄ in the rectifier mode is shown in Figure 11. The plots of i_s4 versus v_ce4, i_ce4 versus v_ce4 and i_cr4 versus v_ce4 are shown in the Figure 11a, Figure 11b and Figure 11c, respectively. Figure 11d shows the overlap plot of Figure 11a–c. As can be seen from Figure 11, the suppression of the diode reverse-recovery process of switch S₄ was indeed completed in the rectifier mode. The plots of i_s7 versus v_ce7, i_ce7 versus v_ce7 and i_cr7 versus v_ce7 are shown in the Figure 12a, Figure 12b and Figure 12c, respectively. Figure 12d shows the overlap plot of Figure 12a–c. It follows from Figure 12 that the ZVS on was indeed achieved in the auxiliary switch S₇ in the rectifier mode.

Similarly, the process of the ZVS operation and reverse-recovery-current suppression in the proposed bidirectional grid-tied ZVS three-phase converter operated in inverter mode are shown in Figure 13, Figure 14 and Figure 15. As can be observed from Figure 13, Figure 14 and Figure 15, the ZVS on of main switch S₄, the reverse-recovery-current suppression of main switch S₃ and the ZVS on of auxiliary switch S₇ were indeed achieved in the inverter mode.

The simulated waveforms of the DC bus voltage V_dc, phase-a voltage V_a and current i_a of the proposed bidirectional grid-tied ZVS converter operated in rectifier mode and inverter mode are shown in Figure 16a and Figure 16b, respectively. As can be seen from Figure 16, when the system was operated in the rectifier mode, the controlled grid-side current was in phase with the grid voltage, and when the system was operated in the inverter mode, the controlled grid-side current was phase-shifted by 180 degrees from the grid voltage.

According to the above simulation results, the proposed circuit topology and corresponding PWM control scheme could accomplish zero-voltage switching in the main switches and the auxiliary switch in both the rectifier and inverter modes. Meanwhile, the reverse recovery current of body diodes in the main switches was also suppressed.

4. Experimental Results

To facilitate the understanding of the proposed circuit topology and corresponding modulation control strategy, as well as provide verification, a prototype system was constructed with the parameters listed in Table 4. The adopted active switches were the insulated gate bipolar transistors (FUJI 2MBI100VA-120-50) with a parasitic capacitance C_r = 2 nF, and the system controller was implemented with DSP TMS320F28335/FPGA Cmod-A7-35T.

Figure 17 and Figure 18 show the experimental waveforms when the proposed circuit was operated in the rectifier mode and inverter mode, respectively. While the system was operated in the rectifier mode, the measured switch voltage and current of switches S₃, S₄ and S₇ are shown in Figure 17a–c, respectively. As can be seen from Figure 17a–c, the main switch S₃ and auxiliary switch S₇ were turned on via ZVS, and the diode reverse recovery current of main switch S₄ was also suppressed when the system was operated in the rectifier mode. The voltage v_Cc of the clamping capacitor and the current i_Lr of the resonant inductor are shown in Figure 17d. It follows from Figure 17d that v_Cc was much smaller than V_dc such that the voltage stress on the main and auxiliary switches was v_cc + V_dc ≈ V_dc. The voltage and current waveforms of diodes D_inv and D_rec are shown in Figure 17e and Figure 17f, respectively. As can be observed from Figure 17e,f, the diode voltage stress is v_Cc. It should be noticed that the experimental waveforms of diode voltage and current in Figure 17e,f are in close agreement with the simulation waveforms in Figure 8e,f. The voltage across the two series diodes was v_Cc = v_dinv + v_drec.

While the system was operated in the inverter mode, the measured switch voltage and current of switches S₄, S₃ and S₇ are shown in Figure 18a–c, respectively. As can be seen from Figure 18a–c, the main switch S₄ and auxiliary switch S₇ were turned on via ZVS, and the diode reverse recovery current of main switch S₃ was also suppressed. The voltage v_Cc of the clamping capacitor and the current i_Lr of the resonant inductor are shown in Figure 18d. It follows from Figure 18d that v_Cc was much smaller than V_dc such that the voltage stress on the main and auxiliary switches was v_cc + V_dc ≈ V_dc. In addition, the voltage and current waveforms of diodes D_inv and D_rec are shown in Figure 18e and Figure 18f, respectively. It follows from Figure 18e,f that the diode voltage stress was v_Cc, and the total voltage across the two series diodes was v_Cc = v_dinv + v_drec.

In addition, the light load condition of 300 W for 10% of the rated output power was considered. The rectifier and inverter operations are shown in Figure 19a,b and Figure 19c,d, respectively. As can be observed from Figure 19a,b, the auxiliary switch S₇ and main switch S₃ were turned on via ZCS/ZVS when the converter was operated in the rectifier mode. It follows from Figure 19c,d that the auxiliary switch S₇ and main switch S₄ were also turned on via ZCS/ZVS when the converter was operated in the inverter mode.

Finally, in order to understand the bidirectional power flow functionality of the proposed ZVS grid-tied three-phase converter, the measured waveforms of the DC bus voltage V_dc, phase-a voltage V_a and current i_a in both rectifier mode (3 kW) and inverter mode (3 kW) are depicted in Figure 20a and Figure 20b, respectively. According to the control block illustrated in Figure 6, the bidirectional power flow was achieved in the proposed grid-tied ZVS three-phase converter.

Next, the efficiency was measured using three YOKOGAWA WT310Es. Compared with the traditional hard switching SPWM without an auxiliary circuit, the measured efficiency of the proposed circuit topology and control scheme in the rectifier mode and inverter mode was 3~4% higher than that of the hard switching control scheme, which is illustrated in Figure 21. The realized prototype of the proposed system is shown in Figure 22.

Finally, the current total harmonic distortion THD_i and power losses were analyzed. Figure 23 shows the THD_i versus output power for both rectifier and inverter operation. As depicted in Figure 23, it is evident that the higher the output power, the lower THD_i became. Next, the power loss distributions are shown in Figure 24 and Figure 25 for the rectifier mode and inverter mode, respectively. In the power loss distribution, the IGBT Semikron SKM200GB125D and diode Powerex CS240650 were adopted in the simulation software to analyze the conduction loss, turn-off loss, diode loss, copper loss and core loss. As can be seen from Figure 24 and Figure 25, the total power loss during inverter operation was higher than that during rectifier operation due to the difference in auxiliary circuit paths between the inverter and rectifier operations.

5. Conclusions

This paper proposed a bidirectional grid-tied ZVS three-phase converter topology. In addition, a zero-voltage-switching PWM strategy for a grid-connected three-phase converter is proposed. The control signal for the auxiliary switch is produced using a sawtooth carrier waveform encompassing both positive and negative gradients. This approach is utilized to attain ZVS across both the main and auxiliary switches. Furthermore, the reverse recovery currents in the anti-parallel diodes of the main switches are effectively mitigated. The operational principles of the circuit are extensively elucidated for both rectifier and inverter modes. Both simulation and experimental results verified the validity of the proposed circuit topology and the proposed ZVS DPWM strategy in the bidirectional grid-tied three-phase system. The measured efficiency of the proposed system was about 3~4% higher than that of a conventional SPWM hard-switching system. It is worth mentioning that the soft switching strategies usually suffer from high voltage and current stress of the semiconductors, which will decrease the power rating of the original design. The proposed topology and PWM control scheme also had those limitations.