Simulation of Series Resistance Increase through Solder Layer Cracking in Si Solar Cells under Thermal Cycling

Abstract

In solar cell modules, thermal cycling stresses can cause cracking in the ribbon wire, leading to an increase in series resistance and a drop in the power output of the module. Quantitative analysis was conducted to study the increase in series resistance, considering two cracking models: continuous and random. In the continuous model, it was expected that if all the ribbon wires on the front side of the module cracked, the current would decrease linearly from 0 to 100%, and the series resistance would increase exponentially to infinity. In the random crack model, the current dropped slowly, and the series resistance increased less compared with that in the continuous one. A mathematical model based on the bypass mechanism of the currents was proposed to explain the differences between the two models. The study found that cracking in the solder layer under thermal cycling can be described by a combination of continuous and random models, which can represent the upper and lower levels of the series resistance increase. When the solar cell power dropped to 80%, the increase in series resistance was expected to be in the range of 200 to 250% using the continuous and random models, respectively.

1. Introduction

The construction of Si solar modules typically starts with a layer of low-iron tempered glass, followed by an ethylene-vinyl acetate (EVA) layer that acts as an adhesive and encapsulant. The Si wafer, which is responsible for generating electric currents from sunlight, is located beneath the EVA layer, and another layer of EVA is applied on top of it. Finally, there is a back sheet layer that provides structural support and protection. To transfer the electric currents generated in the Si wafer to other wafers, the module is equipped with several attached Cu ribbon wires. These ribbon wires are connected to the Si wafer using solder layers, which are coated onto the ribbon wires. The solder layers provide both electrical and mechanical connections between the ribbon wires and the Si wafer, ensuring reliable and efficient energy transfer.

The temperature difference between day and night or between summer and winter causes thermal cycling (TC) stress in outdoor solar modules. TC is known to be a detrimental stress that induces degradation of power conversion efficiency [1]. TC causes cracking of the solder layer due to the difference in the coefficient of thermal expansion between the materials. These cracks, in turn, increase the series resistance (${\mathrm{R}}_{\mathrm{s}}$) in the solar cell, leading to a reduction in power output. Many studies have identified this power degradation mechanism as a result of TC in solar cells [2,3,4,5,6]. As the power drop under TC is a function of an increase in ${\mathrm{R}}_{\mathrm{s}}$ in solar cells, it is important to know the quantitative relationship between the amounts of solder layer cracking and the increase in ${\mathrm{R}}_{\mathrm{s}}$, and the maximum ${\mathrm{R}}_{\mathrm{s}}$ increase allowed in a cell.

These concerns can be investigated numerically. Any numerical approach capable of Poisson’s equation and continuity equation for electrons and holes can simulate the solar cell’s electric behavior [7]. Analyses based on the finite element method (FEM) have been conducted in many studies. Malm and Edoff [8] studied the effects of bandgap energy and trap density of thin-film solar cells on the open-circuit voltage using a commercial FE package in a 2D model. To simulate the efficiency of the composition grading of thin-film solar cells, Brown et al. [9] solved the Poisson and continuity equations using a commercial FEM package. Shiradkar et al. [10] evaluated the leakage current under high potential in solar modules using a 2D FE model. Recently, using a designated solar cell simulator based on the 2D FEM, Asadpour et al. [11,12] studied the effect of solder bond failure in Si solar cells on current–voltage (I–V) curves. As processing both the Poisson and continuity equations simultaneously requires large amounts of computing resources, most studies have been limited to 1D or 2D FEMs for a partial area of a solar cell.

However, the current in solar cells flows through a 3D structure consisting of front ribbon wire, front electrode, wafer, rear electrode, and rear ribbon wire. Quantitative studies on the effect of solder layer cracking on ${\mathrm{R}}_{\mathrm{s}}$ increase in a cell require 3D full modeling of solar cells for numerical simulation. In this study, the continuity equation was separated from the Poisson’s equation by modeling the absorber layer of a Si solar cell in an equivalent resistance, and an electrostatic model for the entire solar cell in 3D FEM was constructed for the analysis of ${\mathrm{R}}_{\mathrm{s}}$ in Section 2. Next, cracking in the solder layer of the ribbon wire in a solar cell was reflected in the model, and the electric potential and current were analyzed to estimate the ${\mathrm{R}}_{\mathrm{s}}$ increase in the solar cell in Section 3. Extensive quantitative studies have been conducted on the effects of solder cracking associated with variations in the amount, position, front and rear, and pattern of cracking. The analysis results revealed a relationship between solder cracking and an increase in ${\mathrm{R}}_{\mathrm{s}}$. The flow of simulation conducted in this study is summarized in Figure 1 for clarity.

2. Simulation of Series Resistance in Solar Cells

In the equivalent circuit of the solar cell shown in Figure 2a, the current flow is expressed as:

$$\mathrm{I}={\mathrm{I}}_{\mathrm{ph}}-{\mathrm{I}}_{\mathrm{d}}-{\mathrm{I}}_{\mathrm{sh}}={\mathrm{I}}_{\mathrm{ph}}-{\mathrm{I}}_0\left[\exp \left(\frac{{\mathrm{V}}_{\mathrm{t}}+{\mathrm{R}}_{\mathrm{s}}\mathrm{I}}{{\mathrm{aV}}_{\mathrm{T}}}\right)-1\right]-\frac{{\mathrm{V}}_{\mathrm{t}}+{\mathrm{R}}_{\mathrm{s}}\mathrm{I}}{{\mathrm{R}}_{\mathrm{sh}}}$$

(1)

In the equation, ${\mathrm{R}}_{\mathrm{s}}$ is caused by the resistance through the emitter and base of the solar cell, contact resistance between the metal contact and silicon, and resistance of the top and rear metals. The circuit can be defined by the voltages before and after ${\mathrm{R}}_{\mathrm{s}}$ as:

$${\mathrm{R}}_{\mathrm{s}}=\frac{{\mathrm{V}}_{\mathrm{s}}-{\mathrm{V}}_{\mathrm{t}}}{\mathrm{I}}$$

(2)

where ${\mathrm{V}}_{\mathrm{s}}$ is as defined in Figure 2. To measure ${\mathrm{R}}_{\mathrm{s}}$, we need to monitor ${\mathrm{V}}_{\mathrm{s}}$. It can be interpreted that we need to measure the I–V curve of a solar cell without the ${\mathrm{R}}_{\mathrm{s},}$ as shown in Figure 2b, which is practically impossible.

However, this is possible in the simulations. If we model the solar cell by counting all the ${\mathrm{R}}_{\mathrm{s}}$ components and separating them from the current of photogeneration (${\mathrm{I}}_{\mathrm{ph}}$), diode effect (${\mathrm{I}}_{\mathrm{d}}$), and shunt resistance effect (${\mathrm{I}}_{\mathrm{sh}}$), as shown in Figure 2c, the ${\mathrm{R}}_{\mathrm{s}}$ can be estimated in an electrostatic problem.

2.1. Electrostatic Modeling Theory in FEM

In electrostatic problems, the Maxwell equations for materials are decoupled into electric and magnetic field pairs of equations. For electric field intensity $E$, the Maxwell equations become:

$$\nabla ·\mathsf{\epsilon }E=\mathsf{\rho }$$

(3)

$$\nabla \times E=0$$

(4)

where $\mathsf{\rho }$ is the electric charge density and $\mathsf{\epsilon }$ is the permittivity of the material [13]. Using the relation between the electric field intensity and potential, $E=-\nabla \mathrm{V}$, Equation (3) is transformed into the Poisson’s equation as follows:

$$\nabla ·\mathsf{\epsilon }\nabla \mathrm{V}=-\mathsf{\rho }.$$

(5)

It becomes the Laplace’s equation for a free net charge situation, $\mathsf{\rho }=0$,

$$\nabla ·\mathsf{\epsilon }\nabla \mathrm{V}=0.$$

(6)

For solar modules, a free net charge situation can be assumed except in the depletion region [14].

The solution to Equation (6) can be obtained through the FE analysis. In the FEM, the electric potential becomes:

$$\mathrm{V}={\left\{\mathrm{N}\right\}}^{\mathrm{T}}\left\{{\mathrm{V}}_{\mathrm{e}}\right\}$$

(7)

where $\left\{\mathrm{N}\right\}$ is the element shape function vector and $\left\{{\mathrm{V}}_{\mathrm{e}}\right\}$ is the nodal electric scalar potential vector. After applying the variational principle, the matrix equation for an electrostatic problem using a current-based electric element, such as SOLID231 in the commercial FE package ANSYS, ref. [15] becomes

$$\left[\mathrm{K}\right]\left\{{\mathrm{V}}_{\mathrm{e}}\right\}=\left\{{\mathrm{I}}_{\mathrm{e}}\right\}$$

(8)

and

$$\left[\mathrm{K}\right]={{\displaystyle \int }}_{\mathrm{vol}}^{}{\left(\nabla {\left\{\mathrm{N}\right\}}^{\mathrm{T}}\right)}^{\mathrm{T}}\left[\mathsf{\sigma }\right]{\left(\nabla {\left\{\mathrm{N}\right\}}^{\mathrm{T}}\right)}^{\mathrm{T}}\mathrm{d}\left(\mathrm{vol}\right)$$

(9)

where vol is the element volume, $\left[\mathsf{\sigma }\right]$ is the conductivity matrix, and $\left\{{\mathrm{I}}_{\mathrm{e}}\right\}$ is the nodal current vector.

2.2. Electrostatic Material Properties of Solar Cells

The constructed 3D FE model of the solar cell used for electrostatic analysis is shown in Figure 3. The model consists of a Si wafer, front Ag electrodes, back Al electrodes, Cu ribbon wires, and solder layers. It represents a real size of the solar cell of 155 × 158 mm² with the thickness of 0.17 mm. It is composed of five bus bars of width 1 mm and 106 lines of front metal electrodes with a width of 0.1 mm. The spans of the bus bars and electrode are 30 mm and 1.4 mm, respectively. The element Solid231 was used in the ANSYS software. Through a convergence check, the number of nodes in the model was determined to be 7,904,195. Five ribbon wires (RW), consisting of a Cu layer and solder layer, are located at the busbar positions. They are denoted as RW1 to RW5 from left to right, as shown in Figure 3.

The required material property for the electrostatic analysis of Equation (6) is the conductivity or its inverse, resistivity. The adopted resistivities in the analysis are summarized in

Table 1. Selected resistivity of the materials in the model for electrostatic analysis.

Materials		Resistivities	References
Solder (Pb40Sn60)		1.50 × 10−4 Ω-mm	[16]
Copper		1.68 × 10−5 Ω-mm	[17]
Silver		1.59 × 10−5 Ω-mm	[18]
Aluminum		2.65 × 10−5 Ω-mm	[18]
Si wafer	$\mathrm{Bulk}\mathrm{resistivity}({\mathsf{\rho }}_{\mathrm{b}})$	30 Ω-mm	[19]
	$\mathrm{Emitter}\mathrm{sheet}\mathrm{resistance}({\mathrm{R}}_{\mathrm{E}\mathrm{S}})$	55 Ω/sq.	[20,21]
	$\mathrm{Contact}\mathrm{resistance}({\mathsf{\rho }}_{\mathrm{c}})$	0.3 Ω-mm2	[20,21]

for the solder, copper, silver, aluminum, and Si wafer. For Si wafers, there are three components of resistivity: bulk resistivity, emitter sheet resistance, and contact resistance.

The resistance of the Si wafer is defined at four points, as shown in Figure 4, where ${\mathrm{w}}_{\mathrm{f}}$, ${\mathrm{s}}_{\mathrm{f}}$, and ${\mathrm{t}}_{\mathrm{w}}$ are the finger grid width, span, and wafer thickness, respectively. In this study, typical dimensions of solar cells with ${\mathrm{w}}_{\mathrm{f}}=$ 0.1, ${\mathrm{s}}_{\mathrm{f}}=$ 1.4, and ${\mathrm{t}}_{\mathrm{w}}=$ 0.17 mm were employed. The lower contact resistance between the wafer and back contact, ${\mathrm{R}}_1$, is generally negligible [22]. The substrate resistance ${\mathrm{R}}_2$ is determined using the bulk resistivity [20]. Emitter resistance ${\mathrm{R}}_3$ is one of the main contributors and is determined using the emitter sheet resistance. The upper contact resistance between the wafer and finger ${\mathrm{R}}_4$ is determined using the contact resistance. For the dashed square area by ${\mathrm{w}}_{\mathrm{f}}+{\mathrm{s}}_{\mathrm{f}}$ and wafer thickness ${\mathrm{t}}_{\mathrm{w}}$ shown in Figure 4, the calculations are as follows:

$${\mathrm{R}}_2={\mathsf{\rho }}_{\mathrm{b}}\times 2{\mathrm{t}}_{\mathrm{w}}/{\left({\mathrm{w}}_{\mathrm{f}}+{\mathrm{s}}_{\mathrm{f}}\right)}^2=4.5 \mathsf{\Omega },$$

(10)

$${\mathrm{R}}_3={\mathrm{R}}_{\mathrm{ES}}\times \left({\mathrm{s}}_{\mathrm{f}}/2\right)/\left({\mathrm{w}}_{\mathrm{f}}+{\mathrm{s}}_{\mathrm{f}}\right)=25.7 \mathsf{\Omega },$$

(11)

$${\mathrm{R}}_4={\mathsf{\rho }}_{\mathrm{c}}/\left({\mathrm{w}}_{\mathrm{f}}\times \left({\mathrm{w}}_{\mathrm{f}}+{\mathrm{s}}_{\mathrm{f}}\right)\right)=2.0 \mathsf{\Omega }.$$

(12)

The total resistance in the longest pass of current is ${\mathrm{R}}_2+{\mathrm{R}}_3+{\mathrm{R}}_4=$ 32.2 Ω, and in the shortest pass is ${\mathrm{R}}_2+{\mathrm{R}}_4=$ 6.5 Ω. In the passes, the equivalent resistivity can be determined as:

$${\mathsf{\rho }}_{\mathrm{eq}}=\left({\mathrm{R}}_2+{\mathrm{R}}_3+{\mathrm{R}}_4\right)\times {\left({\mathrm{w}}_{\mathrm{f}}+{\mathrm{s}}_{\mathrm{f}}\right)}^2/2{\mathrm{t}}_{\mathrm{w}} =213 \mathsf{\Omega }\text{-}\mathrm{mm}.$$

(13)

$${\mathsf{\rho }}_{\mathrm{eq}}=\left({\mathrm{R}}_2+{\mathrm{R}}_4\right)\times \left({\mathrm{w}}_{\mathrm{f}}+{\mathrm{s}}_{\mathrm{f}}\right){\mathrm{w}}_{\mathrm{f}}/{\mathrm{t}}_{\mathrm{w}} =43 \mathsf{\Omega }\text{-}\mathrm{mm}.$$

(14)

The average of them is 128 Ω-mm, which is the value of Si wafer equivalent resistivity in this study. Note that this is an overestimation, because the current tends to find the smallest resistance path.

The applied boundary conditions on the model were the electric potentials at the end of the RWs, as shown in Figure 5, where the normalized electric potentials, or ‘0′ and ‘1′ voltages, were applied.

2.3. Series Resistance Calculation

The electric potential plots of the cells obtained from the analysis are shown in Figure 6. The potential on the busbar of the front side was maintained as ‘1’, as shown in the details of Figure 6a. It drops sharply to ‘0′ at the front and rear sides of the cell.

To calculate the ${\mathrm{R}}_{\mathrm{s}}$ of the cell, the electric flow should also be considered. The electric current densities in the x- and y-directions are shown in Figure 7. In the x-direction, the current flow at the electrodes is dominant, as shown in Figure 7a. In the y-direction, the flow in the busbars prevails, as shown in Figure 7b. Interpreting the plots reveals the current flow in the cell as represented in Figure 7c. The current started to flow from the top of the five front busbars, divided into the front electrodes, and was distributed into the cell. At the rear side of the cell, the reverse motion of the current flow is expected; cell, electrode, and busbars. The amount of current flowing across the solar cell can be calculated by summing up the amount of the current at the ends of five busbars. When ‘1′ voltage was applied, the total amount of current was 179.4 A. The calculated ${\mathrm{R}}_{\mathrm{s}}$ of the cell was 1/179.4, or 0.0056 Ω.

It is known that typical values for area-normalized ${\mathrm{R}}_{\mathrm{s}}$ of Si solar cells are between 0.5 Ω-cm² for laboratory-type solar cells and up to 1.3 Ω-cm² for commercial solar cells [23]. In this study, they were found to be between 0.002 Ω and 0.005 Ω. Considering the overestimation of Si wafer equivalent resistivity, it can be said that the value of 0.0056 Ω from the analysis is in the correct estimation range.

3. Simulation of Series Resistance Increase through Solder Layer Cracking

As shown in Figure 8, the cracks generated in the solder layer under TC stresses were modeled by removing the corresponding elements at the FE model previously configured. Many cases are possible with variations in the locations, sides, and amount of cracking. The simulated cases are summarized in

Table 2. Definition of simulation cases.

Notation	Description *
Case 0	No cracking
Case F	Cracking in the RWs at front side:
	Case F-1	continuously from bottom to top at RW1.
	Case F-3	continuously from bottom to top at RW3.
	Case F-123	continuously from bottom to top at RWs 1, 2, and 3.
	Case F-12345	continuously from bottom to top at RWs 1, 2, 3, 4, and 5.
Case R	Cracking in the RWs at rear side:
	Case R-1	continuously from bottom to top at RW1.
	Case R-3	continuously from bottom to top at RW3.
	Case R-123	continuously from bottom to top at RWs 1, 2, and 3.
	Case R-12345	continuously from bottom to top at RWs 1, 2, 3, 4, and 5.
Case FR	Crack in the RWs at both front and rear sides:
	Case FR-12345	continuously from bottom to top at RWs 1, 2, 3, 4, and 5.
	Case FR-rand	in random at RWs 1, 2, 3, 4, and 5.

* RW numbered 1–5 from left to right.

. In the table, Case 0 corresponds to cases without cracking. Cases F, R, and FR stand for the cases with cracking at the front, rear, and both sides RWs of solar cells, respectively. The second index in Table 1, or -1, -3, -123, -12345, and -rand, represent the cracking positions at RW1, RW3, RW1 to RW3, RW1 to RW5, and random, respectively. A total of 10 cracking cases were simulated. For all the cases, except for the random case (Case FR-rand), it was assumed that a crack in the solder layer was initiated at the bottom of the ribbon wire, where the strain energy density reached a maximum [24] and propagated continuously.

3.1. Cases with Continuous Cracks

When cracks were present in the solder layer, it was simulated that the electric potentials were broken by the cracks, and the currents stopped flowing in the areas, as shown in Figure 9. The results of the current stops for Case F-3 are depicted in Figure 10, which compares the change in the current output at the RWs when cracks propagate from 0 to 75% at RW3. The figure shows that the current at RW3 decreased as the crack propagated at RW3. Furthermore, it can be said that part of the lost current was compensated at the other RWs by the potential bypass of the current; however, it was not fully filled up and caused an increase in ${\mathrm{R}}_{\mathrm{s}}$.

Figure 11 shows the simulation results of the current drop and ${\mathrm{R}}_{\mathrm{s}}$ increase over the crack ratio for Cases F-1 and F-3. When the cracks continuously propagated to 100% in the RWs, ${\mathrm{R}}_{\mathrm{s}}$ increased up to 7.5% and 15% for Cases F-1 and F-3, respectively. The difference between the cases can be explained by the possibility of current bypassing at the cracked RWs. If there is a crack in RW1, the currents can only be bypassed in the right direction because there is no RW on the left. However, if a crack occurs in RW3, the current can bypass in both directions.

When multiple RWs start to crack continuously at once, more current drops and ${\mathrm{R}}_{\mathrm{s}}$ increases are expected, as shown in Figure 12. In Case F-12345, or when all the RWs at the front side crack from bottom to top, it was expected that the current drops from 0 to 100%, linearly and ${\mathrm{R}}_{\mathrm{s}}$ increases exponentially to infinity. However, it was less than 250% until all the RWs cracked to 75%. In Case F-123, the maximum ${\mathrm{R}}_{\mathrm{s}}$ increase was only up to 100%.

If cracks occurred in the RWs at the rear side, it was observed that the current dropped less and consequently ${\mathrm{R}}_{\mathrm{s}}$ increased less compared to the case of cracking at the front side, as shown in Figure 13. As the rear electrode covered the entire cell area, unlike the front electrode, it was easier to secure an alternative pass of current during cracking. It was expected that ${\mathrm{R}}_{\mathrm{s}}$ would increase by only 70% even if all the RWs were almost cracked.

Figure 14 compares the results of Cases F, R, and FR when all the RWs cracked continuously from bottom to top. As expected from Figure 12 and Figure 13, smaller drops and increases were estimated in Case R than in Case F. Notably, the effect of rear-side cracking is insignificant when all the front and rear sides are assumed to have cracks. Case FR produced a similar amount at the curves as Case F.

3.2. Case with Random Cracks

All the cases thus far have assumed that solder cracking starts at the bottom and propagates continuously to the top, based on an analysis of the maximum strain energy density position. However, cracks in the solder layer can be initiated at other positions or randomly. Case FR-rand simulates the random generation of cracks on both sides of the RWs. The results are presented in Figure 15. In the random case, the current dropped slowly, and the amount of ${\mathrm{R}}_{\mathrm{s}}$ increase reduced compared with that in Case FR-12345. ${\mathrm{R}}_{\mathrm{s}}$ was expected to increase to 45% and 200% when the solder layers were randomly cracked above 50% and 80%, respectively. In the case of continuous cracking, ${\mathrm{R}}_{\mathrm{s}}$ increased to 83% and 330% when the crack ratios were 50% and 80%, respectively.

A simple mathematical model can explain the difference between Cases FR-12345 and FR-rand. First, a crack function is defined, which indicates the status of cracking at solder layer positions m and k as follows:

$$\mathrm{Crack}\left(\mathrm{m},\mathrm{k}\right)=\{\begin{array}{c}0,\mathrm{cracked}\\ \\ 1,\mathrm{no}\mathrm{crack}\end{array},$$

(15)

where $\mathrm{m}$ is the number of ribbon wires (1–5 in this study) and $\mathrm{k}$ is the number of electrodes (1–106 in this study). In Case FR-12345, Equation (15) is zero from the bottom to the value defined by the crack ratio. In Case FR-rand, it will be zero at random, and the number of zeros will be determined by the crack ratio.

Next, considering the bypassing mechanism of the current during cracking, the current density at the electrode can be modeled as:

$$\mathrm{CurrentDensity}\left(\mathrm{n},\mathrm{k}\right)=\{\begin{array}{c}\mathrm{Crack}\left(1\mathrm{or}6,\mathrm{k}\right),\mathrm{if}\mathrm{n}=1\mathrm{or}6\\ \\ \mathrm{Crack}\left(\mathrm{n}-1,\mathrm{k}\right)\cup \mathrm{Crack}\left(\mathrm{n},\mathrm{k}\right),\mathrm{if}\mathrm{n}=2\mathrm{to}5\end{array},$$

(16)

where $\cup$ indicates the Boolean operation OR, in other words, $\mathrm{CurrentDensity}\left(\mathrm{n},\mathrm{k}\right)=1-\left(1-\mathrm{Crack}\left(\mathrm{n}-1,\mathrm{k}\right)\right)\times \left(1-\mathrm{Crack}\left(\mathrm{n},\mathrm{k}\right)\right)$. The $\mathrm{CurrentDensity}$ function will be 0 or 1 depending on the status of $\mathrm{Crack}$ function and position. The values $\mathrm{n}$, $\mathrm{m}$, and $\mathrm{k}$ used in this study are defined in Figure 16.

Graphical representations of $\mathrm{Crack}\left(\mathrm{n},\mathrm{k}\right)$ are shown in Figure 17a in red (cracked) and white (no crack) for Cases FR-12345 and FR-rand at 50% crack ratio for the solar cell configuration shown in Figure 16. The number ratios of red blocks in the figure for both cases are exactly 50%. The results of the $\mathrm{CurrentDensity}\left(\mathrm{n},\mathrm{k}\right)$calculation are represented in Figure 17b in green (1) and white (0) for both cases. The number ratios of green blocks in the figure are 50% and 70% for Cases FR-12345 and FR-rand, respectively.

By summing the current function results, the current drop can be estimated over the crack ratio, as shown in Figure 18. It shows a linear current drop in Case FR-12345, as simulated in Figure 15a. Also, Case FR-rand generated a nonlinear curve pattern similar to the simulation results shown in Figure 15a. The results indicate that Equation (16) represents the mechanism of current drop in solar cells.

The current density simulation results on the Si wafer in Cases FR-12345 and FR-rand when the cracks propagate to 50% of RWs are shown in Figure 19, which shows a pattern similar to the one in Figure 17b. The random pattern shown in Figure 19b is reminiscent of the electroluminescence (EL) images of a Si solar cell after TC, which can be easily found in previous studies [25,26,27]. An example EL image after 1000 TC is shown in Figure 20 for a 72-cell mono-crystalline solar cell module. The condition of TC to the module was from IEC 61215 [28]; 85 °C to –40 °C in 4 h with 30 min dwell time each. The EL images show a random pattern of rectangular dark areas (RDA) in EL images after TC. The intensity of the EL images is proportional to the minority carrier diffusion length in the Si solar cells [29]. Cracks in the solder layer reduce the minority carrier diffusion length and they can be spatially detected as RDAs during light emission.

From these observations, it can be stated that the cracks tend to be initiated randomly. However, cracks initiated randomly propagate continuously through the mechanism of fracture mechanics. Therefore, cracking in the solder layer under TC can be explained by a combination of continuous and random models. The extreme cases, or Cases FR-12345 and FR-rand, represent the upper and lower levels of increase in ${\mathrm{R}}_{\mathrm{s}}$, respectively.

3.3. Power Drop Analysis

To estimate the practical amount of ${\mathrm{R}}_{\mathrm{s}}$ increase in solar cells, the power drops owing to the ${\mathrm{R}}_{\mathrm{s}}$ increase were studied. The one-diode equivalent-circuit model in Equation (1) for a one-cell module with ${\mathrm{I}}_{\mathrm{o}}$ = 1.5 × 10⁻⁸ A, ${\mathrm{R}}_{\mathrm{sh}}=$ 25 $\mathsf{\Omega }$, ${\mathrm{I}}_{\mathrm{ph}}=$ 9 A, and a = 1.25 was constructed using a SPICE simulation software application [30]. The increased ${\mathrm{R}}_{\mathrm{s}}$ values for the calculation were extracted from Figure 15b.

The calculated I–V curves with several crack ratios for Cases FR-12345 and FR-rand are shown in Figure 21a,b, respectively. From the curves, the maximum powers were calculated, and they are plotted in Figure 21c with respect to the crack ratios for both the cases. It was found that the power is maintained at 71 to 82% when the solar cell had 80% cracked RWs and it drops rapidly after that.

The lifetime of a solar module can be defined as a power drop over 80%, which is a typical choice for many manufacturers’ power warranty time [24]. When the solar cell power decreased to 80%, the ${\mathrm{R}}_{\mathrm{s}}$ increases are analyzed to be in the range of 200 to 250% for the continuous and random models, respectively.

4. Conclusions

Quantitative analysis was conducted using a 3D FE model to study the effect of solder layer cracking on the ${\mathrm{R}}_{\mathrm{s}}$ increase in Si solar cells. The model consisted of a Si wafer, front Ag electrodes, back Al electrodes, Cu ribbon wires, and solder layers in a real solar cell with an equivalent resistivity to the absorber layer of the Si wafer. For the ${\mathrm{R}}_{\mathrm{s}}$ calculation, an electric potential was applied at the end of the busbars, and the amount of current flowing across the solar cell was calculated by summing the current at the end of the busbars.

Two types of cracking models were considered: continuous and random. In the continuous crack model, or when all the RWs on the front side were cracking from bottom to top, it was expected that the current would drop from 0 to 100%, linearly and ${\mathrm{R}}_{\mathrm{s}}$ would increase exponentially to infinity. However, it was less than 250% until all the RWs were cracked to 75%. Less drops and increases were estimated when cracks were present on the rear side of the RWs. In the random crack model, the current dropped slowly, and the value of ${\mathrm{R}}_{\mathrm{s}}$ increase reduced compared to the continuous crack model. A simple mathematical model based on the bypass mechanism of the currents was suggested to explain the differences between the models. It was found that cracking in the solder layer under TC is a combination of continuous and random models, and the two models can represent the upper and lower levels of the ${\mathrm{R}}_{\mathrm{s}}$ increase. When the solar cell power dropped to 80%, ${\mathrm{R}}_{\mathrm{s}}$ increase was analyzed to be in the range of 200 to 250% using the continuous and random models, respectively.