Analytical Prediction of the Thermal Behavior of Semiconductor Power Devices from Room-Temperature I–V Measurements ^†

Abstract

The thermal characterization of power devices is an inevitable task in the industry. Thermal transient testing is one of the major tools for this characterization, as it is not only capable of giving information about the actual thermal parameters but may also reveal the root cause of potential device failures. The testing may occur on single packages or modules on a dedicated standard test bench, or “in situ”, in an actual assembly. The testing process itself is very fast in both cases, on the order of seconds, but the transient measurement needs to be preceded by a calibration step to determine the temperature dependence of a temperature-sensitive parameter (TSP) of the semiconductor device. This may require a long time, as the device has to be measured at many stabilized temperatures, which in the case of power devices may take hours. It also has to be considered that, especially in “in situ” measurements, reaching the highest device temperatures of power devices may even damage other parts of the surrounding electronics. Moreover, the temperature distribution inside a module will be different at calibration time than during operation with the same junction temperature, as bond wires and copper traces do not reach the chip temperature in the latter case. This paper presents a methodology that can be used to replace the lengthy measurement of one parameter at many temperatures with a fast single I–V characteristics measurement at room temperature. Physics-based calculations assign a unique temperature-sensitive parameter to each item of interest in the system. After the presentation of the theoretical background, the usability of the method is demonstrated by verifying measurements on silicon power devices.

1. Introduction

Semiconductor devices are the key elements in power electronics in many fields, ranging from vehicle traction to solar power generation and consumer electronics. An indispensable part of the design and also of the testing of power electronics equipment targets predicting the operation of these elements in a wide current and temperature range.

Measurements of the I–V characteristic of the semiconductor parts at various temperatures and storing the current and voltage pairs of many operating points provide a valid amount of data for this prediction. However, decades of research have provided electric and thermal models for the devices, which yield accurate predictions of the device characteristics in a much denser form by analytical equations governed by a few fundamental parameters. A historical overview of the development of device modeling methodologies from the original Shockley equation to artificial-intelligence-based black-box models can be found in [1].

Although the traditional physics-driven compact models are still in the mainstream nowadays, due to the complexity of the devices and the availability of automated extraction methods, AI-assisted compact model extraction from measured and/or TCAD-simulated data is gaining popularity [1]. The fundamentals of physics-based compact electrical modeling for classic devices are summarized for example in [2], and extensions for modeling wide-bandgap power devices can be found in [3,4]. The lumped charge modeling approach solves simplified fundamental semiconductor device equations; it promises more accurate results than the classical compact modeling approach in a faster manner than solving the device equations directly using numerical methods [5,6].

Our recent research focused on how the extended use of relatively simple models can simplify and speed up the work in the testing field [7]. It is not the scope of this work to develop a complete electrothermal simulation model, since we do not need to model the electrical characteristic itself, as it can be measured in situ in one or multiple operating points. Rather, we try to model the temperature dependence of the characteristics in a well-defined temperature and current range, e.g., to predict the electrical characteristics at arbitrary temperatures from a room-temperature measurement or to calculate the device’s temperature from an electrical measurement.

It should be noted that when a simulation model of the device is to be built, it reflects an average (or sometimes a corner case) device. With the novel concept, only the temperature-related behavior is modeled, and the electrical characteristics are measured individually on each item; therefore, one can reach a higher accuracy than an electrothermal compact model for the average device.

For decades, testing concepts have been more and more extended to the thermal analysis of larger electronic appliances. Especially, thermal transient testing has become a major methodology for the characterization of the heat transfer properties of semiconductor packages or assemblies or reliability tests by active power cycling. The development of the thermal transient measurement concept can be followed in the related standards [8,9,10,11,12,13,14,15], and an extensive review of its usage with additional references can be found in [16], Chapter 7.

Thermal transient testing is accomplished frequently on a single package or module, in a dedicated test environment, as defined in the above thermal testing standards. As semiconductor devices and thermal interface materials may behave very differently in an actual appliance with different heat-conducting paths compared with the standard arrangement, more and more tests are carried out “in situ” with a number of active devices mounted in a larger assembly.

All thermal tests are based on the measurement of a specific electric quantity of a functioning semiconductor device, referred to as the temperature-sensitive parameter (TSP).

Each thermal transient test comprises two subsequent processes. The first one is a calibration phase, when the TSP is mapped to device temperature in a temperature-controlled environment. This is followed by a measurement phase when the change in the TSP is measured at changing power levels and applied to the system [16].

For gaining the most information on the structural details of the device under test (DUT), thermal transient measurements are to be carried out completely, from steady state to steady state. The length of the transient test depends on the thermal mass of the DUT and the effectiveness of the cooling.

A packaged transistor has a mass of grams, and a module may be a few hundred grams. The temperature sweep of the DUT itself concludes in a minute, or even in a shorter time. In the case of using a liquid-cooled cold plate and a dozen liters of the coolant circulating in it, the cold plate can be considered to have infinite heat-sinking capability for the time of the transient test.

As such, the full cooling transient between a “hot” steady state at high applied power and a “cold” steady state at low applied power completes in a minute with a device mounted on a cold plate, but the calibration process may take hours. Thermal measurement standards generally prescribe five or more temperature points for calibration. To reach the temperature stabilization at each point of the whole mass of the cold plate, the liters of coolant and the internal heating/cooling aggregate have to reach the set temperature, and each setting may take several minutes. Consequently, shortening or eliminating the calibration process is a key issue in speeding up the thermal transient characterization of a device.

Moreover, we cannot generally expect that in a complex appliance, all semiconductor parts have passed thermal calibration in advance. While proper access can be provided to main power devices for electric measurement, keeping the whole appliance at several temperature points in a wide range is not feasible. Also, while the semiconductor chip easily withstands temperatures well over 100 °C, the packaging material and other structural components in the appliance may have a much lower temperature limit, preventing the calibration at higher temperatures in the range of interest.

Furthermore, the established TSP may be slightly distorted as the temperature distribution inside a module will be different at calibration time than during operation with the same junction temperature, as bond wires and copper traces do not reach the chip temperature.

In many device categories, the usual TSP selection for the thermal transient test is a temperature-dependent voltage value at an applied constant current. For this reason, in this work, we attempt to achieve reduced time effort and easier feasibility by replacing the lengthy TSP calibration process with I–V characteristics measurement at a single temperature, practically at room temperature. Physics-based considerations from this single measured data set then yield analytic equations, which can serve as an electrothermal model of the device, predicting its behavior in a wide current and temperature range.

Note that the predicted value always differs from the true physical value by an error. Different accuracy levels can be stated for a model as follows:

(a)

If the error remains below a few °C in the temperature range of interest, the predicted temperature value from the model can be used for lifetime estimation in a reliability test (10 °C difference can result in four times shorter lifetime).

(b)

If the error is in the range of about 10 °C, the predicted temperature can be used for structure identification and failure analysis in a thermal transient test, or by adding an appropriate safety margin, it can be used as an overheating alarm or system stop criterion in a real operating appliance.

(c)

If a model can be set up in which the error systematically diminishes when adjusting a single model parameter, then further physical estimations based on other measurements (e.g., breakdown voltage) or estimations from datasheet values can reduce the error to reach the accuracy of case (a).

2. Physical Background

Realistic semiconductor devices are mostly handled as a compound of regions with different expected behavior. In the classical treatment, these regions are several pn junctions in forward or reverse operation, coupled with charge transfer from one to another. The junctions are adjoined with quasi-neutral semiconductor regions of mostly ohmic behavior, and “external” regions are added, attributed to metallization, package pins, etc. All these regions obey physical laws, which can be described by analytic equations, shaped by material parameters like the lifetime of charged particles or the concentration of dopant atoms.

The temperature-sensitive quantity, TSP, is often a V_F voltage across a pn or Schottky junction in a diode, transistor, or a more complex structure at an applied constant I_F forward current. The laws of physics imply that the current in the semiconductor depends on many constraints, such as, e.g., the lattice constant of the crystal, the concentration of dopant atoms and the gradient of this concentration, the presence of moving charge carriers, the electric field, and, most importantly, the temperature.

Looking at an actual device characteristic already gives some clue as to which analytic expressions gained from physics can be relevant.

Figure 1 presents the temperature-dependent I–V characteristics of a semiconductor diode. The curves correspond to the measured V_F forward voltage at forced I_F forward current in a wide current and temperature range.

For illustration purposes, the I–V characteristics of a silicon carbide device are presented (SCT3160KLHR medium power MOSFET, ROHM Semiconductor). The inherent bulk diode was measured in the current and temperature range shown (0.1 μA to 1 A and 10 °C to 90 °C, respectively) at −6 V gate bias.

In the chart, three specific regions, denoted as Low, Medium, and High, respectively, can be seen. In silicon devices, the same regions can be identified but with wider overlapping transition sections from one region to the other, and the regions cover a wider current range.

It is obvious from the chart that when applying a high current to the device, it heats up, the V_F(I_F,T) forward voltage shifts to a high-current/high-temperature point, determined by V_F·I_F power and the cooling capability of the thermal environment. Then, after stabilization, switching abruptly to a lower constant I_M measurement current, the operation point moves in time to a low-temperature point along the selected vertical line corresponding to I_M. Details of the heating and cooling setup and techniques of the thermal transient measurement are broadly treated in the literature, among others, in [13], Chapters 5 and 6 of [16], and in [17].

Figure 2 presents the recorded transient voltage change on the bulk diode of the above SCT3160KLHR device, mounted on a cold plate. After switching from a 10 A forward current to a constant 100 mA, the cooling-related change of the forward voltage can be observed. A proper, not necessarily linear TSP mapping between the V_F forward voltage and T_J junction temperature can convert the recorded voltage change to a temperature transient.

The electric switching transient covers the temperature-related change in the signal until approximately 40 μs. Still, by analyzing the transient between 40 μs and one minute, the temperature and quality of the die attached within the package and the thermal interface and the cold plate can be determined. Temperature measurement standards such as [9,12,13] prescribe a square-root time backward extrapolation for this region (red line in the figure).

In a similar in situ measurement, in a real appliance instead of a cold plate arrangement, structure-function-based structure analysis [16] can check the quality and health of, e.g., soldering and glue layers in the near thermal environment.

Now, to find a valid mapping between the temperature-dependent V_F forward voltage and the T_J junction temperature, Figure 1 has to be examined again. In all three regions, before or after a transition section, characteristic straight-line sections appear. As the chart is a log-line type, straight lines correspond to exponential dependence.

Semiconductor physics has an adequate explanation for some of these straight sections when the internal pn junction is considered. The corresponding equations are less plausible for other sections, and the literature often concludes with awkward explanations for the intermediate intervals [17,18].

Concentrating on the straight sections, the V_F = A·ln(I_F) + B expression can be easily mapped to the Shockley equation:

$$I_F=I_S·\left(e^{\frac{V_F}{m{V}_T}}-1\right)$$

(1)

In the forward direction, the last term can be neglected, and the equation can be rearranged for a forced I_F forward current as follows:

$$V_F\approx m{V}_T\ln \frac{I_F}{I_S}.$$

(2)

Note that an equation like (1) is a simplified model of the fundamental drift/diffusion processes in a pn junction. The intention of the formula is clear: it attempts to separate the description of a voltage-dependent behavior from other factors influenced only by the material properties in a semiconductor domain.

The pn junction current model in (1) is the product of two quantities. The exponential part is strongly dependent on voltage and temperature, with no tie to the actual device type except the enigmatic m “ideality factor”. The temperature dependence appears through the thermal voltage, V_T = k·T/q, where k is the Boltzmann constant, T is the absolute temperature at the junction, and q is the electron charge. (The ideality factor is sometimes notated as n, but in this context, we reserve n for the density of electrons.)

The other component in Equations (1) and (2) is the I_S “saturation current”, which is temperature-dependent. It comprises all material properties of the semiconductor, the nature of the underlying physical charge–carrier transport process, and the physical construction of the device as well.

A deeper physical approach explaining the origin of different m and I_S values for different conditions is given in textbooks, for example in [17] or [18]. A detailed summary of the compact models to be used in circuit simulation can be found in [19].

In this article, we focus first on the midcurrent range, which is most suitable for using a semiconductor device as a temperature sensor for the thermal transient measurement technique. The measurement current is to be selected for the best temperature sensitivity and lowest noise on the recorded temperature-related signal.

After the appropriate equations are constructed, we extend the results to other current ranges which also exhibit a V_F = A·ln(I_F) + B style.

In the midcurrent and high-current range, a further term is to be added to (2) for an R_s series resistance. It cumulates the effect of the ohmic behavior of the semiconductor regions and the wiring in the package:

$$V_F\approx m{V}_T\ln \frac{I_F}{I_S}+I_F{R}_S$$

(3)

In the case where the $R_S$ term is mostly attributed to external wiring, its value is not influenced by the internal junction temperature. The $R_d=d{V}_F/d{I}_F$ differential resistance of the pn junction decreases at higher $I_F$ [16]:

$$R_d=\frac{d{V}_F}{d{I}_F}=\frac{m{V}_T}{I_F}+R_S$$

(4)

The $d{V}_F/dT$ temperature sensitivity itself slightly diminishes with growing $I_F$ forward current, as it will be pointed out below. This way, at a high enough measurement current, the inherent noise of the measurement current generator and the input amplifiers in the tester are effectively shunted by a low $R_d$. At even higher currents, undesirable self-heating effects can occur. At very low currents, the measurement is susceptible to external perturbations. A more rigorous analysis of the diode temperature sensors can be found in [20].

Keeping in mind the purpose of extending the analytical equations to different T temperatures from characteristics measured at the T₀ reference temperature, the describing equations are to be converted to a suitable format. Based on the style of Equations (2) and (3), for modeling the saturation current, we may introduce the temperature-dependent K factor:

$$K(T)=\frac{I_S\left(T\right)}{I_S\left(T_0\right)}$$

(5)

and with it, we can express (2) as

$$V_F\left(T\right)=V_F\left(T_0\right)\frac{T}{T_0}-m{V}_T\ln K\left(T\right)$$

(6)

Equation (6) indicates that the temperature-dependent voltage of the pn junction can be calculated from an operating point at the reference temperature if an appropriate model of the K(T) multiplier is available. As mentioned above, this K(T) multiplier is independent from the device voltage.

We can also get rid of an explicit $I_S$ parameter in (3) if two I_F forward current values are considered at the same device temperature:

$$V_{F1}-V_{F2}=m{V}_T\ln \left(\frac{I_{F1}}{I_{F2}}\right)+R_S·(I_{F1}-I_{F2})$$

(7)

In (7), all current and voltage values can be deduced from two measurements in the midcurrent range. Determining I_S is a more complex calculation with higher numerical error.

2.1. Short Summary of the Temperature-Dependent Semiconductor Properties

Before we discuss in detail the available models for different devices and current ranges, it is advisable to summarize the temperature dependence of the important semiconductor properties and phenomena. A deeper treatment of the topic is given in [16,17,18].

As long as the doping of the semiconductor material is relatively low, ionized atoms and the presence of movable electrons and holes are low in a given volume compared with the amount of crystal atoms there. The encounter of an electron with a hole is a rare event, and as such, the probability of the encounter is proportional to the n·p product, which equals through the mass action law:

$$n·p=n_i^2\left(T\right)=N_V\left(T\right)N_C(T) e^{-\frac{W_G\left(T\right)}{kT}}$$

(8)

where n and p are the density of the electrons and the holes, respectively, n_i is the intrinsic electron density, N_V and N_C are the effective density of states in the valence and conduction band, respectively, and W_G is the bandgap energy. The effective density of states is temperature-dependent, and the product can be simplified as

$$N_V\left(T\right)N_C\left(T\right)=G_{np}{T}^3$$

(9)

where G_np cumulates structural parameters of the crystal lattice with no significant temperature dependence.

In Equation (8), the bandgap tends to decrease with increasing temperature. The relationship can be modeled by the semiempirical Varshni expression [21]

$$W_G(T)=W_{G0}-\frac{\alpha T^2}{T+\beta }$$

(10)

where W_G0, α, and β constants are material parameters. For silicon, these constants are listed in

Table 1. Important temperature-dependent model parameters of silicon.

Model Parameter	Value	Reference(s)
WG0	1.16 eV	[21]
α	4.73 × 10−4 eV	[21]
β	636 K	[21]
W1	6.92 meV	[22]
Nref	1.3 × 1017/cm3	[22]
Θ	electron: 2.295,  2.3–2.6   hole: 2.248,   2.3–2.8	[23,24]
γ	electron: 1.77  hole: 0.57	[23]

.

In heavily doped semiconductors, the dopant band overlaps the conduction or the valence band, effectively narrowing the bandgap. For modeling the band gap narrowing, the empirical model of Slotboom is widely used [22]:

$${\Delta W}_G=W_1\left(\ln \frac{N_1}{N_{ref}}+\sqrt{{\ln }^2\frac{N_1}{N_{ref}}+\frac{1}{2}}\right)$$

(11)

where N₁ is the total dopant concentration, the sum of the $N_D$ donor and $N_A$ acceptor concentrations. W₁ and N_ref are material-related constants, listed in Table 1.

The current in a semiconductor is generated by the motion of free carriers. This motion is always a temperature-related random motion at high velocity, with energy exchange of crystal lattice atoms. A tiny directional component of the motion can be superposed on the random motion by an electric field (drift current) or by differences in carrier density (diffusion current). The collisions of the particles with the lattice can be interpreted as an obstacle against the drift current and formalized as $\mu$ carrier mobility. The temperature dependence of $\mu$ can be modeled by the following expression [23]:

$$\mu \left(T\right)=\mu (T_0){\left(\frac{T}{T_0}\right)}^{-\theta }$$

(12)

The exponent is negative, since the mobility will decrease for increasing temperature, and can be determined as ${\mu }_n$ and ${\mu }_p$ for electrons and holes experimentally. T₀ is again the reference temperature. The values found in the literature are also listed in Table 1.

For the diffusion current, the temperature dependence can be expressed similarly, through the well-known Einstein equation between the D diffusion coefficient and the $\mu$ mobility:

$$D\left(T\right)=\mu \left(T\right)·kT=D(T_0){\left(\frac{T}{T_0}\right)}^{1-\theta }$$

(13)

$D_n$ and $D_p$ can be derived for electrons and holes separately.

The generation and recombination mechanisms can also play an important part in the operation of the device. The simplest model for this mechanism is that the recombination or generation is proportional to the excess carrier density and inversely proportional to the ${\tau }_n$ and ${\tau }_p$ lifetimes of the electrons and holes. The temperature dependence can be modeled for both carrier types as follows [23]:

$$\tau \left(T\right)=\tau (T_0){\left(\frac{T}{T_0}\right)}^{\gamma }$$

(14)

where γ is positive, as the carrier lifetime is increasing with the temperature.

Using the references [17] or [18] and with the help of Equations (8)–(14), we can calculate the temperature-dependent behavior of the saturation current for different current mechanisms and different device constructions. Here, we summarize the results for the most important mechanism for our purposes, namely the low carrier injection in long and short pn junctions.

2.2. Long-Base Junction

In this case, we assume that the p side of the pn junction is much wider than the $L_n$ and $L_p$ diffusion lengths of the minority carriers. We also assume that the n layer is heavily doped. In that case, the current is transported mainly by electrons, and the $I_S$ saturation current becomes [17]:

$$I_S\approx qA\frac{D_n}{L_n}\frac{n_i^2}{N_A}=qA\frac{n_i^2}{N_A}\sqrt{\frac{D_n}{{\tau }_n}}$$

(15)

$A$ is the surface of the junction, $D_n$, $L_n$, and ${\tau }_n$ were defined for electrons above.

Using Equation (5), we can calculate a K factor, which is

$$K=\frac{I_S\left(T\right)}{I_S\left(T_0\right)}=\frac{n_i^2\left(T\right)}{n_i^2\left(T_0\right)}\frac{\sqrt{\frac{D_n\left(T\right)}{{\tau }_n\left(T\right)}}}{\sqrt{\frac{D_n\left(T_0\right)}{{\tau }_n\left(T_0\right)}}}$$

(16)

From the Equations (8)–(14), after substitution, we have

$$K={\left(\frac{T}{T_0}\right)}^{3+\frac{1-\theta -\gamma }{2}}{e}^{\frac{W_G\left(T_0\right)}{k{T}_0} - \frac{W_G\left(T\right)}{kT}}$$

(17)

And finally, the forward voltage at a given forward current can be expressed as

$$V\left(T\right)=V_G(T)+\frac{T}{T_0}\left(V_0-V_{G0}\right)-\left(3+\frac{1-\theta -\gamma }{2}\right)V_T\ln \frac{T}{T_0}$$

(18)

In this equation, we use the shorthands V_G = W_G/q and V_T = kT/q.

2.3. Short-Base Junction

In short or narrow pn diodes, for example, in the case of the emitter-base junction of a bipolar junction transistor, BJT, the physical length of the lighter doped side of the junction is less than the diffusion length of the minority carriers, and consequently, the thermal generation–recombination is negligible. We assume again, that the n layer is heavily doped. In this case, the saturation current can be expressed as in [17]:

$$I_S\approx qA\frac{n_i^2}{N_A}\frac{D_n}{w_D}$$

(19)

where $w_D$ is the width of the depleted layer. Following the analysis of the previous subsection, we can express the temperature dependence of the forward voltage:

$$V\left(T\right)=V_G\left(T\right)+\frac{T}{T_0}\left(V_0-V_{G0}\right)-\left(4-\theta \right)·V_T\ln \frac{T}{T_0}$$

(20)

A similar equation and its use in design and analysis of bandgap reference sources can be found in [25].

2.4. Other Current Mechanisms

It can be easily shown that using the same methodology, the temperature-dependent forward voltage can be calculated for other physical phenomena and device constructions, such as high-level injection or recombination current. The resulting expressions are very similar to the Equations (18) and (20) and have the following form:

$$V\left(T\right)=V_G(T)+\frac{T}{T_0}\left(V_0-V_{G0}\right)-{\xi V}_T\ln \frac{T}{T_0}$$

(21)

The value of ξ for some important physical processes is presented in

Table 2. Constants for Equations (2), (21), and (22).

Dominant Physical Process	m	ξ
Trap-assisted recombination	2	$3-2\gamma$
Low injection, long diode	1	$3+\frac{1-\theta -\gamma }{2}$
Low injection, short diode	1	$4-\theta$
High injection (ambipolar diffusion)	2	$4-\theta -\gamma$

.

In a previous work [7], we used (21) to model the change in the temperature sensitivity, the S_VF = dV_F/dT quantity:

$$\frac{d{V}_F}{dT}=\frac{V_F-V_G}{T}-\mathsf{\xi }\frac{\mathrm{k}}{\mathrm{q}}+\frac{d{V}_G}{dT}$$

(22)

Some quantitative estimations can easily be made on the scale of the terms in Equation (22). For example, in silicon material at light doping, the bandgap energy at 300 K temperature is 1.12 eV. For a small diode, 0.7 V forward voltage at 1 mA current is a reasonable approximation. This results for the first term in about −1.4 mV/K, the second term adds −0.39 mV/K (considering low injection of electrons), and the third term will be −0.26 mV/K, resulting in the expected sensitivity of around −2 mV/K. For visualizing the influence of the bandgap voltage, Figure 3 presents the temperature dependence of the bandgap voltage and its derivate for silicon. The results were calculated analytically from Equations (10) and (22) using the material parameters in Table 1.

2.5. The Effect of the Ohmic Resistance in Semiconductors

For low currents, the effect of the resistance of the ohmic regions in the semiconductor at both sides of a junction and the wiring in the package can be neglected, but for medium and higher currents, the temperature-dependent series resistance should also be modeled. We can assume that most of the series resistance is caused by the ohmic region of the lightly doped side of the pn junction. The thermal coefficient of the resistance of an extrinsic semiconductor can be positive or negative, since the carrier mobility decreases, but the number of minority carriers increases with the rising temperature, which can compensate the mobility decrease if the doping level is low. The $\sigma$ electrical conductivity is given by

$$\sigma =q({\mu }_{n}n+{\mu }_{p}p)$$

(23)

In Equation (23), the temperature dependence of the carrier mobilities can be calculated from (12) and the carrier concentration from (8). In the case of silicon, at the usual doping levels and temperature range, we can expect that the carrier mobility change dominates; therefore, the temperature-dependent resistance of a doped silicon resistor can be expressed as

$$R\left(T\right)\cong R(T_0){\left(\frac{T}{T_0}\right)}^{-\theta }$$

(24)

3. Instrumentation and Measurement Scheme

In order to verify our findings, we accomplished measurements on various bipolar and MOS transistors. Some of the results are very promising, but some need further investigation. In this article, we present the measurement results of some typical, widely used, and commercially available silicon samples. We are also conducting experiments on wide-band-gap semiconductors, and the results are still under evaluation.

In most cases, the measured devices were mounted on a dry thermostat (Arroyo Instruments 264M-BB-DB9), and we recorded the I–V characteristics using a Keithley 2450 source meter at temperatures between 10 °C and 100 °C, in 10 °C steps. We selected devices in TO-220 or similar packages to ensure small thermal resistance between the junction and the thermostat’s plate.

In certain complex appliances, the critical power devices can be accessed in a true four-wire, force/sense manner (4W access, Kelvin contact). In other cases, the access is limited to just two wires with current drive and voltage sensing (2W access). For example, half-bridge modules may have dedicated force and sense pins, but the internal wiring in the module still has to be considered.

In the actual measurements, the driving current was changed from 100 nA to 100 mA in logarithmically equidistant points, with 20 points/decade resolution. The four-wire measurement method was used with the default settings of the Keithley 2450 source meter (the number of power cycle lines was set to one, and auto-zero and automatic measure range selections were activated). For comparison, some measurements were repeated in a 2W setup, in which an external R_S series resistance corresponding to the force wires can be observed in the measured device characteristics.

Recording the I–V characteristics took about 10 s, and the stabilization of the thermostat at each temperature point took about 5–10 min, resulting in about 1.5 h total measurement time.

For MOS transistor measurements, we added a 4 × AA battery pack (~6 V) as noiseless gate-source voltage to properly close the channel during body diode measurements. This addition was not necessary for silicon MOS transistors; however, it is an essential setup for the measurement of silicon–carbide devices [26].

Due to the limitations of the dry thermostat, and to achieve more than 100 °C temperature change, in some measurements, we used a Julabo Presto A40 circulator thermostat and a cold plate. With this thermostat, it was possible to cool down the samples to −20 °C and heat them up to 120 °C temperature. We measured the temperature directly of the aluminum plate with an Ametek DTI-1000 A digital thermometer.

In these latter measurements, a Keysight U2722A source meter unit recorded the I–V characteristics. The forced current was programmed between 100 nA and 100 mA, with 12 points/decade. An I–V measurement took about 5 s; however, the stabilization of the thermostat took about 10–20 min at each temperature point, and lower temperatures required the longest setting time.

4. Results

For verifying the concept, the analytical equations with their governing parameters were compared with the measured data on several devices possessing suitable pn junctions. The measurement arrangements corresponded to the powering and sensing concepts used in actual thermal transient tests.

When testing bipolar transistors, the heating during the test is applied in normal active operation, and the transient measurement occurs in the same mode at a bias in the midcurrent range. In the case of MOSFETs, the heating can occur at a high current on the conducting channel or on the reverse-biased inherent bulk diode. The transient measurement is performed most frequently on the reverse diode.

In this article, we present a selection of measurements to verify the applicability of the method.

We selected devices of different breakdown voltage (40 V to 120 V), that is, of highly different dopant concentrations on the lightly doped side of the junction. We also selected devices of different current limits (3 A to 75 A). These devices were encapsulated in similar TO220 packages, but, as the current limit indicates, the internal chip surface may vary at a ratio of 1:20. Accordingly, the forward voltage measurement at similar currents covered highly different current densities, without using high current instrumentation and special wiring considerations.

Table 3. The measured devices with major datasheet values.

Manufacturer	Device
	Type		Max. Current	Max. Voltage	RDSON [Ω]
ON Semi	BD241C	npn	3 A	5 V/100 V	NA
ON Semi	MJE15029	pnp	8 A	5 V/120 V	NA
ON Semi	BUV26	npn	20 A	7 V/90 V	NA
Infineon	IRF3710	nMOS	57 A	100 V	23 mΩ
Infineon	IRF2804	nMOS	75 A	40 V	2 mΩ

lists the device types that we present now from a larger set of verification measurements. For bipolar transistors, the maximum voltages for both the base-emitter and base-collector junctions are listed.

4.1. Bipolar Transistors

The transistors were measured as a pn junction between the emitter and the connected base and collector.

To illustrate the concept, first, we select Sample MJE15029, which is a typical bipolar transistor of pnp type. Figure 4 shows the I–V characteristics of the transistor at different temperatures, measured in 2W arrangement. At low current, the characteristics generally follow Shockley Equation (1). Above 10 mA, the decline of the curves indicates that the effects of high injection and the serial resistance begin to dominate.

Figure 5 compares the measured I–V characteristics in 2W and 4W arrangements.

We calculated an effective m diode ideality factor from the differential resistance of the diode, transforming (7) into the following equation:

$$r_d=\frac{\partial V_F}{\partial I_F}=\frac{m{V}_T}{I_F}\cong \frac{\Delta V_F}{\Delta I_F}$$

(25)

In this approach, the change in the m factor includes the effect of the series resistor, too. The m factor calculated from 2W measurements is plotted in Figure 6. In true 4W measurements, this effective m grows to approximately 1.3 only, due to internal resistances in the transistor package and high injection effects in the junction.

At low current levels, this function shows very small temperature dependence, and its value is practically the m = 1 textbook value, as it is expected from the measured I–V characteristics. Above 1 mA, it starts to slightly increase, but at higher injection levels, the m parameter still shows a small temperature dependence, which can be attributed to the resistance of the nondepleted collector region.

After finishing the measurements over a large current and temperature range, one selected curve, e.g., the one measured at 20 °C, can serve as a reference to produce the analytical equations. Then, the measured I–V curves can be compared with the calculated ones at different temperatures.

In the case of a bipolar transistor, the emitter layer is strongly doped, the base is moderately doped, and the collector is lightly doped. The emitter-base diode in this case can be considered as a narrow diode, and we can calculate the temperature dependence of the forward voltage according to Equation (20).

It is worth remarking that the accuracy of the calculated forward voltage heavily depends on the accuracy of the bandgap voltage model. Since the base is moderately doped, we must take the bandgap narrowing effect into account.

Unfortunately, the doping profile of a commercial device is usually unknown; however, it is possible to estimate an average doping from the breakdown voltage. Equation (26) shows an approximate experimental expression connecting the breakdown voltage, the bandgap, and the doping concentration according to Equation 104 in Chapter 2 [18]:

$$V_{BD}\approx 60{\left(\frac{W_G}{1.1 \mathrm{e}\mathrm{V}}\right)}^{\frac{3}{2}}{\left(\frac{N}{{10}^{16} \mathrm{c}{\mathrm{m}}^{-3}}\right)}^{-\frac{3}{4}}$$

(26)

where W_G is the bandgap energy at room temperature in electronvolt, and N is the doping concentration of the lightly doped side of the junction in cm⁻³.

This equation is valid for an abrupt pn junction, which is not typical in bipolar devices; however, we only use it for the estimation of the band gap narrowing. Due to the logarithmic nature of Equation (11), an order of magnitude accurate estimation is sufficient.

The breakdown voltage can be measured, or it can be estimated from the datasheet value, and the bandgap narrowing can be calculated from Equations (11) and (26).

The serial resistance also can be estimated from the current–voltage characteristics by comparing the ideal and the experimental curve, as can be seen in Figure 7.

$$R_S\approx \frac{\Delta V}{I}$$

(27)

In this work, we demonstrate the validity of the concept first by measurements on three bipolar devices, followed by calculating an analytic model with the parameters in

Table 4. Model parameters for the analytical calculations in the case of BJTs.

Device	Type	Estimated VBR [V]	Approximate NB [cm−3]	ΔWBGN [meV]	RS, 4W [mΩ]	RS, 2W [mΩ]	ξ
MJE15029	pnp	6	2.2 × 1017	9.5	69	304	1.8
BD241C	npn	6	2.2 × 1017	9.5	58	289	1.6
BUV26	pnp	8	1.5 × 1017	5.8	43	489	1.6

.

In the table, the V_BR breakdown voltage values were estimated from the voltage limit of the base-emitter junction, taken from the datasheet (shown in Table 3). We assumed a 20% safety margin between the specified maximum limit value and the actual breakdown voltage.

Figure 8 compares three measured I–V curves at characteristic temperatures (10 °C, 50 °C, and 100 °C) with their corresponding analytical counterparts generated from the single measurement at 20 °C in 4W arrangement. The measured curves are represented as solid lines and the calculated ones as dashed lines in the figure.

The calculation steps are as follows:

• The diode ideality factor was calculated using Equation (2) in order to identify the different regions of the I–V characteristic.
• The series resistance was determined using Equation (27), using linear regression in the low-injection region, in the 0.1 mA to 1 mA current range.
• The temperature-dependent bandgap voltage was calculated using Equations (10), (11) and (26).
• Finally, the characteristics were calculated at different temperatures using Equation (20).

Figure 8 indicates that the measured and the analytically calculated curves nearly coincide, especially at higher currents. The fit appears to be perfect, but it has to be noted that in the usual logarithmic current vs. linear voltage plots, the difference in the higher current range is hardly visible. The difference can be contrasted presenting the difference between the measured and analytically calculated characteristics, as shown in Figure 9.

The accuracy of the modeling is acceptable, as it is on the order of a few millivolts in a wide temperature and current range. The difference between calculated and measured values is the lowest in the medium current range and tends to increase for both low and higher current ranges due to different current mechanisms with different thermal behavior.

The match of the model depends on the assumed value of the V_g bandgap voltage. A numerical optimization can be carried out if the I–V characteristics are measured at two different temperatures. Such an optimization process yields even more accurate results, but for the above-mentioned reasons, the target was to perform the calibration based on a single temperature I–V measurements. A more detailed discussion on V_g estimation is presented in Section 4.2 for MOSFET devices, where the deviation between measured and calculated data is noteworthy.

The data presented in Figure 8, showing temperature-dependent current related to forward voltage, can also be plotted in a more familiar way for the TSP analysis. Figure 10 converts the data to the typical look of TSP calibration curves; now, the horizontal axis shows the temperature, the vertical axis is the forward voltage on the device, and the current is the parameter assigned to selected curves. Again, markers denote measured data, and dashed lines denote the analytically calculated functions.

Sample BUV26 was the next device, a typical bipolar transistor of npn type. The measured and calculated I–V characteristics are shown in Figure 11, and the differences between the analytically calculated and measured characteristics are plotted in Figure 12. The increasing difference in the higher current range indicates that the simple serial resistance model needs further consideration; however, the difference in the medium current range is acceptable.

Figure 13 presents the TSP calibration curves created from the I–V curves for the BUV26 transistor.

The next measured sample was BD241C, which is also a bipolar transistor of npn type. Similar charts can compare the analytically calculated I–V curves to measured data points again.

In a previous work [7], we already attempted to analytically calculate the sensitivity at different temperatures and currents. However, using Equation (20), we may calculate and compare more than just the sensitivity. We may transform the measured and calculated I–V curves into the form of the usual TSP calibration curves in the measured temperature range. Figure 14 shows the actual measured and calculated calibration curves for the BD241C transistor in a higher temperature range between −15 °C and +130 °C.

Finally, taking the voltage difference between the measured and calculated calibration curves, we calculated the temperature prediction accuracy of the analytical expressions for different forward currents.

Table 5. Accuracy of the calculated TSP calibration curves at different forward currents with the largest deviation from the analytical formula over the measured temperature interval.

Device	Δ[email protected] [°C]	ΔT@1mA [°C]	ΔT@10mA [°C]	Δ[email protected] [°C]
BD241C 4W	2.59 (2.9%)	1.35 (1.5%)	0.70 (0.8%)	0.60 (0.7%)
BD241C 2W	0.63 (0.7%)	0.6 (0.7%)	1.24 (1.4%)	1.55 (1.7%)
MJE15029 4W	0.31 (0.3%)	0.12 (0.1%)	0.06 (0.1%)	0.62 (0.7%)
MJE15029 2W	1.16 (1.3%)	0.97 (1.1%)	0.83 (0.9%)	1.31 (1.5%)
BUV26 4W	0.78(0.9%)	0.6(0.7%)	0.4(0.4%)	0.58(0.6%)
BUV26 2W	0.08 (0.1%)	0.23 (0.3%)	0.91 (1%)	5.82 (6.5%)

summarizes the accuracy of the calculated TSP calibration curves, that is, the largest deviation from the analytical formula over the measured temperature interval, expressed as the absolute difference in °C and percent of the measured temperature sweep.

A general tendency can be observed in Table 5. At higher currents, in this case at 100 mA, the 4W approach yields a significantly better approximation than the 2W arrangement, as expected. Slightly higher errors appear in some measurements at low I_F forward currents. We suspect that the measurement is susceptible to internal noise and external perturbations due to the high R_S differential resistance of the junction. The measured V_F forward voltage can be slightly deviated, e.g., by rectified induced interference.

Still, the accuracy of the temperature estimation is high in all cases.

4.2. MOSFET Transistors

In the next series of experiments, several MOSFET devices were tested in the previously defined current and temperature range. These transistors were robust devices with large chip surfaces and, accordingly, of high maximum drain current and low channel resistance.

The measurements were carried out on the inherent bulk diode of the MOSFETs, which covers the whole chip surface. In this measurement series, a 4W arrangement was used. This way, the modeling was extended to low-concentration doping profiles, as is typical for bulk diodes with high breakdown voltage and low current densities.

The first selected sample was an Infineon nMOS device, IRF3710. Using the same methodology as in the previous section, we analytically calculated the characteristics and the calibration curves from a single measurement at 20 °C. In such vertical trench devices, the body diode must be treated as a long pn junction diode; therefore, Equation (18) was used. To achieve high breakdown voltage, the body of the MOSFET is lightly doped; therefore, as stated above, the bandgap narrowing effect can be neglected.

Table 6. Model parameters for the analytical calculations in the case of MOSFETs.

Device	Type	Appr. NB [cm−3]	RS, 4W, [mΩ]	ξ
IRF3710	nMOS	4 × 1015	5.69	1.465
IRF2804	nMOS	1.7 × 1016	3.55	1.465

shows the model parameters for the analytical calculations.

However, using the same thermal parameters as in the case of the bipolar junction transistor, the calculated I–V characteristics show a larger offset than in previous tests, resulting in more than 5% relative error, as can be seen in Figure 15.

Figure 16 presents the data in Figure 15 converted to the look of TSP calibration curves; markers again denote the measured data, and dashed lines denote the analytically calculated functions.

In Figure 15 and Figure 16, we can observe that a visible difference appeared between the measured and the calculated values in the chart compared with similar charts for bipolar transistors in the previous section. The error term keeps increasing with the temperature, and the difference can be read along a horizontal line at fixed V_F forward voltage (red arrows in the figure): it is 4 °C at a 100 °C junction temperature, which is actually an acceptable deviation for most purposes.

An analytical model should reflect the physical reality within an error margin. We claimed in the Introduction that this can only be achieved if when tuning a single, physically sound parameter, the error diminishes. Analyzing the parameters in Equations (15)–(18), we found that a reasonable correction of the V_g bandgap voltage results in a nearly perfect fit.

Shrinking of the bandgap voltage is typically attributed to higher dopant concentration in the semiconductor. Note that the temperature-dependent shrinking of V_g was taken into account in all previous calculations (Equation (10)). For bipolar transistors, in the previous section, a further correction guess was made on doping-concentration-related effects based on the breakdown voltage.

An easy and obvious step to calculate V_g shrinking would be to measure the characteristics at at least two different temperatures. However, this is exactly what we want to avoid, at least for complex appliances or subassemblies, in order to determine the TSP value in a fast and easy way. At present, our team is working on developing a V_g correction method considering further device parameters or datasheet values.

In this work, it is easy to check the concept of V_g correction, as the charts were constructed from many measurements at various temperatures. We found that by diminishing the textbook value of V_g by 34.7 mV, a perfect fit of the analytic and measured values can be reached again. This parameter was extracted using two I–V characteristic curves at 20 °C and 30 °C, between 0.1 mA and 100 mA.

Figure 17 compares the TSP calibration curves of the measured MOSFET (markers) and the analytically calculated functions, now with V_g with correction (dashed lines). The reference temperature for the calculation was 20 °C, and the required correction in the bandgap voltage was 34.7 mV.

The next MOSFET device tested was the bulk diode of an IRF2804 transistor. This device was tested in a broader temperature range, between approximately −15 °C and 135 °C, in 15 °C steps. For a better fit of the measured and calculated curves, the bandgap voltage correction step was required again. The calculated TSP calibration curves can be seen in Figure 18. With this correction, it was possible to achieve the same level of model accuracy as in the case of bipolar devices.

We summarized the achieved accuracy of this model after the correction step in

Table 7. Accuracy of the calculated TSP calibration curves with the largest deviation from the analytical formula over the measured temperature interval before (normal) and after (italic) correction.

Device	Δ[email protected] [°C]	ΔT@1mA [°C]	ΔT@10mA [°C]	Δ[email protected] [°C]
IRF3710	3.6 (4%) 0.12 (0.1%)	3.67 (4.1%) 0.32 (0.4%)	3.8 (4.2%) 0.55 (0.6%)	4.19 (4.7%) 0.61 (0.7%)
IRF2804	2.71 (1.9%) 0.85 (0.6%)	3.36 (2.3%) 1.31 (0.9%)	4.16 (2.9%) 2.15 (1.5%)	6.32 (4.4%) 3.8 (2.6%)

, again as the largest deviation from the analytical formula over the measured temperature interval, expressed as the absolute difference in °C and percent of the measured temperature sweep.

5. Conclusions

In this paper, we presented the theoretical background of a methodology that enables one to speed up the thermal transient testing of power semiconductor devices. The method replaces the lengthy traditional calibration process of measuring the forward voltage of the semiconductor device in a large range of temperatures by a fast, single measurement of the I–V characteristic of the device.

We verified by a series of measurements that the method is highly accurate for bipolar silicon devices in a large current range and in a broad temperature range, enabling even lifetime prediction.

In some cases, mostly in the case of MOSFETs, the temperature prediction error is higher, on the order of about 5–10 °C. In such cases, the accuracy of the analytical model could be further improved in a correction step, based on a second measurement at a different temperature, or an estimation of the change in the bandgap based on physical considerations or literature data.

The presented measurements on different devices demonstrate the applicability and the accuracy of the method for silicon devices of very different structures.

Currently, we are working on extending the methodology to wide-band-gap materials.