Switched Capacitor Inverter with Reduced Inrush Current and High Boosting Gain

Abstract

This article describes a 17-level switched-capacitor-based eight-times-boosting gain inverter. The inverter is made up of a DC power source, thirteen switches, three diodes, and three capacitors. The inverter produces seventeen steps during each cycle and crosses the zero line two times in one complete cycle. The proposed inverter has its polarity change mechanism; it is not necessary to use an H-bridge. Three self-balancing capacitors make up this construction. The capacitors automatically balance voltage by connecting in series/parallel to the input voltage source. Logic gates can generate gate pulses with the phase disposition pulse-width modulation technique, which helps to preserve capacitor voltage balance at the same time. The proposed structure was compared to recent papers, analyzing factors including voltage gain, DC sources, semiconductor devices, cost function, and TSV. The proposed configuration offers cost effectiveness and fewer semiconductor devices for providing a 17-level output with sufficient voltage gain. Also, to reduce the capacitor inrush current, soft charging is used. Additionally, the proposed structure’s power losses were examined, confirming its efficiency. Finally, an experimental prototype was tested to analyze and validate the suggested structure’s performance under various situations. Results show the proposed structure performs well under steady and dynamic situations.

1. Introduction

Renewable Energy Resources (RES) are increasing the demand for Multi-Level Inverters (MLIs) in industrial applications like motor drives, speed control, grid integration, UPS, and electric cars. MLIs are preferred due to their superior sinusoidal output, reduced harmonics, improved efficiency, and enhanced electromagnetic compatibility. The decrease in dv/dt ratio reduces the blocking voltage requirement, resulting in a smaller filter and lower costs [1,2,3,4].

Over the years, the MLI has evolved from a simple two-level inverter to a conventional one to address issues like high voltage stress and device rating limitations, demonstrating the continuous progress of MLI technology over time [5,6]. The three most common conventional MLIs are neutral-point clamped (NPC), cascaded H-bridge (CHB), and flying capacitors (FC) [7]. The two-level inverter solution addressed issues but also had drawbacks. It required more components for higher output voltage generation, and standard MLIs lacked capacitor voltage balancing and the ability to perform self-voltage boosting, which hindered many topologies [8]. Switched capacitor (SC) inverters offer near-sinusoidal output voltages and reduced harmonics, making circuitry less complicated. SC-based topologies reduce the device number, losses, and ratings, and require fewer input supplies and power electronics devices. They are suitable for applications requiring medium-to-high voltage, such as variable-speed drives, electric vehicles, and grid-tied energy systems. SC-based topologies are preferred for applications requiring medium-to-high voltage [9].

The Modular Multi-Level Converter (MMC) is a bidirectional high-voltage direct current converter with excellent efficiency and benefits. However, its drawbacks include the high number of components required due to the half or full bridge and capacitor, which increases system costs. Capacitor voltage balancing is difficult when capacitor values are high, and an output filter and interface transformer are required [10]. Recent MLIs aim to reduce component usage, such as usage of switches, DC sources, and capacitors, while increasing voltage gain without increasing total standing voltage. The author of [11,12,13] suggested that adopting different topologies can reduce the number of switches. The H-bridge can generate positive and negative cycles, but its higher blocking output voltage limits its usage to high voltages. To solve this challenge, using designs like E-type [14] and ST-type [15] designs, which generate both positive and negative cycles independently, is considered. In articles [16,17,18,19], researchers devised a new method to generate various levels. A basic device was constructed using only a few switches, capacitors, and DC sources. A cascade of these devices was then coupled to provide a high-level output. Cascaded MLI is the name given to this form of MLI. Reducing the number of switches while simultaneously elevating the level of fundamental units was a goal for the authors of [17,18,19,20,21,22,23]. Different DC sources can also be found in some asymmetric models. The number of DC sources that make these systems unachievable is a fundamental worry. Applications with asymmetric multi-input sources and highly inductive loads are well suited to the methods described by [24], which use multiple voltage sources to produce a nine-level output voltage. Voltage stress equivalent to the maximum output voltage is something that the majority of switches in these topologies have to endure. The topology in [25] generates 17- and 9-level output voltage using multiple voltage sources, making it ideal for asymmetric multi-input sources with inductive loads. However, most switches in these topologies must sustain voltage stress equal to the output voltage peak. To overcome the need for several high-rated voltage sources and switches, Ref. [26] proposes SCMLI topologies with a single input voltage source. Some publications propose SCMLI topologies with a single input voltage source to solve the problems of high-rated switches and numerous voltage sources [27,28]. Out of these two, Ref. [28] could increase the input voltage at the load terminal by a factor of three. Ref. [26] could increase the input voltage by three times at the load terminal. Octal boosting is possible in the topologies introduced in [29,30,31,32]. The authors in [29] used 14 switches, resulting in four times the input voltage on the switched capacitor unit. In contrast, Refs. [30,31] used more diodes, which may cause circuit imbalance due to their longer reverse recovery time. A seventeen-level topology with a single source is another MLI that is covered in [33]. Output voltage THD is under the IEEE-519 limit because of the seventeen voltage levels; however, the circuit is more complex owing to the number of components and the problems in balancing the charges of the capacitors. More MLIs have been documented for use in extremely sensitive applications prioritizing power quality over inverter size and cost [34]. The topology in [35] is capable of producing 17 levels of output voltage. However, it offers a gain of less than eight, and the voltage stress is equal to the output voltage.

The research in the literature indicates that most SCMLI topologies have low voltage gain or high voltage stress on switches, and high inrush current with high semiconductor counts. The goal is to increase dynamic boosting, decrease component voltage stress, reduce heavy inrush current, and employ fewer components. With the goal of developing a high-gain MLI with only one source, lower TSV, fewer components, and increased efficiency, the idea is inspired by the desire to achieve these conditions.

A switched-capacitor-based 17-level design is described in this study, and the following contributing elements are included in the architecture:

• The suggested architecture has a lesser number of components: one DC source, three diodes, and thirteen switches;
• The proposed topology possesses voltage-boosting capability;
• A voltage sensor circuit is not needed because the capacitors’ voltage is self-balancing;
• LS-SPWM control logic (i.e., complementary switching pair for pulse creation) is developed;
• The topology with a charging inductor and diode reduces capacitor inrush current to a great extent;
• The topology is cost effective and can be used for medium-to-high-power applications.

In Section 2, this paper discusses how the proposed topology was designed and how well it worked. It also talks about how capacitors were chosen and how much power was lost. In Section 3, more comparisons are made to show how the suggested topologies are better. An experiment is carried out using a prototype, and the results are presented in Section 4. Finally, in Section 5, this paper is concluded.

2. Proposed Switched Capacitor Topology

The proposed SC-MLI is developed by using 13 power switches, of which 11 are bidirectional and 2 are made unidirectional by using a diode in series with each. In total, three diodes are used in the proposed design, and three capacitors are used to store charge and act as a voltage source when needed. The construction of the proposed system can be seen in Figure 1.

Figure 2 depicts another design that differs somewhat from the previous one. When using this configuration, an inductor diode is linked in series with the voltage source, and a diode is connected in parallel with the inductor. The primary goal of this enhancement is to prevent the capacitor from being overcharged or undercharged while it is being charged. This will also have an effect on the capacitor’s spike current, which will lower the losses and enhance the capacitor’s life span.

Figure 1. Proposed SC-MLI topology without inductor diode.

Figure 1. Proposed SC-MLI topology without inductor diode.

Figure 2. Proposed SC-MLI topology with inductor diode.

Figure 2. Proposed SC-MLI topology with inductor diode.

2.1. Operation

The functioning operation of the suggested design is completely dependent on the switching sequence of the switches, which may be seen in the preceding table (

Table 1. Proposed topology includes switches, diodes, and capacitor states.

Switches	Diodes	Capacitors			${\mathit{V}}_{\mathit{out}}$
		${\mathit{C}}_{\mathbf{1}}$	${\mathit{C}}_{\mathbf{2}}$	${\mathit{C}}_{\mathbf{3}}$
$T_2$, $T_9$, $T_{12}$, $T_6$, $T_5$, and $T_3$	−	⇓	⇓	⇓	$+8V_{\mathrm{in}}$
$T_2$, $T_9$, $T_8$, $T_6$, $T_5$, and $T_3$	$D_1$	⇑	⇓	⇓	$+7V_{\mathrm{in}}$
$T_2$, $T_{11}$, $T_{12}$, $T_{13}$, $T_6$, $T_5$, and $T_3$	$D_2$	⇓	⇑	⇓	$+6V_{\mathrm{in}}$
$T_2$, $T_{11}$, $T_8$, $T_6$, $T_5$, and $T_3$	$D_1$	⇑	¬	⇓	$+5V_{\mathrm{in}}$
$T_2$, $T_9$, $T_{12}$, $T_7$, $T_3$, $T_5$, and $T_{10}$	$D_3$	⇓	⇓	⇑	$+4V_{\mathrm{in}}$
$T_2$, $T_9$, $T_8$, $T_7$, and $T_3$	$D_1$	⇑	⇓	¬	$+3V_{\mathrm{in}}$
$T_2$, $T_{12}$, $T_{11}$, $T_7$, $T_3$, and $T_{13}$	$D_2$	⇓	⇑	¬	$+2V_{\mathrm{in}}$
$T_2$, $T_{11}$, $T_8$, $T_7$, and $T_3$	$D_1$	⇑	¬	¬	$+1V_{\mathrm{in}}$
$T_1$, $T_5$, and $T_3$	-	¬	¬	¬	0
$T_2$ and $T_4$	-	¬	¬	¬	0
$T_1$, $T_{11}$, $T_8$, $T_7$, $T_5$, and $T_4$	$D_1$	⇑	¬	¬	$-1V_{\mathrm{in}}$
$T_1$, $T_{11}$, $T_{12}$, $T_7$, $T_4$, $T_5$, and $T_{13}$	$D_2$	⇓	⇑	¬	$-2V_{\mathrm{in}}$
$T_1$, $T_9$, $T_8$, $T_7$, $T_5$, and $T_4$	$D_1$	⇑	⇓	¬	$-3V_{\mathrm{in}}$
$T_1$, $T_9$, $T_{12}$, $T_7$, $T_4$, $T_5$, and $T_{10}$	$D_3$	⇓	⇓	⇑	$-4V_{\mathrm{in}}$
$T_1$, $T_{11}$, $T_8$, $T_6$, and $T_4$	$D_1$	⇑	¬	⇓	$-5V_{\mathrm{in}}$
$T_1$, $T_{11}$, $T_{12}$, $T_{13}$, $T_6$, and $T_4$	$D_2$	⇓	⇑	⇓	$-6V_{\mathrm{in}}$
$T_1$, $T_9$, $T_8$, $T_6$, and $T_4$	$D_1$	⇑	⇓	⇓	$-7V_{\mathrm{in}}$
$T_1$, $T_9$, $T_{12}$, $T_6$, and $T_4$	−	⇓	⇓	⇓	$-8V_{\mathrm{in}}$

). It is possible to generate distinct paths by turning on and off the switches at different periods, which facilitates the formation of steps, as shown in Figure 3 and Figure 4. These steps are generated through the use of a voltage source (V_in) and the charging shown by (⇑) and discharging shown by (⇓) of capacitors at specific times. Sign “¬” in Table 1 shows as not connected during that particular operation. The operation of the step formation of the positive half is represented in Figure 3, and the operation of the step formation of the negative half is represented in Figure 4. As seen in Figure 3 and Figure 4, the dotted line shows the path created by turning on the switches as per the order mentioned in Table 1. In Figure 3a, switches T₁, T₅, and T₃ are on. Turning on these switches helps in generating the zero level.

The positive cycle operation of the proposed design is as follows.

2.1.1. Step P1

Figure 3b: V_in voltage is obtained at load by turning on switches T₂, T₁₁, T₇, and T₃, and, by turning on switch T₈, capacitor C₁ is charged with V_in voltage as well.

2.1.2. Step P2

Figure 3c: Turning on switches T₂, T₁₂, T₁₁, T₇, and T₃, 2V_in voltage is obtained at load by connecting voltage source and capacitor C₁ in series. T₁₃ is switched on along with it, and capacitor C₂ is charged with 2V_in.

2.1.3. Step P3

Figure 3d: When T₂, T₉, T₇, and T₃ are switched on, V_in and C₂ are connected in series and result in 3V_in across load. Switch T₈ is switched on simultaneously, and C₁ starts charging.

2.1.4. Step P4

Figure 3e: Now, when T₂, T₁₂, T₉, T₇, and T₃ are switched on, V_in, C₁, and C₂ are connected in series and result in 4V_in across load. Switch T₁₀ is switched on simultaneously, and C₃ starts charging with 4V_in.

2.1.5. Step P5

Figure 3f: Voltage 5V_in is obtained by turning on T₂, T₁₁, T₆, T₅, and T₃. Here, C₃ is connected in series with V_in. Simultaneously, T₈ is turned on, and C₁ starts charging.

2.1.6. Step P6

Figure 3g: When T₂, T₁₂, T₁₁, T₆, T₅, and T₃ are switched on, V_in, C₁, and C₃ are connected in series and result in 6V_in across the load. Switch T₁₃ is switched on simultaneously, and C₂ starts charging with 2V_in.

2.1.7. Step P7

Figure 3h: For obtaining 7V_in along the load, switches T₂, T₉, T₆, T₅, and T₃ are turned on, and, simultaneously, T₈ is turned on to charge C₁.

2.1.8. Step P8

Figure 3i: For obtaining 8V_in, all three capacitors are connected in series with voltage source V_in by turning on T₂, T₁₂, T₉, T₆, T₅, and T₃.

As shown in Figure 3j, another zero level can be generated by turning on the switches T₂ and T₄. The negative cycle operation of the proposed design is as follows.

2.1.9. Step N1

Figure 4a: −V_in voltage is produced at load by turning on switches T₄, T₁₁, T₇, and T₁, and, by turning on switch T₈, capacitor C₁ is charged with V_in voltage simultaneously.

2.1.10. Step N2

Figure 4b: Turning on switches T₄, T₁₂, T₁₁, T₇, T₅, and T₁, −2V_in voltage is obtained at load by connecting voltage source and capacitor C₁ in series. T₁₃ is switched on along with it, and capacitor C₂ is charged with 2V_in.

2.1.11. Step N3

Figure 4c: When T₄, T₉, T₇, T₅, and T₁ are triggered, V_in and C₂ are connected in series and generate −3V_in across the load. Switch T₈ is switched on simultaneously, and C₁ starts charging.

2.1.12. Step N4

Figure 4d: Now, when T₄, T₁₂, T₉, T₇, T₅, and T₁ are switched on, V_in, C₁, and C₂ are connected in series and result in −4V_in across the load. Switch T₁₀ is switched on simultaneously, and C₃ starts charging with 4V_in.

2.1.13. Step N5

Figure 4e: Voltage −5V_in is obtained by turning on T₄, T₁₁, T₆, and T₁. Here, C₃ is connected in series with V_in. Simultaneously, T₈ is turned on, and C₁ starts charging.

2.1.14. Step N6

Figure 4f: When T₄, T₁₂, T₁₁, T₆, and T₁ are switched on, V_in, C₁, and C₃ are connected in series and result in −6V_in across the load. Switch T₁₃ is switched on simultaneously, and C₂ starts charging with 2V_in.

2.1.15. Step N7

Figure 4g: For obtaining −7V_in along the load, switch T₄, T₉, T₆, and T₁ are turned on, and, simultaneously, T₈ is turned on to charge C₁.

2.1.16. Step N8

Figure 4h: For obtaining −8V_in, all three capacitors are connected in series with voltage source V_in by turning on T₄, T₁₂, T₉, T₆, and T₃.

The charging and discharging pattern of both positive and negative cycles will be the same as shown in Figure 5.

2.2. Maximum Blocking Voltage (MBV)

The total standing voltage (TSV) is calculated by adding up the individual MBV of all of the power electronics switches:

$$V_{\mathrm{M}\mathrm{B}\mathrm{V}}=\left\{\begin{array}{c}{T}_1,T_2,T_4=8V_{\mathrm{DC}}\hfill \\ T_3,T_5,T_6,T_7,T_{10}=4V_{\mathrm{DC}}\hfill \\ T_{13}=3V_{\mathrm{DC}}\hfill \\ T_9,T_{11}=2V_{\mathrm{DC}}\hfill \\ T_8,T_{12}=1V_{\mathrm{DC}}\hfill \end{array}\right.$$

(1)

2.3. Modulation Scheme

Various PWM techniques for high-switching-frequency operations, including level-shifted (LS-PWM), phase-shifted (PS-PWM), and space vector (SV-PWM) techniques, are presented in the literature [36]. In this article, we are using phase disposition level-shifted pulse-width modulation (PD-LSPWM). In this scheme, by comparing the absolute value of the sinusoidal reference (|Vref|) to eight carrier signals $V_{cr1}$–$V_{cr8}$, desirable voltage levels are achieved. Comparing the reference and carrier signals provides the 17-L inverter’s comparators.

2.4. Selection of Capacitor

The capacitance of the capacitors must be carefully selected in order to accomplish self-balancing for the voltage of the capacitors and to prevent undercharging the capacitors. It would not be necessary to use an external balancing circuit in this case. As a result, two important elements should be considered; the first is connected to the amplitude of the load current and the phase difference between it and the load voltage, and the second is related to the phase difference between the load voltage and the load current. Selecting a proper capacitance also helps in reducing the cost, ripple loss, and size of the MLI. The size of a capacitor depends on the longest discharge time (LDT) of individual capacitors. Figure 5 shows the step formation of the waveform, charging and discharging sequence, and LDT of capacitors.

The maximum charge needed by the i^th capacitor can be specified by Equation (2) [37].

$$\begin{array}{c}{Q}_{C_i}={\int }_{{\varphi }_i}^{\pi -{\varphi }_i}\frac{I_{out,max}}{\omega }sin\left(\omega t\right)d\omega t\\ Q_{C_1}={\int }_{{\varphi }_8}^{\pi -{\varphi }_8}\frac{I_{out,max}}{\omega }sin\left(\omega t\right)d\omega t\\ Q_{C_2}={\int }_{{\varphi }_7}^{\pi -{\varphi }_7}\frac{I_{out,max}}{\omega }sin\left(\omega t\right)d\omega t\\ Q_{C_3}={\int }_{{\varphi }_5}^{\pi -{\varphi }_5}\frac{I_{out,max}}{\omega }sin\left(\omega t\right)d\omega t\end{array}$$

(2)

$$\begin{array}{c}{\varphi }_i={sin}^{-1}\left(\frac{2i-1}{16}\right)\end{array}$$

(3)

Here, $Q_{C_i}$ is the maximum charge accumulated by the ith capacitor where (i = 1, 2, 3); $\varphi$_i and $\pi -{\varphi }_{\mathit{i}}$ are the start and end time values of the LDT, respectively; and I_out,max is the maximum load current at the output. As a result, the capacitance values should meet the following criteria:

$$C_{i,min}\ge \frac{Q_{C_i}}{\Delta V_{in}}$$

(4)

Here, $\Delta$V_in is the ripple voltage, and, as the resistive load is responsible for the greatest amount of voltage ripple, the capacitance values must be greater than the calculated value at the resistive load. Capacitance at R-L load is calculated by Equation (5), where ⌀ is the load power factor angle, $\omega$ is the fundamental frequency, and $I_{out}$ is the output current.

$$C_{i,min}={\int }_{{\varphi }_i}^{\pi -{\varphi }_i}\frac{I_{out}}{\omega \Delta V_{in}}sin(\omega t-⌀)d\omega t$$

(5)

Further, the value of capacitors for different load resistances R_L at various ripple values is depicted in Figure 6. In Figure 6c, different possible values for capacitor C₁ for different resistive loads are shown. Similarly, in Figure 6a,b, the value of capacitors C₃ and C₂ is shown, respectively, at different resistive loads. In

Table 2. Value of different capacitors at different loads.

Ci,min (F)	R = 140 Ω; L = 0 mH			R = 80 Ω; L = 300 mH
	$\mathit{\rho }\mathbf{=}\mathbf{0.07}\mathbf{;}$	$\mathbf{0.1}\mathbf{;}$	$\mathbf{0.2}$	$\mathit{\rho }\mathbf{=}\mathbf{0.07}\mathbf{;}$	$\mathbf{0.1}\mathbf{;}$	$\mathbf{0.2}$
C1,min	1808.45	1265.9	632.96	1325.34	927.73	463.87
C2,min	3029.59	2120.70	1060.40	2220.26	1554.18	777.09
C3,min	4296.78	3007.75	1503.88	3148.93	2204.25	1102.13

, the value of C_1,min, C_2,min, and C_3,min for different ripple values at different resistive as well as inductive loads is shown.

2.5. Selection of Optimal Value of Inductor

When charging occurs in the capacitor, it takes inrush current, which may damage the switch, DC source, and even the capacitor itself. So, to avoid this situation, an inductor may be employed in the charging loop. However, it generates a new constraint for the voltage spike, which is harmful, in contrast to the breaker switch, and it restrains choosing the optimal value of the inductor. Connecting a freewheeling diode in parallel to the inductor, shown in Figure 2, resolves this problem, and an optimal value of inductance can be calculated using Equation (6) [38].

$$L_{\mathrm{opt}}=\frac{1}{{\left(2\pi f\right)}^{2}C}$$

(6)

where f refers to the fundamental frequency in Hz, and C is the capacitance. When we analyze the inrush current value with and without an inductor in the inverter circuit, it is found that, with an inductor, the input inrush current is 25 A, and it reduces to 10 A. There is a significant reduction in the input inrush current when an inductor is added to the circuit.

Figure 6. Change in capacitance in relation to resistance at various ripple levels and capacitor value (a) for $C_3$, (b) for $C_2$, and (c) for $C_1$.

Figure 6. Change in capacitance in relation to resistance at various ripple levels and capacitor value (a) for $C_3$, (b) for $C_2$, and (c) for $C_1$.

2.6. Power Loss

With the help of PLECS software (https://www.plexim.com/), an estimation of the losses caused by the suggested structure is carried out. It is possible to quantify the effectiveness of the recommended topology by making use of these losses. The thermal modeling feature of the system is what is utilized to perform the computation that determines the various losses that occur in the diodes, capacitors, and switches. This research takes into account the conduction losses (P_Loss,cond.) of all power electronic semiconductor devices, the switching losses (P_Loss,sw.), and the ESR losses (P_Loss,ESR) of the capacitors. The ripple loss that occurs in capacitors is also there, but it is not taken into account in these calculations. The calculations that are a part of this investigation are based on a method known as the fundamental switching frequency.

2.6.1. Conduction Loss

During the process of calculating the losses in conduction mode for the steady-state situation, the internal resistance of power electronic switches and diodes is one of the factors that is taken into consideration. All capacitors are meant to be equal. When taking the results, PLECS is the software that is utilized. When studying the loss of power in SCMLIs, resistive loading is regarded to be the worst-case situation; hence, this kind of load is assumed to be the load being analyzed [39].

2.6.2. Switching Loss

When different switches are turned on and off during the generation of different steps, it takes some time to turn on and off, which is known as the rise and fall time, respectively. Due to the overlapping of this, voltage and current losses are produced. Power dissipation caused by switching ON:

$$P_{S,on,k}\left\{\begin{array}{c}=f{\int }_0^{t_{on}}v\left(t\right)i\left(t\right)dt\hfill \\ =f{\int }_0^{t_{on}}\left(\frac{V_{S,k}}{t_{on}}t\right)\left(-\frac{I_k}{t_{on}}\left(t-t_{on}\right)\right)dt\hfill \\ =\frac{1}{6}f{V}_{S,k}{I}_k\hfill \end{array}\right.$$

(7)

Power dissipation caused by switching OFF:

$$P_{S,off,k}\left\{\begin{array}{c}=f{\int }_0^{t_{off}}v\left(t\right)i\left(t\right)dt\hfill \\ =f{\int }_0^{t_{off}}\left(\frac{V_{S,k}}{t_{off}}t\right)\left(-\frac{I_k^{\prime }}{t_{off}}\left(t-t_{off}\right)\right)dt\hfill \\ =\frac{1}{6}f{V}_{S,k}{I}_k^{\prime }{t}_{off}\hfill \end{array}\right.$$

(8)

where $I_k$ is the current flowing through the kth switch after switching ON, f is the switching frequency, $v\left(t\right)$ is the instantaneous voltage, $i\left(t\right)$ is the instantaneous current, and $V_{S,k}$ is the voltage of the switch in OFF state. All 13 switches’ switching losses may be calculated by multiplying the number of ON ($N_{on}$) and OFF states in a cycle ($N_{off}$) with Equations (7) and (8) following (9):

$$P_{Loss,sw}=\sum _{k=1}^{13}\left(\sum _{m=1}^{N_{on}}{P}_{S,on,km}+\sum _{m=1}^{N_{off}}{P}_{S,off,km}\right)$$

(9)

2.6.3. Capacitor Equivalent Series Resistance Loss

The equivalent series resistance of capacitors is determined by the frequency of the current passing through the capacitor, as noted in [40].

This frequency-dependent conduction loss is caused by the internal resistance of the capacitor, which, for the purposes of this discussion, is assumed to be 0.1 $\mathsf{\Omega }$ for both capacitors. The resulting thermal stress and heat dissipation from these losses can negatively impact the lifespan of the capacitors. In PLECS, each of these losses is simulated and modeled, allowing for the calculation of the total loss in the proposed design using Equation (10).

$$P_{Loss}=P_{Loss,cond.}+P_{Loss,sw.}+P_{Loss,ESR}$$

(10)

where $P_{Loss,cond.}$ is the conduction losses, $P_{Loss,sw.}$ is the switching losses, and $P_{Loss,ESR}$ is the ESR losses of the capacitor. Efficiency can be calculated using the above-calculated losses with the help of Equation (11).

$$\eta (\%)=\frac{output}{input}\times 100=\frac{output}{output+P_{Loss}}\times 100$$

(11)

Table 3 shows the conduction loss and switching loss of each switch and diode and the overall efficiency of the proposed inverter. The efficiency calculation of the proposed topology with and without a charging inductor at different loading conditions using PLECS software is depicted in Figure 7.

Table 3. Component losses while using a charging inductor.

	PSw.	PCon.	PTotal
T1	0.5871	1.304	1.887
T2	0.46	1.40	1.86
T3	0.23792	1.2167	1.44
T4	0.3472	1.237	1.57
T5	0.3572	1.1171	1.41
T6	0.4572	1.07	1.429
T7	0.25	0.67	0.92
T8	0.11	0.35	0.46
T9	0.258	0.4788	0.43
T10	0.27	0.35	0.62
T11	0.112	0.226	0.33
T12	0.107	0.223	0.32
T13	0.1018	0.223	0.325
D1			2.538
D2			1.2
D3			1.06
D4			0.7120
C1			0.812
C2			1.34
C3			2.164
Total losses			23.79
Rated power = 610 W			610
$\eta$ (%)			96.13

Table 3. Component losses while using a charging inductor.

	PSw.	PCon.	PTotal
T1	0.5871	1.304	1.887
T2	0.46	1.40	1.86
T3	0.23792	1.2167	1.44
T4	0.3472	1.237	1.57
T5	0.3572	1.1171	1.41
T6	0.4572	1.07	1.429
T7	0.25	0.67	0.92
T8	0.11	0.35	0.46
T9	0.258	0.4788	0.43
T10	0.27	0.35	0.62
T11	0.112	0.226	0.33
T12	0.107	0.223	0.32
T13	0.1018	0.223	0.325
D1			2.538
D2			1.2
D3			1.06
D4			0.7120
C1			0.812
C2			1.34
C3			2.164
Total losses			23.79
Rated power = 610 W			610
$\eta$ (%)			96.13

Figure 7. Efficiency curve for various output power.

Figure 7. Efficiency curve for various output power.

3. Comparison

Here, different topologies producing seventeen levels are compared (

Table 4. Comparison of the proposed topology in relation to other 17-level topologies.

Topology	Nlevel	NDC	Nsw	Ndio	Ncap	G	TSV	TSVpu	CF/Nlevel		Voltage THD
									$\mathit{\beta }\mathbf{=}\mathbf{0.5}\mathbf{;}$	$\mathit{\beta }\mathbf{=}\mathbf{1.5}$	(%)
[18]	17	4	12	0	0	1	44	44	10.82	21.18	-
[41]	17	1	24	8	7	8	72	9	3.97	4.5	4.5
[20]	17	4	10	0	0	1	40	40	9.41	18.82	4.38
[42]	17	4	20	4	4	4	60	20	13.64	18.35	-
[16]	17	4	10	0	0	1	38	38	9.18	18.12	-
[43]	17	4	10	0	0	1	38	38	9.18	18.12	-
[15]	17	4	12	0	0	1	48	48	11.3	22.56	2.77
[44]	17	2	18	2	4	4	24	6	5.29	6	-
[45]	17	8	20	16	0	1	40	40	35.76	54.59	5.41
[46]	17	2	24	0	4	2	24	12	6.8	8.2	-
[47]	17	1	39	0	7	8	39	4.875	5.14	5.43	-
[48]	17	4	10	0	0	1	36	36	8.94	17.41	6.17
[49]	17	4	20	0	0	1	40	40	14.12	23.53	8
[50]	17	4	16	16	4	4	44	11	13.53	16.12	4.12
[51]	17	2	12	3	3	1.6	21.5	13.43	4.31	5.9	3
[44]	17	2	18	2	4	2	40	20	6.11	8.47	-
[32]	17	1	18	7	6	8	52	6.5	3.07	3.455	-
[52]	17	1	14	4	4	2	48	24	2.82	4.23	7.86
[53]	17	1	11	1	3	4	28	7	1.73	2.14	7.98
[54]	17	1	10	4	6	2	34	17	2.26	3.26	-
[33]	17	1	13	6	4	2	11.2	5.6	2.28	2.61	7.09
[55]	17	2	18	2	6	4	28.8	7.2	1.40	1.61	-
[35]	17	1	14	4	4	4	37	7.2	2.32	2.75	-
Proposed	17	1	13	3	3	8	53	6.623	2.06	2.42	4.03

).

The factors considered for comparison include the number of levels produced (N_level), the number of DC sources used (N_DC), the number of switches used (N_sw), the number of diodes used (N_dio), the number of capacitors used (N_cap), voltage gain, and total standing voltage per unit (TSV_pu). Table 4 shows the comparison of different published topologies to the proposed topology. The topologies presented by the researchers of [14,16,18,20,43,45,48,49,50] use four and eight DC sources, respectively, for producing seventeen levels and have only one voltage gain. The number of switches is low as compared to the proposed topology, but cost and TSV_pu are very high. Some authors [44,46] used two DC sources to produce seventeen levels, but the number of switches used is larger than in the proposed topology. Now, the author of [41,47] used only one DC source, similar to the proposed topology, but the number of switches used by [41,47] is very large. The topology in [52] has more components than the proposed one and has a gain of only 2 times. A very recent article [53] presents a topology with a lesser number of components than the proposed one but offers only a 4 times boosting ability. Another factor known as the cost factor (CF) is also taken into consideration for comparison, and its estimation is carried out by Equation (12).

$$CF=\left(N_{sw}+N_{dr}+N_{dio}+N_{cap}+\beta TS{V}_{pu}\right)\times \frac{N_{dc}}{N_L}$$

(12)

where $N_{sw}$ is the number of switches, $N_{dr}$ is the number of driver circuits, $N_{dio}$ is the number of diodes used in the circuit, $N_{cap}$ is the number of capacitors, $N_L$ represents the number of levels generated, TSVpu is the total standing voltage per unit, $N_{dc}$ is the number of DC sources, and $\beta$ is the weighting factor for TSV, and its values are taken as $\beta$ = 0.5 and $\beta$ = 1.5 in the comparison table. The inverter architecture of [44,51] uses two DC sources to generate 17 levels, while the proposed one requires a single DC source. Also, despite achieving eight times voltage gain in [32], these inverters use more power electronic components, increasing losses and CF. Topologies in [33,35,55] require a larger number of components as compared to the proposed one, thus increasing the cost and complexity of the circuit. Article [54] proposes a 17-level inverter with a lesser switch count than the proposed one, but the numbers of capacitors and diodes are greater, and also TSVpu is high. Thus, the proposed design improves voltage gain while lowering stress and component counts, highlighting its importance.

4. Experimental Setup and Results

To conduct further evaluations of the proposed inverter, a seventeen-level experimental prototype was created, as seen in Figure 8, with the component characteristics specified in Table 5.

In Figure 9a, output voltage and current waveform are depicted. At first, resistive load is connected with R = 140 $\Omega$, and, after some instants, load is minimized to R = 80 $\Omega$.

It can be observed that the output current changes, but the output voltage does not change. In Figure 9b, Z₁ = 140 $\Omega$ + 300 mH is connected, and, after some instants, Z₂ = 80 $\Omega$ + 200 mH is connected. It suggests that, on reactive load too, output current changes with a phase shift, but output voltage does not change. On changing the input voltage at some instant, the behavior of the output voltage and current with load Z₁ = 140 $\Omega$ + 300 mH is as shown in Figure 10a. It can be seen that the output current remains constant while the output voltage changes. In Figure 10b, output voltage and current at frequency f_o = 200 Hz are shown. The output voltage and current at a modulation index of 0.55 are depicted in Figure 10c, which suggests that the system responds normally in the case of a low modulation index too. Output voltage THD with and without inductor is shown in Figure 11b and a, respectively. From Figure 11, it can be seen that including an inductor in the circuit reduces harmonics in the output voltage waveform. The behavior of the input current without the source inductor diode is shown in Figure 12a, while, in Figure 12b, the behavior of the input current with the use of a source inductor diode is shown. Figure 12c,e,g represent the voltage across the capacitor and charging current due to the capacitor without the use of a source inductor diodes C₁, C₂, and C₃, respectively, while Figure 12d,f,h show the behavior of capacitor voltage and charging current due to the capacitors C₁, C₂, and C₃, respectively, when the source inductor diode is connected. The source inductor diode reduces spike current significantly.

Figure 8. Experimental setup.

Figure 8. Experimental setup.

Figure 9. For dynamically changing loads, the load voltage and current waveforms range from (a) R₁ = 140 $\Omega$ to R₂ = 80 $\Omega$ and (b) Z₁ = 140 $\Omega$ + 300 mH to Z₂ = 80 $\Omega$ + 200 mH.

Figure 9. For dynamically changing loads, the load voltage and current waveforms range from (a) R₁ = 140 $\Omega$ to R₂ = 80 $\Omega$ and (b) Z₁ = 140 $\Omega$ + 300 mH to Z₂ = 80 $\Omega$ + 200 mH.

Figure 10. Output voltage and output current: (a) when input voltage changes, (b) at frequency f_o = 200 Hz, (c) at modulation index 0.55.

Figure 10. Output voltage and output current: (a) when input voltage changes, (b) at frequency f_o = 200 Hz, (c) at modulation index 0.55.

Table 5. Experimental parameters for the proposed topology.

Parameters	Rating
Vin	40 V to 30 V
fc	5 kHz
$R_1$	140 Ω
$R_2$	80 Ω
$Z_1$	140 Ω + 300 mH
$Z_2$	80 Ω + 200 mH
$C_1,C_2,C_3$	1000 μF, 1500 μF, 2200 μF
Charging inductor ($L_1$)	58 μH
Delay time	2 μs
Switches	CT60AM18F
Optocoupler	TLP250
Modulation index	0.55 to 0.99

Table 5. Experimental parameters for the proposed topology.

Parameters	Rating
Vin	40 V to 30 V
fc	5 kHz
$R_1$	140 Ω
$R_2$	80 Ω
$Z_1$	140 Ω + 300 mH
$Z_2$	80 Ω + 200 mH
$C_1,C_2,C_3$	1000 μF, 1500 μF, 2200 μF
Charging inductor ($L_1$)	58 μH
Delay time	2 μs
Switches	CT60AM18F
Optocoupler	TLP250
Modulation index	0.55 to 0.99

Figure 11. Output voltage THD (a) without inductor, (b) with inductor.

Figure 11. Output voltage THD (a) without inductor, (b) with inductor.

Figure 12. (a) Input source current without source inductor diode, (b) input source current with source inductor diode, (c) current and voltage across C₁ without source inductor diode, (d) current and voltage across C₁ with source inductor diode, (e) current and voltage across C₂ without source inductor diode, (f) current and voltage across C₂ with source inductor diode, (g) current and voltage across C₃ without source inductor diode, and (h) current and voltage across C₃ with source inductor diode.

Figure 12. (a) Input source current without source inductor diode, (b) input source current with source inductor diode, (c) current and voltage across C₁ without source inductor diode, (d) current and voltage across C₁ with source inductor diode, (e) current and voltage across C₂ without source inductor diode, (f) current and voltage across C₂ with source inductor diode, (g) current and voltage across C₃ without source inductor diode, and (h) current and voltage across C₃ with source inductor diode.

5. Conclusions

This article introduces an implementation of a revolutionary SC-based, step-up, single-source inverter architecture. The suggested inverter produces a 17-level output and is controlled by a phase disposition pulse-width modulation approach. The suggested MLI has many benefits, including voltage boosting, high efficiency, and cheap cost as a result of the decreased number of power switches, as well as low-voltage stress on the switches, which boosts the inverter’s dependability by increasing its reliability. A comparison analysis demonstrating the advantages of the proposed MLI over other MLIs that have recently been established has been provided. Experimental validation was performed to evaluate the suggested topology’s operation and stability under dynamic resistive- and inductive-load-switching situations. Also, we discussed the performance of the suggested topology with and without inductor diode findings.