Multi-Functional Device Based on Superconducting Magnetic Energy Storage

Abstract

Presently, there exists a multitude of applications reliant on superconducting magnetic energy storage (SMES), categorized into two groups. The first pertains to power quality enhancement, while the second focuses on improving power system stability. Nonetheless, the integration of these dual functionalities into a singular apparatus poses a persistent challenge. Considering this, this paper proposes a multi-functional device based on SMES, encompassing both power quality enhancement and power system stability improvement capabilities. It incorporates power quality enhancement features such as current harmonic filtering, active power smoothing, reactive power compensation, and critical load protection, while also furnishing virtual inertia to bolster grid frequency. Simulation results validate the effectiveness of the proposed methodologies.

1. Introduction

Superconducting magnetic energy storage (SMES) is an electrical apparatus designed to directly accumulate electromagnetic energy utilizing superconducting coils (SCs), subsequently releasing stored energy to the power grid or other loads as required. Comprising devices capable of swift energy storage and discharge, SMES leverages the minimal losses and rapid response attributes of superconducting magnets. By capitalizing on the zero-resistance property of superconductors, SMES facilitates lossless energy storage within SCs, thereby achieving objectives such as enhancing power quality and grid stability [1]. Furthermore, it facilitates rapid exchange of active and reactive power with external power systems via power electronic converters, thereby augmenting power system stability and enhancing the quality of power supply [2,3].

The SMES system comprises four primary components: SCs, power conditioning system (PCS), cryogenic system, and monitoring system, with SC and PCS being pivotal. The PCS facilitates energy conversion between the SC and the grid, serving as the conduit for power exchange between energy storage devices and the grid [4,5]. Based on circuit topology, PCS can be categorized into two fundamental structures: current source converter (CSC) based PCS [6] and voltage source converter (VSC) based PCS [7,8,9]. The DC side of the CSC is directly linked to the SC, while the DC side of the VSC necessitates connection to the SC via a chopper. SC serves as the nucleus of SMES, with its rated energy and structure dictating magnet size. The advancement in high-temperature superconducting (HTS) materials technology has made SMES applications a prominent subject, owing to HTS magnets’ attributes such as zero resistance and high current density [10,11,12,13].

In the realm of SMES applications, they broadly fall into two categories:

(1)

Enhancing power system stability: This application domain seeks to fortify the stability and reliability of power systems utilizing SMES. By storing and dispensing electrical energy, SMES systems aid in balancing energy flow in power systems, thereby mitigating voltage and frequency fluctuations, consequently bolstering power system stability [14,15,16,17].

(2)

Improving power quality: This category predominantly utilizes SMES systems to ameliorate power quality. As a fast-response energy storage device, SMES injects active and reactive power into the grid swiftly, within a single cycle [18]. Through energy storage and release, SMES mitigates current and voltage fluctuations, diminishes harmonics, and ameliorates sags, thereby enhancing power quality [19,20,21,22,23,24].

These two application types underscore the substantial role of SMES systems in power systems. They enhance system performance and efficiency, elevate power supply quality, and fortify power system stability. Multiple applications of SMES are listed in [25,26,27]. However, these applications can only achieve certain kinds of functions. Currently, no SMES devices can simultaneously improve the stability and power quality of the power system. Nonetheless, integrating the aforementioned functions into a unified device remains a challenge. Hence, this paper proposes a multifunctional device based on SMES, concurrently enhancing power quality and power system stability, capable of active power smoothing, current harmonic and reactive power compensation, inertia support, and dynamic voltage restoration.

The paper’s structure unfolds as follows: operational principles and topology design methodology are elucidated in Section 2, the system control scheme is delineated from Section 3, Section 4 and Section 5, simulation results and comparison are presented and assessed in Section 6 and Section 7, and conclusions are drawn in Section 8.

2. Operational Principle and Topology Design Methodology

The SMES stores electrical energy in the magnetic field of the SC and releases the energy to the grid when needed. Due to the zero resistance and high current density characteristics of the SC, the SMES has outstanding performance such as high efficiency and high power density. The operation of SMES can be divided into three main stages: 1. Charging stage: In this stage, the DC power supply charges the SC to increase its magnetic field so as to store the electrical energy. 2. Energy storage stage: In this stage, the SC stores the magnetic energy and the SC current remains stable. Due to the zero resistance of the superconductor, the magnetic field does not decay. 3. Discharge stage: When the stored energy needs to be released, the SC is discharged and magnetic energy is released with declining SC current.

The modular SMES is depicted in Figure 1. In this study, the PCS adopts a modular design strategy aimed at augmenting power capacity. The PCS is delineated into two primary segments: the inverter modules and the chopper modules. These segments are further subdivided into eight groups, each comprising one chopper module and three inverter modules, interconnected via the DC bus. The outputs of the inverter modules are interconnected in parallel to enhance the current rating, subsequently interfacing with the grid through an isolation transformer. The outputs of the chopper modules are connected in series to amplify voltage rating, and then linked in series with the SC. The inverter module assumes multiple functions including inertia support, active current harmonics filtering, active power smoothing, reactive power compensation, and dynamic voltage restoration, whereas the chopper module is responsible for charging and discharging the SC. Additionally, the SMES interfaces with the grid through three sets of capacitors, inductors, and thyristors, while the load operates in parallel with the SMES.

The equivalent circuit is illustrated in Figure 2, where U_g represents the gird and U_c represents grid-side capacitor. The PCS of SMES is represented as the voltage source (U_v), while the load is depicted as the current source (I_L). During regular operation, the thyristors are activated. The magnitude and phase of the capacitor voltage are regulated by SMES to manage active and reactive power interchange with the grid. In the event of a grid fault, the thyristors are deactivated. The capacitor voltage is then controlled to maintain its pre-grid fault value, thereby safeguarding the critical load.

The toroidal SC has the good merit of a low leakage magnetic field, which is more suitable for energy storage. An SC made of YBCO superconductor tape was designed in [28], whose major parameters are listed in

Table 1. Preliminary parameters of the toroidal HTS magnets.

Name	Unit	Value
Maximum operating current	A	1600
Maximum operating voltage	kV	10
Number of magnet modules	\	16
Maximum magnetic field on coil surface	T	5.91
Maximum vertical magnetic field on coil surface	T	3.55
Coil self-induction	H	6.366
Maximum energy storage	MJ	11.9
Maximum effective output energy	MJ	10
Cooling mode	\	Liquid hydrogen immersion cooling

.

Based on the SC parameters, the SMES PCS design procedure is:

2.1. Select the PCS Rated Voltage

Since the maximum operating current is 1600 A and the total energy stored in the SC is:

$$E=\frac{1}{2}L{I}^2=8.15 \mathrm{MJ},$$

(1)

where L is the inductance of the SC. The PCS is designed to be able to output the rated power even when the energy storage in the SC drops to 10% of its rated value.

When energy is 10% of the rated value, the current of the SC is:

$$I_{\mathrm{SC},\min }=\sqrt{\frac{0.1E}{\frac{1}{2}L}}\approx 500 \mathrm{A},$$

(2)

The SC total rated voltage should satisfy the flowing inequation:

$$U_{\mathrm{SC},\mathit{total},rated}\ge \frac{P_{rated}}{I_{\mathrm{sc},\min }},$$

(3)

Since the rated PCS is designed to be 5 MW, the $U_{SC,\mathit{total},rated}$ should be larger than 10 kV.

2.2. Design of the L Filter Inductance

The inverter module is connected to the secondary side of the transformer through an L filter. The L filter is used to filter out switching harmonics, whose inductance is determined by the maximum allowable current ripple:

$$\Delta i_{L,\max }=\frac{V_{DC}}{4L_f}{T}_{sw},$$

(4)

where T_sw is the switching period, $V_{DC}$ is the DC link voltage, and $L_f$ is inductance of the L filter. Since phase shift modulation method is used for 8 inverter modules, the total current ripple is 1/8 of a single module. Therefore $\Delta i_{L,\max }$ can be relatively high to save the inductor cost.

2.3. Design of the Capacitance of the DC Link Capacitor

The DC link capacitor is used to filter out the DC link voltage ripples. Since the rated SC current is 1600 A, which is relatively high, the chopper switching frequency is designed to be 1/10 (1000 Hz) of the inverter module to reduce the switching losses. Due to the low switching frequency, the voltage ripple on the DC link is mainly due to the charging and discharging of the DC link capacitor by the SC current through the chopper. The highest DC link voltage ripple occurs when the chopper outputs maximum power. The DC link ripple magnitude can be expressed as:

$$\Delta V_{dc}=\frac{I_{sc}}{C}D{T}_{sc},$$

(5)

where I_sc represents the rated SC current, T_sc represents the chopper switching period, and D represents the duty cycle.

The chopper output power can be expressed as:

$$P_{\mathrm{chopper}}=V_{dc}{I}_{sc}D,$$

(6)

The chopper outputs maximum power when the inverter reaches its rated power. The maximum chopper power is:

$$P_{\mathrm{chopper},\max }=\frac{P_{PCS}}{n},$$

(7)

where $P_{PCS}$ is the PCS rated power, and n is the number of the sets of power modules, which is eight here.

From (5) to (7), we have:

$$C=\frac{P_{PCS}{T}_{sc}}{n\Delta U_{dc}{U}_{dc}},$$

(8)

When $\Delta U_{dc}$ is taken as 1.5% U_dc, C is calculated as about 50 mF.

2.4. Design of the Inductance of the Grid-Side Inductor

When the angle $\delta$ between the grid and capacitor voltage is small enough, the output active power of SMES is linear with $\delta$:

$$\frac{U_g{U}_c}{X}\delta =P_{PCS},$$

(9)

where $U_g$ represents the grid voltage magnitude, $U_c$ represents the capacitor voltage magnitude, X represents line impedance ($X=j\omega L_g$, $L_g$ is the grid inductance).

L_g is selected to be 3.2 mH to make maximum $\delta$ less than 0.1.

2.5. Design of the Capacitance of the Grid-Side Capacitor

Since most of the inverter side ripple current flows through the capacitor, voltage fluctuations occur on the capacitor. The capacitance of the capacitor can be selected according to:

$$C_s\ge \frac{\Delta i_{L,\max }}{2\pi f_{sw}\Delta U_C},$$

(10)

where $\Delta U_C$ is the maximum voltage ripple, f_sw represents the equivalent switching frequency, which is 8 times that of single module with the phase shift modulation.

The capacitance is calculated on the secondary side of the transformer. Since the capacitor is installed on the primary side of the transformer, the capacitance can be calculated as:

$$C_p\ge \frac{C_s}{n^2},$$

(11)

According to the above-mentioned parameter calculation method, the parameters of SMES are calculated and listed in

Table 2. Main parameters of SMES.

Name	Unit	Value
Three-phase DC voltage source (line voltage RMS)	kV	10
Grid-side inductance	mH	3.2
Grid-side resistance	R	0.2
Grid-side capacitance	μF	10
DC capacitance	mF	50
Inductance of SC	H	6.366
Filter inductance	mH	0.5
Filter resistance	R	0.0314

.

3. Inverter Outer Power Control Loop

The system control strategy of SMES can be primarily categorized into an outer power loop and an inner voltage and current control loop. The power control loop is primarily utilized for active power smoothing, grid frequency inertial support, and reactive power compensation. Meanwhile, the inner voltage and current loops are predominantly employed for current harmonics and dynamic voltage sag compensation.

3.1. Active Power Loop

The power and frequency control strategy on the grid side employs the virtual synchronous generation (VSG) control method [29,30,31,32]. The outer loop encompasses active power and reactive power control. The model of the synchronous generator can be expressed as:

$$\{\begin{array}{c}J\frac{d\omega }{dt}=\frac{P_m-P_e}{{\omega }_N}-D_P\left(\omega -{\omega }_N\right)\\ \frac{d\theta }{dt}=\omega \end{array},$$

(12)

where J is rotational inertia, $\omega$ is rotor angular velocity, $P_m$ is mechanical power, $P_e$ is electromagnetic power, D_P is damping coefficient, ${\omega }_N$ is rotor rated angular velocity and θ is power angle.

Figure 3 is the equivalent circuit diagram of VSG in grid-connected operation, where $R_g$ represents the grid resistance and $L_g$ represents the grid inductance.

The instantaneous power model is used in this paper. The dynamic of the grid inductor current (i_g) can be expressed under the d-q reference frame as:

$$\frac{d{i}_g}{dt}=(-\frac{R_g}{L_g}+j\omega )i_g+\frac{1}{L_g}(u_c-u_g),$$

(13)

where $u_c$ and $u_g$ are the instantaneous capacitor and grid voltage.

The grid complex power ($s_g$) can be expressed as:

$$s_g=u_c{i}_g^{*}=U_c{I}_g{e}^{j\delta },$$

(14)

where $I_g$ is the grid inductor current magnitude.

Combining Equations (13) and (14), the dynamic model of $s_g$ is:

$$\frac{d{s}_g}{dt}=\frac{d{u}_c}{dt}{i}_g^{*}+\frac{d{i}_g^{*}}{dt}{u}_c=\frac{d{u}_c}{dt}{i}_g^{*}+[(-\frac{R_g}{L_g}+j\omega )i_g+\frac{1}{L_g}(u_c-u_g){]}^{*}{u}_c,$$

(15)

The capacitor voltage is controlled to be a steady value, so $\frac{d{u}_c}{dt}$ can be approximately as 0, Equation (15) turns to:

$$\frac{d{s}_g}{dt}=(-\frac{R_g}{L_g}+j\omega )s_g+\frac{1}{L_g}{(u_c-u_g)}^{*}{u}_c,$$

(16)

When in the steady case, $s_g$ is expressed as:

$$s_g=\frac{u_c^{*}{u}_c-u_g^{*}{u}_c}{R_g-j\omega L_g}=\frac{{U_c}^2-U_c{U}_g{e}^{\delta }}{R_g-j\omega L_g}=\frac{{U_c}^2-U_c{U}_g\cos \delta -j{U}_c{U}_g\sin \delta }{R_g-j\omega L_g},$$

(17)

Given that the phase angle difference between the grid and capacitor is approximately 0 and the grid resistance can be disregarded, Equation (17) can be simplified as:

$$s_g=p_g+q_g=\frac{U_c{U}_g\delta }{X}+j\frac{U_c(U_c-U_g)}{X},$$

(18)

where X represents line impedance.

So, the expression of the output active power is as follows:

$$P_e=\frac{U_c{U}_g\delta }{X},$$

(19)

To smooth the active power of the load, a first-order low-pass filter is applied and utilized as the reference power of VSG. Based on Equations (12) and (19), the block diagram of active power is depicted in Figure 4, where ${\omega }_g$ and ${\omega }_c$ are the grid frequency and the cutoff frequency of the first-order low-pass filter, respectively.

In Figure 4, the closed-loop transfer function between $P_{ref}$ and $P_e$ is expressed as:

$$G_c=\frac{\frac{K}{J{\omega }_g}}{s^2+\frac{D_P}{J}s+\frac{K}{J{\omega }_g}},$$

(20)

where K is $\frac{U_C{U}_g}{X}$.

From Equation (20), the VSG-based power loop is a two-order system. The following relation can be obtained:

$$\{\begin{array}{c}\frac{K}{J{\omega }_g}={{\omega }_n}^2\\ \frac{D_P}{J}=2\xi {\omega }_n\end{array},$$

(21)

where ${\omega }_n$ refers to natural angular frequency, and $\xi$ refers to the damping ratio.

The damping ratio is designed to be 0.707, so the parameters D_P and J have the following relationship:

$$D_P=\sqrt{\frac{2KJ}{{\omega }_g}},$$

(22)

The formula for the kinetic energy of a rotating object is as follows:

$$S_{n}t=\frac{1}{2}J{\omega }^2,$$

(23)

where $S_n$ represents the SMES rated power, t represents energy storage time, and $\omega$ represents the VSG angular velocity. In this paper, $S_n$ is designed to be 5 MW, t is 5 s, and $\omega$ is grid frequency. Therefore, parameter J can be calculated.

As can be seen in Figure 4, there are two inputs in the system, which are the load power $P_L$ and grid frequency ${\omega }_g$. From Figure 4, the grid power $P_e$ can be described as:

$$P_e=G_{rp}(s)P_L+G_{\omega p}(s){\omega }_g,$$

(24)

According to Figure 4, $G_{rp}(s)$ and $G_{\omega p}(s)$ are shown as follows:

$$G_{rp}(s)=\frac{K}{({\omega }_{N}J{s}^2+{\omega }_N{D}_{P}s+K)(\frac{s}{{\omega }_c}+1)}=\frac{\frac{K}{J{\omega }_N}}{(s^2+\frac{D_P}{J}s+\frac{K}{J{\omega }_N})(\frac{s}{{\omega }_c}+1)},$$

(25)

$$G_{\omega p}(s)=\frac{K{\omega }_{N}Js+K{\omega }_N{D}_P}{{\omega }_{N}J{s}^2+{\omega }_N{D}_{P}s+K},$$

(26)

In Equation (25), the value of ${\omega }_c$ is set to 1 Hz (6.28 rad/s), since ${\omega }_c\ll {\omega }_n$ (${\omega }_n$ is 70.7 rad/s from Equation (21)), $-{\omega }_c$ is the dominant pole of the system. Therefore, the dynamic response of $G_{rp}(s)$ is mainly influenced by the first-order low-pass filter, and the low-pass filter cutoff frequency mainly determines the load active power smoothing performance.

3.2. Reactive Power Loop

To simulate the reactive voltage regulation function of the system, the excitation controller of the VSG achieves control of the output voltage by detecting and managing the system’s output reactive power. To streamline the control process, a first-order inertial link is utilized for modeling. Consequently, the excitation formula of VSG is obtained as:

$$K_q\frac{d{U}_r}{dt}=Q_{ref}-Q_e,$$

(27)

where K_q is the reactive power–voltage inertia coefficient, U_r is the virtual electromotive force, Q_ref is the reference reactive power, Q_e is the reactive power output. The reference reactive power Q_ref is set to zero, so the total reactive power of the SMES and load is zero. The reactive power of the load is inherently compensated by the SMES.

From Equation (18), the expression of the output reactive power is as follows:

$$Q_e=\frac{U_c\Delta U}{X},$$

(28)

where $\Delta U=U_c-U_g$ is the voltage difference between the capacitor and grid, which can be used to regulate the reactive power.

Based on Equations (27) and (28), the block diagram of reactive power is shown in Figure 5. A simple integral regulator is used, and the final output is the reference value of the capacitor voltage (U_cref).

The closed-loop transfer function for reactive power control is:

$$G_{cq}=\frac{1}{\frac{K_{q}Xs}{U_c}+1},$$

(29)

It is clear that $G_{cq}$ is a first-order system, whose bandwidth is:

$${\omega }_h=\frac{U_c}{K_{q}X},$$

(30)

As evident from Equation (30), the smaller the parameter $K_q$, the wider the bandwidth of the system, leading to faster response speed.

4. Inverter Inner Voltage and Current Control Loop

4.1. Realization of Voltage Sag Compensation

Upon occurrence of a grid fault, the gate signal of the thyristors is deactivated, and the capacitor voltage is regulated to remain unchanged to safeguard the load. A dual-loop control strategy is employed in the capacitor voltage control, comprising inner loop current control and outer loop voltage control, as illustrated in Figure 6. In the diagram, $G_{PI}$ represents the proportional and integral (PI) controller for inner loop current control, $G_{PIR}$ represents the proportional, integral, and resonant (PIR) controller for outer loop voltage control. L₁ denotes the inverter-side inductance, L₂ represents the grid-side inductance, C stands for the grid-side capacitor, G_d indicates the inverter delay, and s represents the Laplace operator. G_d can be expressed as $\frac{1}{T_{d}s+1}$, where T_d represents the computational and pulse width modulation delay time of the inverter.

To design the PI regulator parameters, the PI regulator is written in the zero-pole form as:

$$G_{PI}=K_{iP}+\frac{K_{iI}}{s}=K_{iP}\frac{\tau s+1}{\tau s},$$

(31)

where $K_{iP}$ and $K_{iI}$ are the proportional and integral control gains of the inner loop current control, $\tau$ is the time constant corresponding to the zero point in the PI regulator.

The conventional type II system design method is employed to design the inner current loop. From Figure 6, the open-loop transfer function of the inner current loop is:

$$W_{oi}(s)=\frac{K_{iP}(\tau s+1)}{\tau L_1{s}^2(T_{d}s+1)},$$

(32)

As observed from Equation (32), there are two parameters to be determined: $K_{iP}$ and $\tau$, which adds complexity to parameter selection. For ease of analysis, a new variable $h=\frac{\tau }{T_d}$ is introduced. To enhance the control dynamics of the inner current loop while considering overshoot, oscillation amplitude, etc., h is chosen to be 5 as suggested [33]. Given a specific h, the following relationship holds to minimize the peak value of the closed-loop amplitude.

$$\frac{K_{iP}}{\tau L_1}=\frac{h+1}{2{\tau }^2},$$

(33)

From Equation (33), we have:

$$K_{iP}=\frac{3L_1}{5T_d},$$

(34)

$$K_{iI}=\frac{K_{iP}}{\tau }=\frac{3L_1}{25{T_d}^2},$$

(35)

When designing the PIR parameters of the outer loop, the PI parameters are first designed. The open-loop transfer function of the outer voltage loop is:

$$G(s)=\frac{W_{oi}\frac{1}{C(s+j{\omega }_0)}}{1+W_{oi}+\frac{1}{L_{1}C{(s+j{\omega }_0)}^2}+\frac{1}{L_{2}C{(s+j{\omega }_0)}^2}+\frac{1}{L_{2}C{(s+j{\omega }_0)}^2}{W}_{oi}},$$

(36)

In order not to influence the control of the inner loop, the bandwidth of the outer loop is set to one-third of the inner loop bandwidth and the phase margin is set to 60 degrees. The frequency response of the outer PI controller at the control bandwidth can be expressed as $G_{pi}(j\omega )=K_{vp}+\frac{K_{vi}}{j{\omega }_v}$, where ${\omega }_v$ refers to the bandwidth of the outer loop, $K_{vp}$ and $K_{vi}$ are the proportional and integral control gains of the outer loop voltage control. The amplitude ($\left|G_{pi}\right|$) and phase angle ($\varphi (G_{pi})$) of the PI controller transfer function are calculated as $\sqrt{{K_{vp}}^2+\frac{{K_{vi}}^2}{{{\omega }_v}^2}}$ and $\arctan (\frac{{-K}_{vi}}{K_{vp}{\omega }_v})\frac{180°}{\pi }$, respectively. To make 60° phase margin, the parameters of the outer loop PI controller can be solved by the following two equations:

$$\{\begin{array}{l}\left|G(j\omega )\right|\left|G_{pi}(j\omega )\right|=1\hfill \\ 180°+\varphi G(j\omega )+\varphi G_{\mathrm{pi}}(j\omega )={60}^{°}\hfill \end{array},$$

(37)

where $\left|G(j\omega )\right|$ refers to the amplitude of the outer open loop transfer function, and $\varphi G(j\omega )$ refers to the phase angle of the outer open loop transfer function.

The resonant controller is primarily designed to enhance 5th and 7th order harmonic tracking performance, with its resonant frequency being 6th order in the d-q reference frame. The expression of the resonant controller is as follows:

$$G_R=\frac{2K_r{\omega }_{c}s}{s^2+2{\omega }_{c}s+{{\omega }_0}^2},$$

(38)

where $K_r$ represents resonant gain, ${\omega }_c$ represents resonant bandwidth, and ${\omega }_0$ represents resonant frequency. In this paper, the resonant frequency is chosen to be six times the fundamental frequency to simultaneously suppress the 5th and 7th order harmonics. The gain of the resonance controller is set to be as large as possible to enhance harmonic tracking performance, provided the phase angle margin exceeds 30 degrees. By setting the resonance gain to 2 and the resonance bandwidth to 0.5 times the fundamental frequency, the phase angle margin is calculated as 39.4 degrees, fulfilling the design criteria.

The expression of PIR is shown below:

$$G_{PIR}=K_{vp}+\frac{K_{vi}}{s}+G_R,$$

(39)

4.2. Realization of Current Harmonic Compensation

To validate the harmonic current compensation performance, impedance analysis method is used [34].

The dual loop control diagram is shown in Figure 7.

With the impedance modeling method, the inverter is represented by the inverter parallel output impedance $Z_0$, the utility grid is modeled by the voltage source and the grid impedance $Z_g$, the grid is modeled as voltage source V_g, and the load is modeled as a current source I_L. The equivalent circuit is shown in Figure 8.

To simplify the impedance analysis, a series of equivalent transformations are performed, which transfers the control diagram in Figure 7 into the ones shown in Figure 9.

Step 1: Move the feedback node of Figure 7 from the output of $G_d$ to the input of $G_{PIR}$, yielding Figure 9a.

Step 2: Merge the two feedback loops in Figure 9a into $\frac{1+G_{PI}{G}_d{G}_{PIR}}{G_{PI}{G}_d{G}_{PIR}}$, and merge the current inner loop into $G_1$, yielding Figure 9b.

Step 3: Move the feedback node of Figure 9b from the input of $G_1$ to its output, yielding Figure 9c.

Step 4: Merge the feedback loop and $\frac{1}{Cs}$ in Figure 9c into $G_2$, yielding Figure 9d.

The resulting transfer function of G₁(s) and G₂(s) can be expressed by:

$$G_1=\frac{G_{PI}{G}_d}{G_{PI}{G}_d+L_{1}s}+G_{PIR},$$

(40)

$$G_2=\frac{G_{PIR}{G}_{PI}{G}_d}{G_{PIR}{G}_{PI}{G}_{d}Cs+G_{PIR}{G}_{PI}{G}_d{G}_1+G_1},$$

(41)

The output impedance of the inverter and grid can be defined as:

$$Z_0=\frac{U_C}{-I_g}=G_2,$$

(42)

$$Z_g=L_{2}s,$$

(43)

Based on Equations (42) and (43), the following bode diagram is plotted (Figure 10), where the blue and red lines are the impedance of Z₀ and Z_g, respectively.

As depicted in the figure, in the high-frequency domain, the harmonic impedance of the grid notably exceeds that of the inverter. Consequently, the majority of harmonic current will flow into the inverter rather than the grid, enabling the realization of the harmonic current compensation function.

5. Chopper Module Control

The chopper module is mainly designed to control the DC bus voltage, and its control block diagram is as follows Figure 11.

Where PI-2 represents the PI controller for voltage control, C_b represents the DC capacitor, U_bref represents the reference DC link voltage and U_b represents the DC link voltage.

According to the typical type II system design method, which is mentioned in the preceding paragraph, the parameters of the PI-2 controller are designed as follows:

$$K_{cP}=\frac{3C_b}{5T_d},$$

(44)

$$K_{cI}=\frac{3C_b}{25{T_d}^2},$$

(45)

where $K_{cP}$ and $K_{cI}$ are the proportional and integral control gains of chopper.

6. Simulation Results

Simulations are conducted to showcase the system’s performance in inertia support, active current harmonics filtering, reactive power compensation, active power smoothing, and dynamic voltage sag compensation.

Figure 12 illustrates the waveform of the active power absorbed from the grid following a 0.1 Hz grid frequency step increment. As the grid frequency undergoes a sudden change, the phase angle difference between the grid and the inverter experiences a significant increase. Consequently, the SMES absorbs step active power to mitigate the grid frequency change, thereby providing inertia support.

Figure 13 displays the waveform of SC current in inertia support. At 0–1 s, active power smoothing has a transient process when it has just started and has not yet entered the steady state. At this time, the load power is slightly greater than the power absorbed from the grid, so SMES provide energy for the load and the SC current slowly decreases. At one second, the active power emitted by the grid notably escalates, while the active power of the load remains approximately constant at 2 MW. Consequently, the SMES absorbs power from the grid, causing the current of the SC to rise. Between approximately 1.1 and 2.5 s, the active power emitted by the grid gradually diminishes but remains higher than that of the load. Consequently, the power absorbed by the SMES from the grid decreases, while the SC current continues to increase at a decreasing rate. After 2.5 s, the active power of the grid and the load almost equalize, resulting in a stable SC current.

Figure 14 illustrates the impact of current harmonic compensation. The upper half of the figure presents the waveform of the grid current after filtering, while the lower half displays the current waveform of the load. Nonlinear loads within the load result in noticeable harmonic distortions. Figure 15 shows the harmonic distortion rate of load current and Figure 16 shows the harmonic distortion rate of grid current. The total harmonic distortion (THD) of the load current is as high as 11.66%, failing to meet the fundamental requirements of the grid. However, following active filtering of the load current, the grid harmonic distortion is reduced to 3.82%, meeting the stipulated grid code requirements.

Figure 17 depicts the simulation waveform for reactive power compensation. The magenta line represents the reactive power of the load, while the blue line illustrates the reactive power of the grid. A step change in load power occurs between 1 and 2 s. Owing to the presence of harmonics, the reactive power of the grid exhibits significant fluctuations. Following compensation, the average reactive power injected into the grid is reduced to 0. The fluctuation in reactive power is significantly dampened due to current harmonic compensation. By greatly reducing the harmonic content, the fluctuation amplitude of the reactive power is diminished. Upon a step power change in the load, there is a slight transient oscillation in the reactive current injected into the grid. However, it quickly diminishes to 0, indicating rapid reactive power regulation speed within the system.

Figure 18 and Figure 19 display the simulation waveforms of active power smoothing. In Figure 18, the magenta curve represents the active power of the load, which jumps from 2 MW to 5 MW in 1 s and returns to 2 MW in 2 s. The blue curve depicts the active power provided by the grid. Despite the step change in the load’s active power, the active power supplied by the grid remains much smoother, effectively mitigating the impact of dynamic load fluctuations on the grid. Figure 19 illustrates the current waveforms of the load and the grid during the step process. It is evident that the rate of change in the grid current waveform is much lower than that of the load, thereby reducing the impact on the grid.

Figure 20 illustrates the SC’s current waveform during active power smoothing. Between 1 and 2 s, the load’s power remains at 5 MW, while the grid’s power gradually increases from 2 MW to 5 MW. Consequently, the SMES provides power for the load, resulting in a decrease in SC current. Between 2 and 3 s, the load’s power is 2 MW, while the grid’s power decreases from 5 MW to 2 MW. In this scenario, the SMES absorbs the differential power, causing the SC current to rise.

Figure 21 illustrates the simulation waveform during a voltage sag event. Between 0.1 and 0.2 s, the amplitude of the grid voltage decreases to 50% of the normal value. Upon detection of the grid fault, the thyristors are turned off. SMES supports the load voltage by controlling the capacitor voltage to match the value before the grid fault. Consequently, the amplitude of the load voltage remains unchanged, with only a minor disturbance observed during the sudden grid voltage sag, effectively realizing the critical load protection function.

Figure 22 and Figure 23 display the active power and the SC’s current waveform during this process. In Figure 22, the magenta line represents the active power of the load, while the blue line indicates the active power of the grid. At 0.1 s, the thyristors are deactivated, causing the grid power to sharply decrease to 0. Consequently, SMES supplies power to the load, resulting in a decrease in SC current (as shown in Figure 23). At 0.2 s, the grid fault is cleared, and the thyristors are reactivated to reconnect SMES and the load with the grid. Following this, the active power of the load remains unchanged, while the active power provided by the grid gradually increases but remains lower than the power of the load. Therefore, SMES needs to provide compensational power for the load. Since the VSG-controlled SMES requires a transient process to follow the reference value (which is the first-order filtered load power), the load power gradually transitions from being provided by SMES to being provided by the grid. Consequently, the SC current continues to decrease at a decreasing rate.

7. Performance Comparison with the Existing Methods

Table 3. Functional comparison of SMES devices.

Name	Function	Paper
Enhancing power system stability	Inertia support	[14,17]
Improving power quality	Critical load protection	[35]
	Active current harmonics filtering	[19,35]
	Active power smoothing	[23,36]
	Reactive power compensation	[23,24,35]

lists the applications and functions of SEMS devices in recent years. It can be seen that most SMES devices can only achieve 1–2 functions, and none of them have all the functions listed in the table, resulting in low cost-effectiveness and low utilization rate of SMES devices. The SMES equipment proposed in this paper has all the functions, which greatly improve the equipment’s utilization rate.

8. Conclusions

In this paper, a multi-functional device based on SMES is explored, which not only bolsters the stability of the power system but also notably enhances power quality. The proposed approach enables the realization of grid frequency support, active power smoothing, and reactive power compensation functions through the outer power control loop. Additionally, the inner voltage and current control loops facilitate the realization of grid voltage sag and harmonic current compensation functions. By integrating multiple functions into a single equipment, the cost-effectiveness of SMES can be substantially enhanced. Simulation results validate the effectiveness of the proposed approaches.